Intersil Corporation HS-80C86RH Datasheet

September 1995

HS-80C86RH

Radiation Hardened

16-Bit CMOS Microprocessor

Features

• Radiation Hardened

- Latch Up Free EPl-CMOS

- Total Dose >100K RAD (Si)

- Transient Upset >10

• Low Power Operation

- ICCSB = 500µA (Max)

- ICCOP = 12mA/MHz (Max)

• Pin Compatible with NMOS 8086 and Intersil 80C86

• Completely Static Design DC to 5MHz

• 1MB Direct Memory Addressing Capability

• 24 Operand Addressing Modes

• Bit, Byte, Word, and Block Move Operations

• 8-Bit and 16-Bit Signed/Unsigned Arithmetic

- Binary or Decimal

- Multiply and Divide

• Bus-hold Circuitry Eliminates Pull-up Resistors for CMOS Designs

• Hardened Field, Self-Aligned, Junction-Isolated CMOS Process

RAD (Si)/s

Description

The Intersil HS-80C86RH high performance radiation hardened 16-bit CMOS CPU is manufactured using a hardened ﬁeld, self aligned silicon gate CMOS process. Two modes of operation, MINimum for small systems and MAXimum for larger applications such as multiprocessing, allow user conﬁguration to achieve the highest performance level. Industry standard operation allows use of existing NMOS 8086 hardware and software designs.

• Single 5V Power Supply

• Military Temperature Range -35

• Minimum LET for Single Event Upset -6MEV/mg/cm (Typ)

C to +125oC

Ordering Information

PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE

HS1-80C86RH-8 -35oC to +125oC Intersil Class B Equivalent 40 Lead Braze Seal DIP

HS1-80C86RH-Q -35oC to +125oC Intersil Class S Equivalent 40 Lead Braze Seal DIP

HS9-80C86RH-8 -35oC to +125oC Intersil Class B Equivalent 42 Lead Braze Seal Flatpack

HS9-80C86RH-Q -35oC to +125oC Intersil Class S Equivalent 42 Lead Braze Seal Flatpack

HS9-80C86RH-SAMPLE 25oC Sample 42 Lead Braze Seal Flatpack

HS1-80C86RH-SAMPLE 25oC Sample 40 Lead Braze Seal DIP

HS9-80C86RH-PROTO -35oC to +125oC Prototype 42 Lead Braze Seal Flatpack

HS1-80C86RH-PROTO -35oC to +125oC Prototype 40 Lead Braze Seal DIP

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207

856

Spec Number 518055

File Number 3035.1

Pinouts

HS-80C86RH

HS-80C86RH 40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835, CDIP2-T40

TOP VIEW

MAX MIN

GND AD14 AD13 AD12 AD11 AD10

AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

NMI

INTR

CLK

GND

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

VDD AD15 AD16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD RQ/GT0 RQ/GT1 LOCK S2 S1 S0 QS0 QS1 TEST READY RESET

(HOLD) (HLDA) (

WR) (M/IO) (DT/R) (DEN) (ALE) (

INTA)

HS-80C86RH 42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK)

INTERSIL OUTLINE K42.A

TOP VIEW

MAX MIN

GND AD14 AD13 AD12 AD11 AD10

AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

NMI

INTR

CLK

GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22

VDD AD15 NC A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD RQ/GT0 RQ/GT1 LOCK S2 S1 S0 QS0 QS1 TEST READY RESET

(HOLD) (HLDA) (

WR)

IO)

(M/

(DT/

DEN)

( (ALE)

INTA)

(

857

Spec Number

518055

Functional Diagram

EXECUTION UNIT

DATA POINTER

AND

INDEX REGS

(8 WORDS)

HS-80C86RH

BUS INTERFACE UNIT

RELOCATION

SEGMENT REGISTERS

INSTRUCTION POINTER

AND

(5 WORDS)

TEST

INTR

NMI

RQ/GT0, 1

HOLD

HLDA

16-BIT ALU

FLAGS

CLK RESET READY

MEMORY INTERFACE

BUS INTERFACE UNIT

CONTROL AND TIMING

MN/

C-BUS

6-BYTE

INSTRUCTION

QUEUE

GND VDD

LOCK

QS0, QS1

S2, S1, S0

BHE/S7 A19/S6

A16/S3 AD15-AD0

INTA,RD, WR DT/

R, DEN, ALE, M/IO

BUS

INTERFACE

UNIT

EXECUTION

UNIT

AH BH CH DH

B+BUS

ES CS SS DS

SP BP

SI DI

AL BL

INSTRUCTION

STREAM BYTE

QUEUE

A-BUS

ARITHMETIC/

LOGIC UNIT

858

EXECUTION UNIT

CONTROL SYSTEM

FLAGS

Spec Number

518055

HS-80C86RH

Pin Description

SYMBOL

The following pin function descriptions are for HS-80C86RH systems in either minimum or maximum mode. The “Local Bus” in these descriptions is the direct multiplexed bus interface connection to the HS-80C86RH (without regard to additional bus buffers).

AD15-AD0 2-16, 39 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1)

A19/S6 A18/S5 A17/S4 A16/S3

BHE/S7 34 O BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to

RD 32 O READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, de-

READY 22 I READY: is the acknowledgment from the addressed memory or I/O device that will complete the

INTR 18 I INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle

TEST 23 I TEST: input is examined by the “Wait” instruction. If theTEST input is LOW execution continues,

NMI 17 I NON-MASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. An

NUMBER TYPE DESCRIPTION

and data (T2, T3, TW, T4) bus. AO is analogous to BHE for the lower byte of the data bus, pins D7-D0. It is LOW during T1 when a byte is to be transferred on the lower portion of the bus in memory or I/O operations. Eight-bit oriented devices tied to the lower half would normally use AD0 to condition chip select functions (See BHE). These lines are active HIGH and are held at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”.

35-38 O ADDRESS/STATUS: During T1, these are the four most significant address lines for memory

operations. During I/O operations these lines are low. During memory and I/O operations, status information is available on these lines during T2, T3, TW, T4. S6 is always zero. The status of the interrupt enable FLAG bit (S5) is updated at the beginning of each CLK cycle. S4 and S3 are encoded.

This information indicates which segment register is presently being used for data accessing. These lines are held at high impedance to the last valid logic level during local bus “hold acknowledge” or “grant sequence”.

S4 S3

0 0 Extra Data 0 1 Stack 1 0 Code or None 1 1 Data

enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus. The S7 status information is available during T2, T3 and T4. The signal is active LOW, and is held at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”; it is LOW during T1 for the first interrupt acknowledge cycle.

BHE A0

0 0 Whole Word 0 1 Upper Byte from/to Odd Address 1 0 Lower Byte from/to Even Address 1 1 None

pending on the state of the M/IO or S2 pin. This signal is used to read devices which reside on the HS-80C86RH local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaranteed to remain HIGH in T2 until the 80C86 local bus has floated.

This line is held at a high impedance logic one state during “hold acknowledge” or “grant sequence”.

data transfer. The RDY signal from memory or I/O is synchronized by the HS-82C85RH Clock Generator to form READY. This signal is active HIGH. The HS-80C86RH READY input is not synchronized. Correct operation is not guaranteed if the Setup and Hold Times are not met.

of each instruction to determine if the processor should enter into an interrupt acknowledge operation. If so, an interrupt service routine is called via an interrupt vector lookup table located in system memory. INTR is internally synchronized and can be internally masked by software resetting the interrupt enable bit. This signal is active HIGH.

otherwise the processor waits in an “Idle” state. This input is synchronized internally during each clock cycle on the leading edge of CLK.

interrupt service routine is called via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A transition from LOW to HIGH initiates the interrupt at the end of the current instruction. This input is internally synchronized.

859

Spec Number

518055

HS-80C86RH

Pin Description

SYMBOL

RESET 21 I RESET: causes the processor to immediately terminate its present activity. The signal must

CLK 19 I CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a

VDD 40 VDD: +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for

GND 1, 20 GND: Ground. Note: both must be connected. A 0.1µF capacitor between pins 1 and 20 is

MN/MX 33 I MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are

The following pin function descriptions are for the HS-80C86RH system in maximum mode (i.e., MN/MX = GND). Only the pin functions which are unique to maximum mode are described below.

S0, S1, S2 26-28 O STATUS: is active during T4, T1 and T2 and is returned to the passive state (1,1,1) during T3

RQ/GT0 RQ/GT1

(Continued)

NUMBER TYPE DESCRIPTION

change from LOW to HIGH and remain active HIGH for at least 4 CLK cycles. It restarts execution, as described in the Instruction Set description, when RESET returns LOW. RESET is internally synchronized.

33% duty cycle to provide optimized internal timing.

decoupling.

recommended for decoupling.

discussed in the following sections.

or during TW when READY is HIGH. This status is used by the 82C88 Bus Controller to generate all memory and I/O access control signals. Any change by S2, S1, or S0 during T4 is used to indicate the beginning of a bus cycle, and the return to the passive state in T3 or TW is used to indicate the end of a bus cycle. These status lines are encoded. These signals are held at a high impedance logic one state during “grant sequence”.

S2 S1 S0

0 0 0 Interrupt Acknowledge 0 0 1 Read I/O Port 0 1 0 Write I/O Port 0 1 1 Halt 1 0 0 Code Access 1 0 1 Read Memory 1 1 0 Write Memory 1 1 1 Passive

31, 30 I/O REQUEST/GRANT: pins are used by other local bus masters to f orce the processor to release the

local bus at the end of the processor’s current b us cycle. Each pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1. RQ/GT has an internal pull-up bus hold device so it may be left unconnected. The request/grant sequence is as follows (see RQ/GT Sequence Timing.)

1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (“hold”) to the HS-80C86RH (pulse 1).

2. During a T4 or T1 clock cycle, a pulse 1 CLK wide from the HS-80C86RH to the requesting master (pulse 2) indicates that the HS-80C86RH has allowed the local bus to float and that it will enter the “grant sequence” state at the next CLK. The CPU’s bus interface unit is disconnected logically from the local bus during “grant sequence”.

3. A pulse 1 CLK wide from the requesting master indicates to the HS-80C86RH (pulse 3) that the “hold” request is about to end and that the HS-80C86RH can reclaim the local bus at the next CLK. The CPU then enters T4 (or T1 if no bus cycles pending).

Each Master-Master exchange of the local bus is a sequence of 3 pulses. There must be one idle CLK cycle after each bus exchange. Pulses are active low.

If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4 of the cycle when all the following conditions are met:

1. Request occurs on or before T2.

2. Current cycle is not the low byte of a word (on an odd address).

3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.

4. A locked instruction is not currently executing. If the local bus is idle when the request is made the two possible events will follow:

1. Local bus will be released during the next cycle.

2. A memory cycle will start within 3 CLKs. Now the four rules for a currently active memory

cycle apply with condition number 1 already satisfied.

860

Spec Number

518055

HS-80C86RH

Pin Description

SYMBOL

LOCK 29 O LOCK: output indicates that other system bus masters are not to gain control of the system bus

QS1, QS0 24, 25 O QUEUE STATUS: The queue status is valid during the CLK cycle after which the queue

The following pin function descriptions are for the HS-80C86RH in minimum mode (i.e. MN/MX = VDD). Only the pin functions which are unique to minimum mode are described; all other pin functions are as described below.

M/IO 28 O STATUS LINE: logically equivalent to S2 in the maximum mode. It is used to distinguish a mem-

WR 29 O WRITE: indicates that the processor is performing a write memory or write I/O cycle, depending

INTA 24 O INTERRUPT ACKNOWLEDGE: is used as a read strobe for interrupt acknowledge cycles. It is

ALE 25 O ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the 82C82

DT/R 27 O DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use a data bus

DEN 26 O DATA ENABLE: provided as an output enable fora bus transceiver in a minimum system which

HOLD HLDA

(Continued)

NUMBER TYPE DESCRIPTION

while LOCK is active LOW. The LOCK signal is activated by the “LOCK” preﬁx instruction and remains active until the completion of the next instruction. This signal is active LO W, and is held at a HIGH impedance logic one state during “grant sequence”. In MAX mode, LOCK is automatically generated during T2 of the ﬁrst INT A cycle and remo ved during T2 of the second INTA cycle.

operation is performed. QS1 and QS2 provide status to allow external tracking of the internal HS-80C86RH instruction

queue. Note that QS1, QS0 never become high impedance.

QS1 QS0

0 0 No Operation 0 1 First Byte of Opcode from Queue 1 0 Empty the Queue 1 1 Subsequent Byte from Queue

ory access from an I/O access. M/IO becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle (M = HIGH, IO = LOW). M/IO is held to a high impedance logic zero during local bus “hold acknowledge”.

on the state of the M/IO signal. WR is active for T2, T3 and TW of any write cycle. It is active LOW, and is held to high impedance logic one during local bus “hold acknowledge”.

active LOW during T2, T3 and TW of each interrupt acknowledge cycle. Note that INTA is never floated.

latch. It is a HIGH pulse active during clock LOW of Tl of any bus cycle. Note that ALE is never floated.

transceiver. It is used to control the direction of data flow through the transceiver. Logically, DT/R is equivalent to S1 in maximum mode, and its timing is the same as for M/IO (T = HlGH, R = LOW). DT/R is held to a high impedance logic one during local bus “hold acknowledge”.

uses the transceiver. DEN is active LOW during each memory and I/O access and for INTA cycles. For a read or INTA cycle it is active from the middle of T2 until the middle of T4, while for a write cycle it is active from the beginning of T2 until the middle of T4. DEN is held to a high impedance logic one during local bus “hold acknowledge”.

31 30

HOLD: indicates that another master is requesting a local bus “hold”. To be a acknowledged,

HOLD must be active HIGH. The processor receiving the “hold” will issue a “hold acknowledge” (HLDA) in the middle of a T4 or T1 clock cycle. Simultaneously with the issuance of HLDA, the processor will float the local bus and control lines. After HOLD is detected as being LOW, the processor will lower HLDA, and when the processor needs to run another cycle, it will again drive the local bus and control lines.

HOLD is not an asynchronous input. External synchronization should be provided if the system cannot otherwise guarantee the setup time.

861

Spec Number

518055

Speciﬁcations HS-80C86RH

Absolute Maximum Ratings Reliability Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V

Input or Output Voltage

Applied for all Grades. . . . . . . . . . . . . . . . . .VSS-0.3V to VDD+0.3V

Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC

Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC

Typical Derating Factor. . . . . . . . . . . 12mA/MHz Increase in IDDOP

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

Operating Conditions

Operating Supply Voltage Range (VDD) . . . . . . . +4.75V to +5.25V

Operating Temperature Range (TA) . . . . . . . . . . . . -35oC to +125oC

Input Low Voltage (VIL) . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Thermal Resistance θ

SBDIP Package. . . . . . . . . . . . . . . . . . . . 40.0oC/W 8.6oC/W

Ceramic Flatpack Package . . . . . . . . . . . 72.1oC/W 9.7oC/W

Maximum Package Power Dissipation at +125oC Ambient

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25W

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.69W

If Device Power Exceeds Package Dissipation Capability, Provide Heat Sinking or Derate Linearly at the Following Rate

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25.0mW/oC

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . .13.9mW/oC

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9750 Gates

Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . . . 3.5V to VDD

Clock Input Low Voltage (VILC) . . . . . . . . . . . . . . . . . . 0.0V to 0.8V

CLK and MN/MX Input High (VIHC) . . . . . . . . . .VDD - 0.8V to VDD

GROUP A

PARAMETERS SYMBOL CONDITIONS

TTL High Level Output Voltage

CMOS High Level Output Voltage

Low Level Output Voltage

Input Leakage Current

Output Leakage Current

Input Current Bus Hold High

Input Current Bus Hold Low

Standby Power Supply Current

Operating Power Supply Current

Functional Tests FT VDD = 4.75V and 5.25V,

Noise Immunity Functional Tests

NOTES:

1. IBHH should be measured after raising VIN to VDD and then lowering to 3.0V.

2. IBHL should be measured after lowering VIN to VSS and then raising to 0.8V.

3. IDDSB tested during Clock high time after halt instruction executed.

4. CLK and MN/MX Input High (VIHC) = VDD -0.8

VOH1 VDD = 4.75V, IO = -2.5mA

VIN = 0V or VDD

VOH2 VDD = 4.75V, IO = -100µA

VIN = 0V or VDD

VOL VDD = 4.75V, IO = +2.5mA

VIN = 0V or VDD

IIH or

IIL

IOZL or

IOZH

IBHH VDD = 4.75V and 5.25V

IBHL VDD = 4.75V and 5.25V

IDDSB VDD = 5.25V, VIN = GND or

IDDOP VDD = 5.25V, VIN = GND or

FN VDD = 4.75V and 5.25V,

VDD = 5.25V VIN = 0V or VDD Pins: 17-19, 21-23, 33

VDD = 5.25V VIN = 0V or VDD Pins: 2-16, 26-29, 32, 34-39

VIN = 3.0V (Note 1) Pins: 2-16, 26-32, 34-39

VIN = 0.8V (Note 2) Pins: 2-16, 34-39

VDD, IO = 0mA (Note 3)

VDD, IO = 0mA, f = 1MHz

VIN = GND or VDD, f = 1MHz

VIN = GND or 3.5V and VDD = 4.5V, VIN = 0.8V or VDD (Note 4)

SUBGROUPS TEMPERATURE

1, 2, 3 -35oC, +25oC,

7, 8A, 8B -35oC, +25oC,

+125oC

LIMITS

UNITSMIN MAX

3.0 - V

VDD -

0.4V

- 0.4 V

-1.0 1.0 µA

-10 10 µA

-600 -40 µA

40 600 µA

- 500 µA

- 12 mA/MHz

-- -

-V

862

Spec Number

518055

Speciﬁcations HS-80C86RH

TABLE 2A. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (MIN MODE)

ACs tested at worst case VDD, ACs guaranteed over full operating speciﬁcations.

GROUP A

PARAMETERS SYMBOL CONDITIONS

CLK Cycle Period TCLCL VDD = 4.75V

VDD = 5.25V

CLK Low Time TCLCH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

CLK High Time TCHCL VDD = 4.75V

VDD = 5.25V

Data in Setup Time TDVCL VDD = 4.75V 9, 10, 11 -35oC, +25oC,

Data in Hold Time TCLDX1 VDD = 4.75V 9, 10, 11 -35oC, +25oC,

Ready Setup Time into 80C86RH

Ready Hold Time into 80C86RH

Ready Inactive to CLK (Note 2)

Hold Setup Time THVCH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

INTR, NMI, Test/Setup Time TINVCH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

MIN MODE TIMING RESPONSES (CL = 100pF) Address Valid Delay TCLAV VDD = 4.75V 9, 10, 11 -35oC, +25oC,

ALE Width TLHLL VDD = 4.75V 9, 10, 11 -35oC, +25oC,

ALE Active Delay TCLLH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

ALE Inactive Delay TCHLL VDD = 4.75V 9, 10, 11 -35oC, +25oC,

Address Hold Time to ALE Inactive

Control Active Delay 1 TCVCTV VDD = 4.75V 9, 10, 11 -35oC, +25oC,

Control Active Delay 2 TCHCTV VDD = 4.75V 9, 10, 11 -35oC, +25oC,

Control Inactive Delay TCVCTX VDD = 4.75V 9, 10, 11 -35oC, +25oC,

RD Active Delay TCLRL VDD = 4.75V 9, 10, 11 -35oC, +25oC,

RD Inactive Delay TCLRH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

RD Inactive to Next Address Active

HLDA Valid Delay TCLHAV VDD = 4.75V 9, 10, 11 -35oC, +25oC,

TRYHCH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

TCHRYX VDD = 4.75V 9, 10, 11 -35oC, +25oC,

TRYLCL VDD = 4.75V 9, 10, 11 -35oC, +25oC,

TLLAX VDD = 4.75V 9, 10, 11 -35oC, +25oC,

TRHAV VDD = 4.75V 9, 10, 11 -35oC, +25oC,

SUBGROUPS TEMPERATURE

9, 10, 11 -35oC, +25oC,

+125oC

9, 10, 11 -35oC, +25oC,

+125oC

LIMITS

UNITSMIN MAX

200 - ns

118 - ns

69 - ns

30 - ns

10 - ns

113 - ns

30 - ns

-8 - ns

35 - ns

30 - ns

10 110 ns

TCLCH -

-80ns

-85ns

TCHCL -

10 10 110 ns

10 110 ns

10 165 ns

10 150 ns

TCLCL -

45 10 160 ns

-ns

863

Spec Number

518055

Speciﬁcations HS-80C86RH

TABLE 2A. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (MIN MODE) (Continued)

ACs tested at worst case VDD, ACs guaranteed over full operating speciﬁcations.

GROUP A

PARAMETERS SYMBOL CONDITIONS

RD Width TRLRH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

WR Width TWLWH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

Address Valid to ALE Low TAVLL VDD = 4.75V 9, 10, 11 -35oC, +25oC,

Output Rise Time TOLOH VDD = 4.75V

From 0.8V to 2.0V

Output Fall Time TOHOL VDD = 4.75V

From 2.0V to 0.8V

NOTES:

1. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

2. Applies only to T2 State (8ns into T3).

TABLE 2B. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (MAX MODE)

ACs tested at worst case VDD, ACs guaranteed over full operating speciﬁcations.

PARAMETERS SYMBOL CONDITIONS

TIMING REQUIREMENTS CLK Cycle Period TCLCL VDD = 4.75V

VDD = 5.25V

CLK Low Time TCLCH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

CLK High Time TCHCL VDD = 4.75V

VDD = 5.25V

Data in Setup Time TDVCL VDD = 4.75V 9, 10, 11 -35oC, +25oC,

Data in Hold Time TCLDX1 VDD = 4.75V 9, 10, 11 -35oC, +25oC,

Ready Setup Time into 80C86RH

Ready Hold Time into 80C86RH

Ready Inactive to CLK (Note 2)

INTR, NMI, Test/Setup Time TINVCH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

RQ/GT Setup Time TGVCH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

RQ Hold Time into HS-80C86RH (Note 3)

MAX MODE TIMING RESPONSES (CL = 100pF) Ready Active to Status

Passive (Notes 2 and 4) Status Active Delay TCHSV VDD = 4.75V 9, 10, 11 -35oC, +25oC,

TRYHCH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

TCHRYX VDD = 4.75V 9, 10, 11 -35oC, +25oC,

TRYLCL VDD = 4.75V 9, 10, 11 -35oC, +25oC,

TCHGX VDD = 4.75V 9, 10, 11 -35oC, +25oC,

TRYHSH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

SUBGROUPS TEMPERATURE

+125oC

9, 10, 11 -35oC, +25oC,

+125oC

9, 10, 11 -35oC, +25oC,

+125oC

GROUP A

SUBGROUPS TEMPERATURE

9, 10, 11 -35oC, +25oC,

+125oC

9, 10, 11 -35oC, +25oC,

+125oC

LIMITS

UNITSMIN MAX

2TCLCL -

TCLCH -

-20ns

LIMITS

200 - ns

118 - ns

69 - ns

30 - ns

10 - ns

113 - ns

30 - ns

-8 - ns

30 - ns

40 TCHCL +10ns

- 110 ns

10 110 ns

-ns

UNITSMIN MAX

864

Spec Number

518055

Speciﬁcations HS-80C86RH

TABLE 2B. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (MAX MODE) (Continued)

ACs tested at worst case VDD, ACs guaranteed over full operating speciﬁcations.

GROUP A

PARAMETERS SYMBOL CONDITIONS

Status Inactive Delay (Note 4)

Address Valid Delay TCLAV VDD = 4.75V 9, 10, 11 -35oC, +25oC,

RD Active Delay TCLRL VDD = 4.75V 9, 10, 11 -35oC, +25oC,

RD Inactive Delay TCLRH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

RD Inactive to Next Address Active

GT Active Delay TCLGL VDD = 4.75V 9, 10, 11 -35oC, +25oC,

GT Inactive Delay TCLGH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

RD Width TRLRH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

Output Rise Time TOLOH VDD = 4.75V

Output Fall Time TOHOL VDD = 4.75V

NOTES:

1. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

2. Applies only to T2 State (8ns into T3).

3. The HS-80C86RH actively pulls the RQ/GT pin to a logic one on the following clock low time.

4. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.

TCLSH VDD = 4.75V 9, 10, 11 -35oC, +25oC,

TRHAV VDD = 4.75V 9, 10, 11 -35oC, +25oC,

From 0.8V to 2.0V

From 2.0V to 0.8V

SUBGROUPS TEMPERATURE

+125oC

9, 10, 11 -35oC, +25oC,

+125oC

9, 10, 11 -35oC, +25oC,

+125oC

LIMITS

UNITSMIN MAX

10 130 ns

10 110 ns

10 165 ns

10 150 ns

TCLCL -

085ns

2TCLCL -

-20ns

-ns

TABLE 3A. ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETERS SYMBOL CONDITIONS TEMPERATURE

Input Capacitance CIN VDD = Open, f = 1MHz

(Note 1)

Output Capacitance COUT VDD = Open, f = 1MHz

(Note 1)

I/O Capacitance CI/O VDD = Open, f = 1MHz

(Note 1) TIMING REQUIREMENTS CLK Rise Time TCH1CH2 VDD = 4.75V and 5.25V

Min and Max Mode

from 1.0V to 3.5V CLK Fall Time TCL2CL1 VDD = 4.75V and 5.25V

Min and Max Mode

from 3.5V to 1.0V Input Rise Time TILIH VDD = 4.75V and 5.25V

Min and Max Mode

from 0.8V to 2.0V Input Fall Time TIHIL VDD = 4.75V and 5.25V

Min and Max Mode

from 2.0V to 0.8V

LIMITS

UNITSMIN MAX

TA = +25oC - 15 pF

TA = +25oC - 20 pF

-35oC < TA < +125oC - 15 ns

-35oC < TA < +125oC - 25 ns

865

Spec Number

518055

Speciﬁcations HS-80C86RH

TABLE 3A. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS

PARAMETERS SYMBOL CONDITIONS TEMPERATURE

TIMING RESPONSES Address Hold Time TCLAX VDD = 4.75V and 5.25V

Min and Max Mode Address Float Delay (Note 2) TCLAZ VDD = 4.75V and 5.25V

Min and Max Mode Data Valid Delay TCLDV VDD = 4.75V and 5.25V

Min and Max Mode Data Hold Time TCLDX2 VDD = 4.75V and 5.25V

Min and Max Mode Data Hold Time After WR TWHDX VDD = 4.75V and 5.25V

Min Mode Status Float Delay (Note 2) TCHSZ VDD = 4.75V and 5.25V

Max Mode Address Float to Read Active

(Note 2)

NOTES:

1. All measurements referenced to device ground.

2. Output drivers disabled. Bus hold circuitry still active.

3. The parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics.

TAZRL VDD = 4.75V and 5.25V

Min and Max Mode

-35oC < TA < +125oC10 - ns

-35oC < TA < +125oC TCLAX 80 ns

-35oC < TA < +125oC 10 110 ns

-35oC < TA < +125oC10 - ns

-35oC < TA < +125oC TCLCL - 30 - ns

-35oC < TA < +125oC - 80 ns

-35oC < TA < +125oC0 - ns

UNITSMIN MAX

TABLE 3B. ELECTRICAL PERFORMANCE CHARACTERISTICS

Timing Signals at HS-82C85RH or 82C88 for Reference Only.

LIMITS

PARAMETERS SYMBOL CONDITIONS TEMPERATURE

RDY Setup Time into HS-82C85RH (Note 1) TR1VCL Min and Max Mode -35oC < TA < +125oC35 - ns RDY Hold Time into HS-82C85RH (Note 1) TCLR1X Min and Max Mode -35oC < TA < +125oC0 - ns Command Active Delay TCLML Max Mode Only -35oC < TA < +125oC 5 35 ns Command Inactive TCLMH Max Mode Only -35oC < TA < +125oC 5 35 ns Status Valid to ALE High TSVLH Max Mode Only -35oC < TA < +125oC - 20 ns Status Valid to MCE High TSVMCH Max Mode Only -35oC < TA < +125oC - 30 ns CLK Low to ALE Valid TCLLH Max Mode Only -35oC < TA < +125oC - 20 ns CLK Low to MCE High TCLMCH Max Mode Only -35oC < TA < +125oC - 25 ns ALE Inactive Delay TCHLL Max Mode Only -35oC < TA < +125oC 4 18 ns MCE Inactive Delay TCLMCL Max Mode Only -35oC < TA < +125oC - 15 ns Control Active Delay TCVNV Max Mode Only -35oC < TA < +125oC 5 45 ns Control Inactive Delay TCVNX Max Mode Only -35oC < TA < +125oC1045 ns

NOTE:

1. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

UNITSMIN MAX

TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS

NOTE: See 25oC limits in Table 1 and Table 2 for Post RAD limits (Subgroups 1, 7 and 9).

866

Spec Number

518055

Speciﬁcations HS-80C86RH

TABLE 5. BURN-IN DELTA PARAMETERS (+25oC)

PARAMETER SYMBOL DELTA LIMITS

Standby Power Supply Current IDDSB ±100µA Output Leakage Current IOZL, IOZH ±2µA Input Leakage Current IIH, IIL ±200nA Low Level Output Voltage VOL ±80mV TTL High Level Output Voltage VOH1 ±600mV CMOS High Level Output Voltage VOH2 ±150mV

TABLE 6. APPLICABLE SUBGROUPS

GROUP A SUBGROUPS

CONFORMANCE

GROUP

Initial Test 100%/5004 1, 7, 9 1 (Note 2) 1, 7, 9 Interim Test 1 100%/5004 1, 7, 9, ∆ 1, ∆ (Note 2) 1, 7, 9 PDA 1 100%/5004 1, 7, ∆ 1, 7 Interim Test 2 100%/5004 1, 7, 9, ∆ 1, ∆ (Note 2) N/A PDA 2 100%/5004 1, 7, ∆ N/A Final Test 100%/5004 2, 3, 8A, 8B, 10, 11 2, 3, 8A, 8B, 10, 11 Group A (Note 1) Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3 (Note 2) N/A Subgroup B6 Sample 5005 1, 7, 9 N/A Group C Sample 5005 N/A N/A 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Group D Sample 5005 1, 7, 9 1, 7, 9 Group E, Subgroup 2 Sample 5005 1, 7, 9 1, 7, 9

NOTES:

1. Alternate Group A testing in accordance with MIL-STD-883 method 5005 may be exercised.

2. Table 5 parameters only.

MIL-STD-883

METHOD

TESTED FOR -Q

RECORDED

FOR -Q TESTED FOR -8

RECORDED

FOR -8

Functional Description

Static Operation

All HS-80C86RH circuitry is of static design. Internal registers, counters and latches are static and require no refresh as with dynamic circuit design. This eliminates the minimum operating frequency restriction placed on other microprocessors. The CMOS HS-80C86RH can operate from DC to 5MHz. The processor clock may be stopped in either state (HIGH/LOW) and held there indeﬁnitely. This type of operation is especially useful for system debug or power critical applications.

The HS-80C86RH can be single stepped using only the CPU clock. This state can be maintained as long as is necessary. Single step clock operation allows simple interface circuitry to provide critical information for bringing up your system.

Static design also allows very low frequency operation (down to DC). In a power critical situation, this can provide extremely low power operation since HS-80C86RH power dissipation is directly related to operating frequency. As the

system frequency is reduced, so is the operating power until, ultimately, at a DC input frequency, the HS-80C86RH power requirement is the standby current, (500µA maximum).

Internal Architecture

The internal functions of the HS-80C86RH processor are partitioned logically into two processing units. The ﬁrst is the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the CPU functional diagram.

These units can interact directly but for the most part perform as separate asynchronous operational processors. The bus interface unit provides the functions related to instruction fetching and queuing, operand fetch and store, and address relocation. This unit also provides the basic bus control. The overlap of instruction pre-fetching provided by this unit serves to increase processor performance through improved bus bandwidth utilization. Up to 6 bytes of the instruction stream can be queued while waiting for decoding and execution.

Spec Number

867

518055

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