Intersil Corporation HS-80C85RH Datasheet

February 1996

HS-80C85RH

Radiation Hardened

8-Bit CMOS Microprocessor

Features

• Devices QML Qualified in Accordance With
MIL-PRF-38535

• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95824 and Intersil’ QM Plan

• Radiation Hardened EPI-CMOS

- Parametrics Guaranteed 1 x 10

- Transient Upset > 1 x 10

- Latch-up Free > 1 x 10

12

5

8

RAD(Si)

RAD(Si)/s

RAD(Si)/s

• Low Standby Current 500µA Max

• Low Operating Current 5.0mA/MHz (X

Input)

1

• Electrically Equivalent to Sandia SA 3000

• 100% Software Compatible with INTEL 8085

• Operation from DC to 2MHz, Post Radiation

• Single 5 Volt Power Supply

• On-Chip Clock Generator and System Controller

• Four Vectored Interrupt Inputs

• Completely Static Design

• Self Aligned Junction Isolated (SAJI) Process

o

• Military Temperature Range -55

C to +125oC

Pinouts

40 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835, CDIP2-T40

TOP VIEW

X1
X2

RESET OUT

SOD

SID

TRAP

RST 7.5
RST 6.5

RST 5.5

INTR
INTA

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

GND

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

VDD

40

HOLD

39

HLDA

38

CLOCK OUT

37
36

RESET IN
READY

35
34

IO / M
S1

33

RD

32
31

WR
ALE

30
29

S0
A15

28

A14

27

A13

26

A12

25

A11

24
23

A10
A9

22

A8

21

Description

The HS-80C85RH is an 8-bit CMOS microprocessor fabri­cated using the Intersil radiation hardened self-aligned junc­tion isolated (SAJI) silicon gate technology. Latch-up free
operation is achieved by the use of epitaxial starting material
to eliminate the parasitic SCR effect seen in conventional
bulk CMOS devices.

The HS-80C85RH is a functional logic emulation of the
HMOS 8085 and its instruction set is 100% software com­patible with the HMOS device. The HS80C85RH is designed
for operation with a single 5 volt power supply. Its high level
of integration allows the construction of a radiation hardened
microcomputer system with as few as three ICs (HS­80C85RH CPU, HS83C55RH ROM I/O, and the HS-81C55/
56RH RAM I/O.

42 LEAD CERAMIC METAL SEAL

FLATPACK PACKAGE (FLATPACK)

INTERSIL OUTLINE K42.A

TOP VIEW

X1
X2

RESET

OUT
SOD

SID

TRAP

RST 7.5
RST 6.5

RST 5.5

INTR
INTA

AD0
AD1
AD2
AD3
AD4

NC
NC

AD5
AD6
AD7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

19
20
21

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

24
23
22

VDD
HOLD
HLDA

CLOCK
OUT
RESET
IN
READY

M

IO /
S1
RD

WR
ALE
S0
A15
A14
A13
A12
A11

A10
A9
A8
GND

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

1

Spec Number

518054

File Number 3036.2

HS-80C85RH

Ordering Information

PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE

5962R9582401QQC -55oC to +125oC MIL-PRF-38535 Level Q 40 Lead SBDIP
5962R9582401QXC -55oC to +125oC MIL-PRF-38535 Level Q 42 Lead Ceramic Flatpack
5962R9582401VQC -55oC to +125oC MIL-PRF-38535 Level V 40 Lead SBDIP
5962R9582401VXC -55oC to +125oC MIL-PRF-38535 Level V 42 Lead Ceramic Flatpack
HS1-80C85RH/SAMPLE +25oC Sample 40 Lead SBDIP
HS9-80C85RH/SAMPLE +25oC Sample 42 Lead Ceramic Flatpack

Functional Diagram

RST

RST

INTA

INTR

INTERRUPT CONTROL SERIAL I/O CONTROL

5.5

RST

6.5

7.5

TRAP

8-BIT

INTERNAL DATA BUS

SID SOD

ACCUMU­LATOR (8)

POWER

SUPPLY

X1
X2

TEMP REG

(8)

VDD
GND

CLK
GEN

READY
CLK
OUT

FLAG (5)

FLIP FLOPS

ARITHMETIC

LOGIC

UNIT

(ALU) (8)

TIMING AND CONTROL

CONTROL STATUS DMA

WR

RD

S0

ALE

INSTRUCTION

REGISTER (8)

INSTRUCTION

DECODER

AND MACHINE

ENCODING

IO/M HLDA

S1

HOLD

CYCLE

RESET

RESET

IN

B REG (8)
D REG (8)
H REG (8)

STACK POINTER (16)

PROGRAM COUNTER (16)

INCREMENTER

DECREMENTER

ADDRESS LATCH (16)

RESET

OUT

C REG (8)
E REG (8)
L REG (8)

ADDRESS

BUFFER (8)

A15-A8

ADDRESS

BUS

REGISTER ARRAY

DATA ADDRESS

BUFFER (8)

AD1-AD0

ADDRESS

BUS

Spec Number 518054

2

HS-80C85RH

Pin Description

PIN

SYMBOL

A8 - A15 21-28 O Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address,

AD0-7 12-19 I/O Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/O address) appear on

ALE 32 O Address Latch Enable: It occurs during the first clock state of a machine cycle and enables the

NUMBER TYPE DESCRIPTION

3-stated during Hold and Halt modes and during RESET.

the bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus
during the second and third clock cycles.

address to get latched into the on-chip latch of peripherals. The falling edge of ALE is set to guar­antee setup and hold times for the address information. The falling edge of ALE can also be used
to strobe the status information. ALE is never 3-stated.

S0, S1, and

IO/M

RD 34 O Read Control: A low level on RD indicates the selected memory or I/O device is to be read and

WR 33 O Write Control: A low level on WR indicates the data on the Data Bus is to be written into the se-

31, 35,

& 36

O Machine Cycle Status:

IO/M S1 S0 Status

0 0 1 Memory write
0 1 0 Memory write
1 0 1 I/O write
1 1 0 I/O read
0 1 1 Opcode fetch
1 1 1 Opcode fetch
1 1 1 Interrupt acknowledge
T 0 0 Halt
T X X Hold
T X X Reset

T = 3-State (high impedance)
X = Unspecified

S1 can be used as an advanced R/W status. IO/M, S0 and S1 become valid at the beginning of
a machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used
to latch the state of these lines.

that the Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and dur­ing RESET.

lected memory or I/O location. Data is set up at the trailing edge of WR, 3-stated during Hold and
Halt modes and during RESET.

READY 35 I Ready: If READY is high during a read or write cycle, it indicates that the memory or peripheral

is ready to send or receive data. If READY is low, the cpu will wait an integral number of clock
cycles for READY to go high before completing the read or write cycle. READY must conform to
specified setup and hold times.

HOLD 39 I Hold: Indicates that another master is requesting the use of the address and data buses. The

cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion
of the current bus transfer. Internal processing can continue. The processor can regain the bus
only after the HOLD is removed. When the HOLD is acknowledged, the Address, Data Bus, RD,
WR, and IO/M lines are 3-stated.

HLDA 38 O Hold Acknowledge: Indicates that the cpu has received the HOLD request and that it will relin-

quish the bus in the next clock cycle. HLDA goes low after the Hold request is removed. The cpu
takes the bus one half clock cycle after HLDA goes low.

Spec Number 518054

3

HS-80C85RH

Pin Description

SYMBOL

INTR 10 I Interrupt Request: Is used as a general purpose interrupt. It is sampled only during the next to

INTA 11 O Interrupt Acknowledge: Is used instead of (and has the same timing as) RD during the Instruc-

RST 5.5
RST 6.5
RST 7.5

TRAP 6 I Trap: Trap interrupt is a non-maskable RESTART interrupt. It is recognized at the same time as

RESET IN 36 I Reset In: Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops.

(Continued)

PIN

NUMBER TYPE DESCRIPTION

the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program
Counter (PC) will be inhibited from incrementing and an
RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR
is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is
accepted.

tion cycle after an INTR is accepted. It can be used to activate an 8259A Interrupt chip or some
other interrupt port.

9
8
7

I Restart Interrupts: These three inputs have the same timing as INTR except they cause an

internal RESTART to be automatically inserted.
The priority of these interrupts is ordered as shown in Table 6. These interrupts have a higher
priority than INTR. In addition, they may be individually masked out using the SIM instruction.

INTR or RST 5.5-7.5. It is unaffected by any mask or Interrupt Enable. It has the highest priority
of any interrupt. (See Table 6.)

The data and address buses and the control lines are 3-stated during RESET and because of
the asynchronous nature of RESET the processor’s internal registers and flags may be altered
by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing connec­tion to an R-C network for power-on RESET delay (see Figure 1). Upon power-up, RESET IN
must remain low for at least 10 “clock cycle” after minimum VDD has been reached. For proper
reset operation after the power-up duration, RESET IN should be kept low a minimum of three
clock periods. The CPU is held in the reset condition as long as RESET IN is applied.

INTA will be issued. During this cycle a

RESET OUT 3 O Reset Out: Reset Out indicates cpu is being reset. Can be used as a system reset. The signal

is synchronized to the processor clock and lasts an integral number of clock periods.

X1
X2

CLK 37 O Clock: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input

SID 5 I Serial Input Data Line: The data on this line is loaded into accumulator bit 7 whenever a RIM

SOD 4 O Serial Output Data Line: The output SOD is set or reset as specified by the SlM instruction.

VCC 40 I Power: +5V supply.

GND 20 I Ground: Reference.

1
2

VDD

I

X1 and X2: Are connected to a crystal, LC, or RC network to drive the internal clock generator.

O

X, can also be an external clock Input from a logic gate. The input frequency is divided by 2 to
give the processor’s internal operating frequency.

period.

instruction is executed.

RESET IN

R1

C1

TYPICAL POWER-ON RESET RC VALUES
R1 = 75KΩ
C1 = 1µF

†

† Values may have to vary due to applied power supply ramp up time.

FIGURE 1. POWER-ON RESET CIRCUIT

4

Spec Number 518054

Specifications HS-80C85RH

Absolute Maximum Ratings Reliability Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V

Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VCC+0.3V

Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC

Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC

Typical Derating Factor. . . . . . . . . . .2.0mA/MHz Increase in IDDOP

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions

Operating Supply Voltage Range (VDD) . . . . . . . +4.75V to +5.25V

Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS

Input Leakage
Current

High Level Output
Voltage

Low Level Output
Voltage

Static Current IDDSB VDD = 5.25V, Clock Out = Hi

Operating Supply
Current (Note 2)

Functional Tests FT VDD = 4.75V and 5.25V,

NOTES:

1. All devices guaranteed at worst case limits and over radiation.

2. Operating supply current (IDDOP) is proportional to crystal frequency. Parts are tested at 1MHz

IIH or

IIL

VOH VDD = 4.75V, IOH = -1.0mA 1, 2, 3 -55oC, +25oC, or

VOL VDD = 5.25V, IOL = 1.0mA, 1, 2, 3 -55oC, +25oC, or

IDDOP VDD = 5.25V, f = 1MHz

VDD = 5.25V, VI = VDD
or GND

and Low

(Note 2)

TCYC = 500ns,
VOL ≤ VDD/2, VOH≥VDD/2

Thermal Resistance θ

SBDIP Package. . . . . . . . . . . . . . . . . . . . 45oC/W 10oC/W

Ceramic Flatpack Package . . . . . . . . . . . 77oC/W 13oC/W

Maximum Package Power Dissipation at +125oC Ambient

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11W

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.65W

If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22.2mW/oC

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . .13.0mW/oC

Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V

Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VDD -0.5V to VDD

GROUP A

SUBGROUPS TEMPERATURE

1, 2, 3 -55oC, +25oC, or

+125oC

+125oC

+125oC

1, 2, 3 -55oC, +25oC, or

+125oC

1, 2, 3 -55oC, +25oC, or

+125oC

7, 8A, 8B -55oC, +25oC, or

+125oC

LIMITS

-1.0 1.0 µA

VDD -0.5 - V

- 0.5 V

- 500 µA

- 5.0 mA/MHz

-- -

JA

θ

JC

UNITSMIN MAX

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP A

PARAMETER SYMBOL

CLK Low Time (Standard CLK Loading) T1 9, 10, 11 -55oC, +25oC, +125oC40 - ns
CLK High Time (Standard CLK Loading) T2 9, 10, 11 -55oC, +25oC, +125oC 100 - ns
CLK Rise Time Tr 9, 10, 11 -55oC, +25oC, +125oC - 115 ns
CLK Fall Time Tf 9, 10, 11 -55oC, +25oC, +125oC - 115 ns
X1 Rising to CLK Rising TXKR 9, 10, 11 -55oC, +25oC, +125oC 30 250 ns
X1 Rising to CLK Falling TXKF 9, 10, 11 -55oC, +25oC, +125oC 50 275 ns
A8-15 Valid to Leading Edge of Control (Note 5) TAC 9, 10, 11 -55oC, +25oC, +125oC 300 - ns
A0-7 Valid to Leading Edge of Control TACL 9, 10, 11 -55oC, +25oC, +125oC 300 - ns
A0-15 Valid to Valid Data In TAD 9, 10, 11 -55oC, +25oC, +125oC 875 - ns
Address Float After Leading Edge of READ

(INTA)

TAFR 9, 10, 11 -55oC, +25oC, +125oC - 70 ns

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

Spec Number 518054

5

Specifications HS-80C85RH

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

GROUP A

PARAMETER SYMBOL

A8-15 Valid Before Trailing Edge of ALE (Note 5) TAL 9, 10, 11 -55oC, +25oC, +125oC75 - ns
A0-7 Valid Before Trailing Edge of ALE tALL 9, 10, 11 -55oC, +25oC, +125oC 125 - ns
READY Valid from Address

Valid
Address (A8-15) Valid After Control TCA 9, 10, 11 -55oC, +25oC, +125oC 150 - ns
Width of Control Low (RD, WR, INTA) Edge of

ALE
Trailing Edge of Control to Leading Edge of ALE TCL 9, 10, 11 -55oC, +25oC, +125oC60 - ns
Data Valid to Trailing Edge of WRITE TDW 9, 10, 11 -55oC, +25oC, +125oC 575 - ns
HLDA to Bus Enable THABE 9, 10, 11 -55oC, +25oC, +125oC - 375 ns
Bus Float After HLDA THABF 9, 10, 11 -55oC, +25oC, +125oC - 375 ns
HLDA Valid to Trailing Edge of CLK THACK 9, 10, 11 -55oC, +25oC, +125oC90 - ns
HOLD Hold Time THDH 9, 10, 11 -55oC, +25oC, +125oC- 0 ns
HOLD Setup Time to Trailing Edge of CLK THDS 9, 10, 11 -55oC, +25oC, +125oC - 300 ns
INTR Hold Time TINH 9, 10, 11 -55oC, +25oC, +125oC- 0 ns
INTR, RST and TRAP Setup Time to Falling

Edge of CLK
Address Hold Time After ALE TLA 9, 10, 11 -55oC, +25oC, +125oC75 - ns
Trailing Edge of ALE to Leading Edge of Control TLC 9, 10, 11 -55oC, +25oC, +125oC 150 - ns
ALE Low During CLK High TLCK 9, 10, 11 -55oC, +25oC, +125oC 125 - ns
ALE to Valid Data During Read TLDR 9, 10, 11 -55oC, +25oC, +125oC 675 - ns
ALE to Valid Data During Write TLDW 9, 10, 11 -55oC, +25oC, +125oC - 350 ns
ALE Width TLL 9, 10, 11 -55oC, +25oC, +125oC 200 - ns
ALE to READY Stable TLRY 9, 10, 11 -55oC, +25oC, +125oC - 175 ns
Trailing Edge of READ to Re-Enabling the Ad-

dress
READ (or INTA) to Valid Data TRD 9, 10, 11 -55oC, +25oC, +125oC 375 - ns
Control Trailing Edge to Leading Edge of Next

Control
Data Hold Time After READ INTA TRDH 9, 10, 11 -55oC, +25oC, +125oC- 0 ns
READY Hold Time TRYH 9, 10, 11 -55oC, +25oC, +125oC- 0 ns
READY Setup Time to Leading Edge of CLK TRYS 9, 10, 11 -55oC, +25oC, +125oC 250 - ns
Data Valid After Trailing Edge of WRITE TWD 9, 10, 11 -55oC, +25oC, +125oC 150 - ns
LEADING Edge of WRITE to Data Valid TWDL 9, 10, 11 -55oC, +25oC, +125oC - 50 ns

NOTES:

1. Output timings are measured with a purely capacitive load, CL = 150pF

2. VDD = 4.75V, VIH = 4.25V, VIL = 0.8V

3. Delay times are measured with a 1MHz clock. An algorithm is used to convert the delays into the AC timings above with a TCYC = 500ns.

4. The AC table is tested as shown above to guarantee the processor system timing.

5. A8 - A15 address specifications also apply to IO/M, S0 and S1 except A8 - A15 are undefined during T4-T6 of off cycle whereas IO/M,
So, and S1 are stable.

TARY 9, 10, 11 -55oC, +25oC, +125oC 250 - ns

TCC 9, 10, 11 -55oC, +25oC, +125oC 575 - ns

TINS 9, 10, 11 -55oC, +25oC, +125oC - 375 ns

TRAE 9, 10, 11 -55oC, +25oC, +125oC 120 - ns

TRV 9, 10, 11 -55oC, +25oC, +125oC 550 - ns

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

Spec Number 518054

6