Intersil Corporation HS-80C85RH Datasheet

February 1996

HS-80C85RH

Radiation Hardened

8-Bit CMOS Microprocessor

Features

• Devices QML Qualified in Accordance With
MIL-PRF-38535

• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95824 and Intersil’ QM Plan

• Radiation Hardened EPI-CMOS

- Parametrics Guaranteed 1 x 10

- Transient Upset > 1 x 10

- Latch-up Free > 1 x 10

12

5

8

RAD(Si)

RAD(Si)/s

RAD(Si)/s

• Low Standby Current 500µA Max

• Low Operating Current 5.0mA/MHz (X

Input)

1

• Electrically Equivalent to Sandia SA 3000

• 100% Software Compatible with INTEL 8085

• Operation from DC to 2MHz, Post Radiation

• Single 5 Volt Power Supply

• On-Chip Clock Generator and System Controller

• Four Vectored Interrupt Inputs

• Completely Static Design

• Self Aligned Junction Isolated (SAJI) Process

o

• Military Temperature Range -55

C to +125oC

Pinouts

40 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835, CDIP2-T40

TOP VIEW

X1
X2

RESET OUT

SOD

SID

TRAP

RST 7.5
RST 6.5

RST 5.5

INTR
INTA

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

GND

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

VDD

40

HOLD

39

HLDA

38

CLOCK OUT

37
36

RESET IN
READY

35
34

IO / M
S1

33

RD

32
31

WR
ALE

30
29

S0
A15

28

A14

27

A13

26

A12

25

A11

24
23

A10
A9

22

A8

21

Description

The HS-80C85RH is an 8-bit CMOS microprocessor fabri­cated using the Intersil radiation hardened self-aligned junc­tion isolated (SAJI) silicon gate technology. Latch-up free
operation is achieved by the use of epitaxial starting material
to eliminate the parasitic SCR effect seen in conventional
bulk CMOS devices.

The HS-80C85RH is a functional logic emulation of the
HMOS 8085 and its instruction set is 100% software com­patible with the HMOS device. The HS80C85RH is designed
for operation with a single 5 volt power supply. Its high level
of integration allows the construction of a radiation hardened
microcomputer system with as few as three ICs (HS­80C85RH CPU, HS83C55RH ROM I/O, and the HS-81C55/
56RH RAM I/O.

42 LEAD CERAMIC METAL SEAL

FLATPACK PACKAGE (FLATPACK)

INTERSIL OUTLINE K42.A

TOP VIEW

X1
X2

RESET

OUT
SOD

SID

TRAP

RST 7.5
RST 6.5

RST 5.5

INTR
INTA

AD0
AD1
AD2
AD3
AD4

NC
NC

AD5
AD6
AD7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

19
20
21

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

24
23
22

VDD
HOLD
HLDA

CLOCK
OUT
RESET
IN
READY

M

IO /
S1
RD

WR
ALE
S0
A15
A14
A13
A12
A11

A10
A9
A8
GND

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

1

Spec Number

518054

File Number 3036.2

HS-80C85RH

Ordering Information

PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE

5962R9582401QQC -55oC to +125oC MIL-PRF-38535 Level Q 40 Lead SBDIP
5962R9582401QXC -55oC to +125oC MIL-PRF-38535 Level Q 42 Lead Ceramic Flatpack
5962R9582401VQC -55oC to +125oC MIL-PRF-38535 Level V 40 Lead SBDIP
5962R9582401VXC -55oC to +125oC MIL-PRF-38535 Level V 42 Lead Ceramic Flatpack
HS1-80C85RH/SAMPLE +25oC Sample 40 Lead SBDIP
HS9-80C85RH/SAMPLE +25oC Sample 42 Lead Ceramic Flatpack

Functional Diagram

RST

RST

INTA

INTR

INTERRUPT CONTROL SERIAL I/O CONTROL

5.5

RST

6.5

7.5

TRAP

8-BIT

INTERNAL DATA BUS

SID SOD

ACCUMU­LATOR (8)

POWER

SUPPLY

X1
X2

TEMP REG

(8)

VDD
GND

CLK
GEN

READY
CLK
OUT

FLAG (5)

FLIP FLOPS

ARITHMETIC

LOGIC

UNIT

(ALU) (8)

TIMING AND CONTROL

CONTROL STATUS DMA

WR

RD

S0

ALE

INSTRUCTION

REGISTER (8)

INSTRUCTION

DECODER

AND MACHINE

ENCODING

IO/M HLDA

S1

HOLD

CYCLE

RESET

RESET

IN

B REG (8)
D REG (8)
H REG (8)

STACK POINTER (16)

PROGRAM COUNTER (16)

INCREMENTER

DECREMENTER

ADDRESS LATCH (16)

RESET

OUT

C REG (8)
E REG (8)
L REG (8)

ADDRESS

BUFFER (8)

A15-A8

ADDRESS

BUS

REGISTER ARRAY

DATA ADDRESS

BUFFER (8)

AD1-AD0

ADDRESS

BUS

Spec Number 518054

2

HS-80C85RH

Pin Description

PIN

SYMBOL

A8 - A15 21-28 O Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address,

AD0-7 12-19 I/O Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/O address) appear on

ALE 32 O Address Latch Enable: It occurs during the first clock state of a machine cycle and enables the

NUMBER TYPE DESCRIPTION

3-stated during Hold and Halt modes and during RESET.

the bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus
during the second and third clock cycles.

address to get latched into the on-chip latch of peripherals. The falling edge of ALE is set to guar­antee setup and hold times for the address information. The falling edge of ALE can also be used
to strobe the status information. ALE is never 3-stated.

S0, S1, and

IO/M

RD 34 O Read Control: A low level on RD indicates the selected memory or I/O device is to be read and

WR 33 O Write Control: A low level on WR indicates the data on the Data Bus is to be written into the se-

31, 35,

& 36

O Machine Cycle Status:

IO/M S1 S0 Status

0 0 1 Memory write
0 1 0 Memory write
1 0 1 I/O write
1 1 0 I/O read
0 1 1 Opcode fetch
1 1 1 Opcode fetch
1 1 1 Interrupt acknowledge
T 0 0 Halt
T X X Hold
T X X Reset

T = 3-State (high impedance)
X = Unspecified

S1 can be used as an advanced R/W status. IO/M, S0 and S1 become valid at the beginning of
a machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used
to latch the state of these lines.

that the Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and dur­ing RESET.

lected memory or I/O location. Data is set up at the trailing edge of WR, 3-stated during Hold and
Halt modes and during RESET.

READY 35 I Ready: If READY is high during a read or write cycle, it indicates that the memory or peripheral

is ready to send or receive data. If READY is low, the cpu will wait an integral number of clock
cycles for READY to go high before completing the read or write cycle. READY must conform to
specified setup and hold times.

HOLD 39 I Hold: Indicates that another master is requesting the use of the address and data buses. The

cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion
of the current bus transfer. Internal processing can continue. The processor can regain the bus
only after the HOLD is removed. When the HOLD is acknowledged, the Address, Data Bus, RD,
WR, and IO/M lines are 3-stated.

HLDA 38 O Hold Acknowledge: Indicates that the cpu has received the HOLD request and that it will relin-

quish the bus in the next clock cycle. HLDA goes low after the Hold request is removed. The cpu
takes the bus one half clock cycle after HLDA goes low.

Spec Number 518054

3

HS-80C85RH

Pin Description

SYMBOL

INTR 10 I Interrupt Request: Is used as a general purpose interrupt. It is sampled only during the next to

INTA 11 O Interrupt Acknowledge: Is used instead of (and has the same timing as) RD during the Instruc-

RST 5.5
RST 6.5
RST 7.5

TRAP 6 I Trap: Trap interrupt is a non-maskable RESTART interrupt. It is recognized at the same time as

RESET IN 36 I Reset In: Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops.

(Continued)

PIN

NUMBER TYPE DESCRIPTION

the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program
Counter (PC) will be inhibited from incrementing and an
RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR
is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is
accepted.

tion cycle after an INTR is accepted. It can be used to activate an 8259A Interrupt chip or some
other interrupt port.

9
8
7

I Restart Interrupts: These three inputs have the same timing as INTR except they cause an

internal RESTART to be automatically inserted.
The priority of these interrupts is ordered as shown in Table 6. These interrupts have a higher
priority than INTR. In addition, they may be individually masked out using the SIM instruction.

INTR or RST 5.5-7.5. It is unaffected by any mask or Interrupt Enable. It has the highest priority
of any interrupt. (See Table 6.)

The data and address buses and the control lines are 3-stated during RESET and because of
the asynchronous nature of RESET the processor’s internal registers and flags may be altered
by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing connec­tion to an R-C network for power-on RESET delay (see Figure 1). Upon power-up, RESET IN
must remain low for at least 10 “clock cycle” after minimum VDD has been reached. For proper
reset operation after the power-up duration, RESET IN should be kept low a minimum of three
clock periods. The CPU is held in the reset condition as long as RESET IN is applied.

INTA will be issued. During this cycle a

RESET OUT 3 O Reset Out: Reset Out indicates cpu is being reset. Can be used as a system reset. The signal

is synchronized to the processor clock and lasts an integral number of clock periods.

X1
X2

CLK 37 O Clock: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input

SID 5 I Serial Input Data Line: The data on this line is loaded into accumulator bit 7 whenever a RIM

SOD 4 O Serial Output Data Line: The output SOD is set or reset as specified by the SlM instruction.

VCC 40 I Power: +5V supply.

GND 20 I Ground: Reference.

1
2

VDD

I

X1 and X2: Are connected to a crystal, LC, or RC network to drive the internal clock generator.

O

X, can also be an external clock Input from a logic gate. The input frequency is divided by 2 to
give the processor’s internal operating frequency.

period.

instruction is executed.

RESET IN

R1

C1

TYPICAL POWER-ON RESET RC VALUES
R1 = 75KΩ
C1 = 1µF

†

† Values may have to vary due to applied power supply ramp up time.

FIGURE 1. POWER-ON RESET CIRCUIT

4

Spec Number 518054

Specifications HS-80C85RH

Absolute Maximum Ratings Reliability Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V

Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VCC+0.3V

Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC

Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC

Typical Derating Factor. . . . . . . . . . .2.0mA/MHz Increase in IDDOP

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions

Operating Supply Voltage Range (VDD) . . . . . . . +4.75V to +5.25V

Operating Temperature Range (TA) . . . . . . . . . . . . -55oC to +125oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

PARAMETER SYMBOL CONDITIONS

Input Leakage
Current

High Level Output
Voltage

Low Level Output
Voltage

Static Current IDDSB VDD = 5.25V, Clock Out = Hi

Operating Supply
Current (Note 2)

Functional Tests FT VDD = 4.75V and 5.25V,

NOTES:

1. All devices guaranteed at worst case limits and over radiation.

2. Operating supply current (IDDOP) is proportional to crystal frequency. Parts are tested at 1MHz

IIH or

IIL

VOH VDD = 4.75V, IOH = -1.0mA 1, 2, 3 -55oC, +25oC, or

VOL VDD = 5.25V, IOL = 1.0mA, 1, 2, 3 -55oC, +25oC, or

IDDOP VDD = 5.25V, f = 1MHz

VDD = 5.25V, VI = VDD
or GND

and Low

(Note 2)

TCYC = 500ns,
VOL ≤ VDD/2, VOH≥VDD/2

Thermal Resistance θ

SBDIP Package. . . . . . . . . . . . . . . . . . . . 45oC/W 10oC/W

Ceramic Flatpack Package . . . . . . . . . . . 77oC/W 13oC/W

Maximum Package Power Dissipation at +125oC Ambient

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11W

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.65W

If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22.2mW/oC

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . .13.0mW/oC

Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V

Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VDD -0.5V to VDD

GROUP A

SUBGROUPS TEMPERATURE

1, 2, 3 -55oC, +25oC, or

+125oC

+125oC

+125oC

1, 2, 3 -55oC, +25oC, or

+125oC

1, 2, 3 -55oC, +25oC, or

+125oC

7, 8A, 8B -55oC, +25oC, or

+125oC

LIMITS

-1.0 1.0 µA

VDD -0.5 - V

- 0.5 V

- 500 µA

- 5.0 mA/MHz

-- -

JA

θ

JC

UNITSMIN MAX

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP A

PARAMETER SYMBOL

CLK Low Time (Standard CLK Loading) T1 9, 10, 11 -55oC, +25oC, +125oC40 - ns
CLK High Time (Standard CLK Loading) T2 9, 10, 11 -55oC, +25oC, +125oC 100 - ns
CLK Rise Time Tr 9, 10, 11 -55oC, +25oC, +125oC - 115 ns
CLK Fall Time Tf 9, 10, 11 -55oC, +25oC, +125oC - 115 ns
X1 Rising to CLK Rising TXKR 9, 10, 11 -55oC, +25oC, +125oC 30 250 ns
X1 Rising to CLK Falling TXKF 9, 10, 11 -55oC, +25oC, +125oC 50 275 ns
A8-15 Valid to Leading Edge of Control (Note 5) TAC 9, 10, 11 -55oC, +25oC, +125oC 300 - ns
A0-7 Valid to Leading Edge of Control TACL 9, 10, 11 -55oC, +25oC, +125oC 300 - ns
A0-15 Valid to Valid Data In TAD 9, 10, 11 -55oC, +25oC, +125oC 875 - ns
Address Float After Leading Edge of READ

(INTA)

TAFR 9, 10, 11 -55oC, +25oC, +125oC - 70 ns

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

Spec Number 518054

5

Specifications HS-80C85RH

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

GROUP A

PARAMETER SYMBOL

A8-15 Valid Before Trailing Edge of ALE (Note 5) TAL 9, 10, 11 -55oC, +25oC, +125oC75 - ns
A0-7 Valid Before Trailing Edge of ALE tALL 9, 10, 11 -55oC, +25oC, +125oC 125 - ns
READY Valid from Address

Valid
Address (A8-15) Valid After Control TCA 9, 10, 11 -55oC, +25oC, +125oC 150 - ns
Width of Control Low (RD, WR, INTA) Edge of

ALE
Trailing Edge of Control to Leading Edge of ALE TCL 9, 10, 11 -55oC, +25oC, +125oC60 - ns
Data Valid to Trailing Edge of WRITE TDW 9, 10, 11 -55oC, +25oC, +125oC 575 - ns
HLDA to Bus Enable THABE 9, 10, 11 -55oC, +25oC, +125oC - 375 ns
Bus Float After HLDA THABF 9, 10, 11 -55oC, +25oC, +125oC - 375 ns
HLDA Valid to Trailing Edge of CLK THACK 9, 10, 11 -55oC, +25oC, +125oC90 - ns
HOLD Hold Time THDH 9, 10, 11 -55oC, +25oC, +125oC- 0 ns
HOLD Setup Time to Trailing Edge of CLK THDS 9, 10, 11 -55oC, +25oC, +125oC - 300 ns
INTR Hold Time TINH 9, 10, 11 -55oC, +25oC, +125oC- 0 ns
INTR, RST and TRAP Setup Time to Falling

Edge of CLK
Address Hold Time After ALE TLA 9, 10, 11 -55oC, +25oC, +125oC75 - ns
Trailing Edge of ALE to Leading Edge of Control TLC 9, 10, 11 -55oC, +25oC, +125oC 150 - ns
ALE Low During CLK High TLCK 9, 10, 11 -55oC, +25oC, +125oC 125 - ns
ALE to Valid Data During Read TLDR 9, 10, 11 -55oC, +25oC, +125oC 675 - ns
ALE to Valid Data During Write TLDW 9, 10, 11 -55oC, +25oC, +125oC - 350 ns
ALE Width TLL 9, 10, 11 -55oC, +25oC, +125oC 200 - ns
ALE to READY Stable TLRY 9, 10, 11 -55oC, +25oC, +125oC - 175 ns
Trailing Edge of READ to Re-Enabling the Ad-

dress
READ (or INTA) to Valid Data TRD 9, 10, 11 -55oC, +25oC, +125oC 375 - ns
Control Trailing Edge to Leading Edge of Next

Control
Data Hold Time After READ INTA TRDH 9, 10, 11 -55oC, +25oC, +125oC- 0 ns
READY Hold Time TRYH 9, 10, 11 -55oC, +25oC, +125oC- 0 ns
READY Setup Time to Leading Edge of CLK TRYS 9, 10, 11 -55oC, +25oC, +125oC 250 - ns
Data Valid After Trailing Edge of WRITE TWD 9, 10, 11 -55oC, +25oC, +125oC 150 - ns
LEADING Edge of WRITE to Data Valid TWDL 9, 10, 11 -55oC, +25oC, +125oC - 50 ns

NOTES:

1. Output timings are measured with a purely capacitive load, CL = 150pF

2. VDD = 4.75V, VIH = 4.25V, VIL = 0.8V

3. Delay times are measured with a 1MHz clock. An algorithm is used to convert the delays into the AC timings above with a TCYC = 500ns.

4. The AC table is tested as shown above to guarantee the processor system timing.

5. A8 - A15 address specifications also apply to IO/M, S0 and S1 except A8 - A15 are undefined during T4-T6 of off cycle whereas IO/M,
So, and S1 are stable.

TARY 9, 10, 11 -55oC, +25oC, +125oC 250 - ns

TCC 9, 10, 11 -55oC, +25oC, +125oC 575 - ns

TINS 9, 10, 11 -55oC, +25oC, +125oC - 375 ns

TRAE 9, 10, 11 -55oC, +25oC, +125oC 120 - ns

TRV 9, 10, 11 -55oC, +25oC, +125oC 550 - ns

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

Spec Number 518054

6

Specifications HS-80C85RH

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

(NOTE 1)

PARAMETER SYMBOL

Input Capacitance CIN VDD = Open, f = 1MHz TA = +25oC - 12 pF
I/O Capacitance CI/O VDD = Open, f = 1MHz TA = +25oC - 13 pF
Output Capacitance COUT VDD = Open, f = 1MHz TA = +25oC - 12 pF

NOTE:

1. All measurements referenced to device ground.

TABLE 4. POST 100K RAD ELECTRICAL PERFORMANCE CHARACTERISTICS

NOTE: The post irradiation test conditions and limits are the same as those listed in Tables 1 and 2.

TABLE 5. BURN-IN DELTA PARAMETERS (+25oC; In Accordance With SMD)

TABLE 6. INTERRUPT PRIORITY, RESTART ADDRESS, AND SENSITIVITY

ADDRESS BRANCHED TO (1)

NAME PRIORITY

TRAP 1 24H Rising edge and high level until sampled.
RST 7.5 2 3CH Rising edge (latched)

CONDITIONS TEMPERATURE

WHEN INTERRUPT OCCURS TYPE TRIGGER

LIMITS

UNITSMIN MAX

RST 6.5 3 34CH High level until sampled.
RST 5.5 4 2CH High level until sampled.
INTR 5 See Note 2 High level until sampled.

NOTES:

1. The processor pushes the PC on the stack before branching to the indicated address.

2. The address branched to depends on the instruction provided to the cpu when the interrupt is acknowledged.

TABLE 7. BUS TIMING SPECIFICATION AS A t

SYMBOL HS-8OC85RH SYMBOL HS-8OC85RH

tAL (1/2)T- 175 Minimum tCC (3/2 + N)T - 175 Minimum
tLA (1/2)T- 175 Minimum tCL (1/2)T - 190 Minimum
tLL (1/2)T-50 Minimum tARY (3/2)T - 500 Maximum

tLCK (1/2)T- 125 Minimum tHACK (1/2)T - 160 Minimum

tLC (1/2)T- 100 Minimum tHABF (1/2)T +125 Maximum
tAD (5/2 + N)T - 375 Maximum tHABE (1/2)T +125 Maximum
tRD (3/2 + N)T - 375 Maximum tAC (2/2)T - 200 Minimum

tRAE (1/2)T- 130 Minimum t1 (1/2)T-210 Minimum

tCA (1/2)T - 100 Minimum t2 (1/2)T- 150 Minimum

DEPENDENT

CYC

tDW (3/2 + N)T - 175 Minimum tRV (3/2)T - 200 Minimum
tWD (1/2)T-100 Minimum tLDR (4/2)T - 325 Maximum

NOTE: N is equal to the total WAIT states T = tCYC

Spec Number 518054

7

Waveforms

X

INPUT

1

HS-80C85RH

CLK

OUTPUT

CLK

A

8-15

AD0-AD

ALE

RD/INTA

tXKR

7

tXKF

tLL tLA

tAL

tr

t1

tCYC

t2

tf

FIGURE 2. CLOCK

T1 T2 T3 T1

tLCK

ADDRESS

ADDRESS

tAFR

tLC

tAC

tAD

tRDH

DATA IN

tLDR

tRD

tCC

tCA

tRAE

tCL

AD

A

0

CLK

8-15

-AD

ALE

WR

FIGURE 3. READ

T1T3T2T1

tLCK

ADDRESS

tLDW

7

tAL

ADDRESS

tAC

tLAtLL

tLC

tDW

tWDL

tCC

DATA OUT

tCA

tWD

tCL

FIGURE 4. WRITE

Spec Number 518054

8

HS-80C85RH

Waveforms

CLK

HOLD

HLDA

BUS (ADDRESS, CONTROLS)

CLK

A

8-15

AD0-AD

ALE

RD/INTA

READY

(Continued)

T2

7

T2 THOLD THOLD T1

tHDS

tHDH

tHACK

tHABF

tHABE

FIGURE 5. HOLD

T1 T2 TWAIT T3 T3

tLCK

ADDRESS

tAD

ADDRESS DATA IN

tAC

tARY

tLA

tLC
tLRY

tAFR

tLDR

tRD

tRYHtRYS tRYS tRYH

tCC

tLL

tAL

tRDH

tCA

tRAE

tCL

NOTE 1: READY MUST REMAIN STABLE DURING SETUP AND HOLD TIMES.

FIGURE 6. READ OPERATION WITH WAIT CYCLE (TYPICAL) - SAME READY TIMING APPLIES TO WRITE

T1 T2 T3 T4 T5 T6 THOLD T1 T2

A8-15

INTR

tINS

A0-7

RD

INTR

HOLD

HLDA

tINH

tHDS

tHDH

CALL INST.

tHACK

BUS FLOATING†

tHABF

FIGURE 7. INTERRUPT AND HOLD

9

tHABE

† IO/M IS ALSO FLOATING DURING THIS TIME.

Spec Number 518054

HS-80C85RH

TABLE 9. INSTRUCTION SET SUMMARY

INSTRUCTION CODE

MNEMONIC

MOVE, LOAD, AND STORE
MOVr1, r2 0 1 D D D S S S Move register to

MOV M.r 01110SSSMove register to

MOV r.M 0 1 D D D 1 1 0 Move memory to

MVl r 0 0 D D D 1 1 0 Move immediate

MVl M 00110110Move immediate

LXl B 00000001Load immediate

LXl D 00010001Load immediate

LXl H 00100001Load immediate

STAX B 00000010Store A indirect
STAX D 00010010Store A indirect
LDAX B 00001010Load A indirect
LDAX D 00011010Load A indirect
STA 00110010Store A direct
LDA 00111010Load A direct
SHLD 00100010Store H & L direct
LHLD 00101010Load H & L direct
XCHG 11101011Exchange D & E,

STACK OPS
PUSH B 11000101Push register Pair

PUSH D 1 1 010101Push register Pair

PUSH H 1 1 1 0 0 1 0 1 Push register Pair

PUSH PSW 1 1 110101Push A and Flags

CZ 11001100Call on zero
CNZ 11000100Call on no zero
CP 11110100Call on positive
CM 11111100Call on minus
CPE 11101100Call on parity even
CPO 11100100Call on parity odd
RETURN
RET 11001001Return
RC 11011000Return on carry
RNC 11010000Return on no carry
RZ 11001000Return on zero

7D6D5D4D3D2D1D0

OPERATIONS

DESCRIPTIOND

register

memory

register

register

memory

register Pair B & C

register Pair D & E

register Pair H & L

H & L Registers

B & C on stack

D & E on stack

H & L on stack

on stack

INSTRUCTION CODE

MNEMONIC

RNZ 11000000Return on no zero
RP 11110000Return on positive
RM 11111000Return on minus
RPE 11101000Return on parity

RPO 11100000Return on parity

RESTART
RST 1 1 A A A 1 1 1 Restart
INPUT/OUTPUT
IN 11011011Input
OUT 11010011Output
INCREMENT AND DECREMENT
INR r 0 0 D D D 1 0 0 Increment register
DCR r 0 0 D D D 1 0 1 Decrement register
INR M 00110100Increment memory
DCR M 00110101Decrement memory
INX B 00000011Increment B & C

INX D 00010011Increment D & E

POP B 11000001Pop register Pair B

POP D 11010001Pop register Pair D

POP H 11100001Popregister Pair

POP PSW 11110001Pop A and Flags off

XTHL 11100011Exchange top ot

SPHL 11111001H & L to stack

LXI SP 00110001Load immediate

INX SP 00110011Increment stack

DCX SP 00111011Decrement stack

JUMP
JMP 11000011Jump unconditional
JC 11011010Jump on carry
JNC 11010010Jump on no carry
JZ 11001010Jump on zero
JNZ 11000010Jump on no zero
JP 11110010Jump on positive
JM 11111010Jump on minus

7D6D5D4D3D2D1D0

OPERATIONS

DESCRIPTIOND

even

odd

registers

registers

& C off stack

& E off stack

H & L off stack

stack

stack, H & L

pointer

stack pointer

pointer

pointer

10

Spec Number 518054

HS-80C85RH

TABLE 9. INSTRUCTION SET SUMMARY (Continued)

INSTRUCTION CODE

MNEMONIC

JPE 11101010Jump on parity

JPO 11100010Jump on parity odd
PCHL 11101001H & L to program

CALL
CALL 11001101Call unconditional
CC 11011100Call on carry
CNC 11010100Call on no carry
LOGICAL
ANA r 10100SSSAnd register with A
XRA r 10101SSSExclusive OR

ORA r 10110SSSOR register with A
CMP r 10111SSSCompare register

ANA M 10100110And memory with A
XRA M 10101110Exclusive OR mem-

ORA M 10110110OR memory with A
CMP M 10111110Compare memory

ANI 11100110And immediate

XRI 11101110Exclusive OR

ORl 11110110OR immediate

CPl 11111110Compare immedi-

ROTATE
RLC 00000111Rotate A left
RRC 00001111Rotate A right
RAL 00010111Rotate A left

RAR 00011111Rotate A right

INX H 00100011Increment H & L

DCX B 00001011Decrement B & C
DCX D 00011011Decrement D & E
DCX H 00101011Decrement H & L
ADD
ADD r 10000SSSAdd register to A
ADC r 10001SSSAdd register to A

ADD M 1 0 C 00110Add memory to A

7D6D5D4D3D2D1D0

OPERATIONS

DESCRIPTIOND

even

counter

register with A

with A

ory with A

with A

with A

immediate with A

with A

ate with A

through carry

through carry

registers

with carry

INSTRUCTION CODE

MNEMONIC

ADC M 10001110Add memory to A

ADl 11000110Add immediate to A
ACl 11001110Add immediate to A

DAD B 00001001Add B & C to H & L
DAD D 00011001Add D & E to H & L
DAD H 00101001Add H & L to H & L
DAD SP 00111001Add stack pointer to

SUBTRACT
SUB r 10010SSSSubtract register

SBB r 10011SSSSubtract register

SUB M 10010110Subtract memory

SBB M 10011110Subtract memory

SUl 11010110Subtract immedi-

SBl 11011110Subtract immedi-

SPECIALS
CMA 00101111Complement A
STC 00110111Set carry
CMC 00111111Complement carry
DAA 00100111Decimal adjust A
CONTROL
El 11111011Enable Interrupts
DI 11110011Disable Interrupt
NOP 00000000No-operation
HLT 01110110Halt
RIM 00100000Read Interrupt

SlM 00110000Set Interrupt Mask

NOTES:

1. DDS or SSS: B000, C001, D010, E011, H100, L101, Memory 110, A111

2. Two possible cycle times (6/12) indicate instruction cycles dependent on condi­tion flags.

7D6D5D4D3D2D1D0

OPERATIONS

DESCRIPTIOND

with carry

with carry

H&L

from A

from A with borrow

from A

from A with borrow

ate from A

ate from A with
borrow

Mask

† All mnemonics copyrighted „ Intel Corporation 1976

11

Spec Number 518054

HS-80C85RH

Functional Description

The HS-80C85RH is a complete 8-bit parallel central pro­cessing unit implemented in a self aligned, silicon gate,
CMOS technology. Its static design allows the device to be
operated at any external clock frequency from a maximum of
4MHz down to DC. The processor clock can be stopped in
either the high or low state and held there indefinitely. This
type of operation is especially useful for system debug or
power critical applications. The device is designed to fit into
a minimum system of three ICs: CPU (HS-80C85RH), RAM/
IO (HS-81C55/56RH) and ROM/IO Chip (HS-83C55RH).

Since the HS-80C85RH is implemented in CMOS, all of the
advantages of CMOS technology are inherent in the device.
These advantages include low standby and operating power,
high noise immunity, moderately high speed, wide operating
temperature range, and designed-in radiation hardness.
Thus the HS-80C85RH is ideal for weapons and space
applications.

The HS-80C85RH has twelve addressable 8-bit registers.
Four of them can function only as two 16-bit register pairs.
Six others can be used interchangeably as 8-bit registers or
as 16-bit register pairs. The HS-80C85RH register set is as
follows:

MNEMONIC REGISTER CONTENTS

ACC or A Accumulator 8 -bits

PC Program Counter 16-bit Address

BC, DE, HL General-Purpose

Registers; Data
Pointer(HL)

SP Stack Pointer 16-bit Address

Flags or F Flag Register 5 Flags (8-bit space)

The HS-80C85RH uses a multiplexed Data Bus. The
address is split between the higher 8-bit Address Bus and
the lower 8-bit Address/Data Bus. During the first T state
(clock cycle) of a machine cycle the low order address is
sent out on the Address/Data bus. These lower 8 bits may
be latched externally by the Address Latch Enable signal
(ALE). During the rest of the machine cycle the data bus is
used for memory or I/O data.

The HS-80C85RH provides

RD, WR, S0, S1, and IO/M sig­nals for bus control. An Interrupt Acknowledge signal (
is also provided. HOLD and all Interrupts are synchronized
with the processor’s internal clock. The HS-80C85RH also
provides Serial Input Data (SID) and Serial Output Data
(SOD) lines for simple serial interface.

In addition to these features, the HS-80C85RH has three
maskable, vector interrupt pins, one nonmaskable TRAP
interrupt, and a bus vectored interrupt, INTR.

Interrupt and Serial I/O

The HS-80C85RH has 5 interrupt inputs: INTR, RST 5.5,
RST 6.5, RST 7.5, and TRAP INTR is maskable (can be

8-bits x 6 or
16-bits x 3

INTA)

enabled or disabled by El or Dl software instructions), and
causes the CPU to fetch in an RST instruction, externally
placed on the data bus, which vectors a branch to any one of
eight fixed memory locations (Restart addresses). The deci­mal addresses of these dedicated locations are: 0, 8, 16,
24, 32, 40, 48, and 56. Any of these addresses may be used
to store the first instruction(s) of a routine designed to
service the requirements of an interrupting device. Since the
(RST) is a call, completion of the instruction also stores the
old program counter contents on the STACK. Each of the
three RESTART inputs, 5.5, 6.5, and 7.5, has a programma­ble mask. TRAP is also a RESTART interrupt but it is
nonmaskable.

The three maskable interrupts cause the internal execution
of RESTART (saving the program counter in the stack and
branching to the RESTART address) if the interrupts are
enabled and if the interrupt mask is not set. The non­maskable TRAP causes the internal execution of a
RESTART vector independent of the state of the interrupt
enable or masks. (See Table 9.)

There are two different types of inputs in the restart
interrupts. RST 5.5 and RST 6.5 are high level-sensitive and
are recognized with the same timing as INTR. RST 7.5 is
rising edge sensitive.

For RST 7.5, only a pulse is required to set an internal
flipflop which generates the internal interrupt request (a
normally high level signal with a low going pulse is recom­mended for highest system noise immunity). The RST 7.5
request flip-flop remains set until the request is serviced.
Then it is reset automatically. This flip-flop may also be reset
by using the SlM instruction or by issuing a

RESET IN to the
80C85RH. The RST 7.5 internal flip-flop will be set by a
pulse on the RST 7.5 pin even when the RST 7.5 interrupt is
masked out.

The status of the three RST interrupt masks can only be
affected by the SIM instruction and

RESET IN.

The interrupts are arranged in a fixed priority that determines
which interrupt is to be recognized if more than one is
pending as follows: TRAP-highest priority, RST 7.5, RST

6.5, RST 5.5, INTR-lowest priority . This priority scheme does
not take into account the priority of a routine that was started
by a higher priority interrupt. RST 5.5 can interrupt an RST

7.5 routine if the interrupts are re-enabled before the end of
the RST 7.5 routine.

The TRAP interrupt is useful for catastrophic events such as
power failure or bus error. The TRAP input is recognized just
as any other interrupt but has the highest priority. It is not
affected by any flag or mask. The TRAP input is both edge
and level sensitive. The TRAP input must go high and
remain high until it is acknowledged. It will not be recognized
again until it goes low, then high again. This avoids any false
triggering due to noise or logic glitches. Figure 8illustrates
the TRAP interrupt request circuitry within the HS-80C85RH.
Note that the servicing of any interrupt (TRAP, RST 7.5, RST

6.5, RST 5.5, INTR) disables all future interrupts (except
TRAPs) until an EI instruction is executed.

12

Spec Number

518054

HS-80C85RH

EXTERNAL
TRAP

INTERRUPT
REQUEST

RESET IN

INSIDE THE
80C85RH

TRAP

SCHMITT
TRIGGER

ACKNOWLEDGE

RESET

INTERNAL

TRAP

VDD

CLK

D

Q

D

F/F

CLEAR

TRAP F.F.

TRAP

INTERRUPT

REQUEST

FIGURE 8. TRAP AND RESET IN CIRCUIT

The TRAP interrupt is special in that is disables interrupts,
but preserves the previous interrupt enable status. Perform­ing the first RIM instruction following a TRAP interrupt allows
you to determine whether interrupts were enabled or
disabled prior to the TRAP. All subsequent RIM instructions
provide current interrupt enable status. Performing a RIM
instruction following INTR, or RST 5.5-7.5 will provide
current interrupt enable status, revealing that interrupts are
disabled.

The serial I/O system is also controlled by the RIM and SIM
instructions. SID is read by RIM, and SIM sets the SOD
data.

Driving the X1 and X2 Inputs

You may drive the clock inputs of the HS-80C85RH with a
crystal, an LC tuned circuit, an RC network, or an external
clock source. The driving frequency may be any value from
DC to 4MHz and must be twice the desired internal clock
frequency.

The following guidelines should be observed when a crystal
is used to drive the HS-80C85RH clock input:

1. A 20pF capacitor should be connected from X2 to ground to
assure oscillator start-up at the correct frequency.

2. A 10MΩ resistor is required between X1 and X2 for bias point
stabilization. In addition, the crystal should have the following
characteristics:

1) Parallel resonance at twice the desired internal clock

frequency

2) CL (load capacitance) ≤ 30pF

3) CS (shunt capacitance) ≤ 7pF

4) RS (equivalent shunt resistance) ≤ 75Ω

5) Drive level: 10mW

6) Frequency tolerance: ±0.005% (suggested)

A parallel-resonant LC circuit may be used as the frequency­determining network for the HS-80C85RH, providing that its
frequency tolerance of approximately ±10% is acceptable.
The components are chosen from the formula:

1

f =

2π√

L (Cext + Cint)
To minimize variations in frequency, it is recommended that
you choose a value for Cext that is at least twice that of Cint,
or 30pF. The use of an LC circuit is not recommended for
frequencies higher than approximately 4MHz.

An RC circuit may be used as the frequency-determining
network for the HS-80C85RH if maintaining a precise clock
frequency is of no importance. Variations in the on-chip tim­ing generation can cause a wide variation in frequency when
using the RC mode. Its advantage is its low component cost.
The driving frequency generated by the circuit shown is
approximately 3MHz. It is not recommended that frequen­cies greatly higher or lower than this be attempted.

Figure 9 shows the recommended clock driver circuits.
For driving frequencies up to and including 4MHz you may

supply the driving signal to X1 and leave X2 open-circuited
(Figure 9D).

80C85RH

20pF

REXT =
10MΩ

X1

1

2

X2

80C85RH

CINT =
15pF

20pF

-6K

X1

1

2

X2

a.) QUARTZ CRYSTAL CLOCK DRIVER c.) RC CIRCUIT CLOCK DRIVER

LEXT

CEXT

LOW TIME > 60ns

X1

1

2

X2

80C85RH

CINT =
15pF

†

X1

X2

† X2 Left Floating

b.) LC TUNED CIRCUIT CLOCK DRIVER d.) 0-4MHz INPUT FREQUENCY EXTERNAL CLOCK DRIVER

CIRCUIT

FIGURE 9. CLOCK DRIVER CIRCUITS

Spec Number 518054

13

HS-80C85RH

HS-80C85RH Caveats

1. An important caveat that is applicable to CMOS devices in gen­eral is that unused inputs should never be left floating. This rule
also applies to inputs connected to a tri- state bus. The need for
external pull-up resistors during tri-state bus conditions is elimi­nated by the presence of regenerative latches on the following
HS-80C85RH output pins: AD0-AD7, A8-A15, and IO/M. Figure
10 depicts an output and corresponding regenerative latch.
When the output driver assumes the high impedance state, the
latch holds the bus in whatever logic state (high or low) it was be­fore the tri-state condition. A transient drive current of approxi­mately ±1.0mA at 0.5 VDD for 10nsec is required to switch the
latch. Thus, CMOS device inputs connected to the bus are not
allowed to float during tri-state conditions.

2. The RD and WR pins of the HS-80C85RH contain internal dy­namic pull-up transistors to avoid spurious selection of memory
devices when the RD and WR pins assume the high impedance
state. This eliminates the need for external resistive pull-ups on
these pins.

3. The RESET IN and X1 inputs on the HS-80C85RH are schmit
trigger inputs. This eliminates the possibility of internal oscilla­tions in response to slow rise time input signals at these pins.

4. A high frequency bypass capacitor of approximately 0.1 µF
should be connected between VDD and GND to shunt power
supply transients.

5. The HS-80C85RH is functional within 10 input clock cycles after
application of power (assuming that reset has been asserted
from power-on). Start up conditions in the crystal controlled
oscillator mode must also account for the characteristics of the
oscillator.

System Interface

The HS-80C85RH family includes memory components,
which are directly compatible to the HS-8OC8SRH CPU. For
example, a system consisting of the three radiation­hardened chips, HS-80C85RH, HS-81C56RH, and
HS-83C55RH will have the following features:

1. 2K Bytes ROM

2. 256 Bytes RAM

3. 1 Timer/Counter

4. 4 8-bit I/O Ports

5. 1 6-bit I/O Port

6. 4 Interrupt Levels

7. Serial In/Serial Out Ports

This minimum system, using the standard I/O technique is
as shown in Figure 12.

In addition to standard 1/0, the memory mapped I/O offers
an efficient I/O addressing technique. With this technique, an
area of memory address space is assigned for I/O address,
thereby, using the memory address for I/O manipulation.
Figure 13 shows the system configuration of Memory
Mapped I/O using HS-80C85RH.

The HS-80C85RH CPU can also interface with the standard
radiation-hardened memory that does not have the
multiplexed address/data bus. It will require use of the
HS-82C12RH (8-bit latch) as shown in Figure 14.

OUTPUT

OUTPUT

DRIVER

REGENERATIVE

LATCH

PIN

FIGURE 10. OUTPUT DRIVER AND LATCH FOR PINS ADO-AD7,

A8-A15 AND IO/M.

Generating An HS-80C85RH Wait State

If your system requirements are such that slow memories or
peripheral devices are being used, the circuit shown in
Figure 11 may be used to insert one WAIT state in each
HS-80C85RH machine cycle.

The D flip-flops should be chosen so that:

1. CLK is rising edge-triggered

2. CLEAR is low-level active.

The READY line is used to extend the read and write pulse
lengths so that the 80C85RH can be used with slow mem­ory. HOLD causes the CPU to relinquish the bus when it is
through with it by floating the Address and Data Buses.

Q

TO
80C85RH
READY
INPUT

†

ALE

VDD

†ALE and CLK (OUT) should be buffered if CLK

input of latch exceeds 80C85RH IOL or IOH.

CLEAR

CLK

D

“D”
F/F

80C85RH
CLK
OUTPUT

Q

CLK

D

“D”
F/F

FIGURE 11. GENERATION OF A WAIT STATE FOR HS-80C85RH

CPU.

VSS VDD

TRAP
RST 7.5
RST 6.5
RST 5.5
INTR

INTA
ADDR

ADDR/

DATA

(8)(8)

X2X1

HS-80C85RH

ALE

RD WR IO/M RDY CLK

RESET IN

RESET

OUT

HOLD
HLDA

SOD

SID

S1
S0

VSS VDD

CE
WR
RD

ALE
DATA/

ADDR

M

IO/
RESET

IOW
RD

ALE
CE

A0-10

DATA/
ADDR

IO/M
RESET

RDY

†

CLK

VSS VDD

PORT

A

PORT

B

HS-81C56RHHS-83C55RH

PORT

C

IN

TIMER

OUT

PORT

A

PORT

B

IOR

(8)

(8)

(6)

(8)

(8)

VDD

VDD

† Optional Connection

FIGURE 12. HS-80C85RH MINIMUM SYSTEM (STANDARD I/O

TECHNIQUE)

14

Spec Number 518054

HS-80C85RH

RESET OUT

READY

A8-15

AD0-7

ALE

RD

WR

IO/
CLK

HS-80C85RH

M

VDD

TIMER OUT

HS-82C12RH

IN

RESET

HS-81C56RH

† TIMER

(RAM + I/O + COUNTER/TIMER)

AD0-7

CE

RD

WR

ALE

M
IO/

A8-10

CE

AD0-7

HS-83C55RH

(ROM +I/O)

(8) (8)(8) (8)(6)

M
IO/

ALE

RD

IOW

CLK

FIGURE 13. HS-80C85RH MINIMUM SYSTEM (MEMORY MAPPED I/O)

VSS VDD

TRAP
RST 7.5
RST 6.5
RST 5.5
INTR

INTA

ADDR

X2X1

HS-80C85RH

ADDR/

ALE RD WR IO/M RDY CLK

DATA

(8)(8)

RESET IN

RESET

OUT

HOLD

HLDA

SOD

SID

S1
S0

IO/M (CS)
WR
RD

STANDARD

MEMORY

DATA

RST

† RDY

† Optional Connection

ADDR (CS)

CLK
RESET

IO/

(16)

M (CS)

WR
RD

DATA

STANDARD

I/O

ADDR

FIGURE 14. HS-80C85RH SYSTEM (USING STANDARD MEMORIES)

15

I/O PORTS,

CONTROLS

VDD
VDD
VDD

Spec Number 518054

HS-80C85RH

Basic System Timing

The HS-80C85RH has a multiplexed Data Bus. ALE is used
as a strobe to sample the lower 8-bits of address on the
Data Bus. Figure 15 shows an instruction fetch, memory
read and I/O write cycle (as would occur during processing
of the OUT instruction). Note that during the I/O write and
read cycle that the I/O port address is copied on both the
upper and lower half of the address.

There are seven possible types of machine cycles. Which of
these seven takes place is defined by the status of the three
status lines (lO/
WR, and INTA). (See Table 10.) The status lines can be
used as advanced controls (for device selection, for exam­ple), since they become active at the T1 state, at the outset
of each machine cycle. Control lines
as command lines since they become active when the trans­fer of data is to take place.

TABLE 10. HS-80C85RH MACHINE CYCLE CHART

MACHINE CYCLE

Opcode Fetch (OF) 0 1101 1
Memory Read (MR) 0 1001 1
Memory Write (MW) 0 0110 1
I/O Read (IOR) 1 1001 1
I/O Write (IOW) 1 0110 1
Acknowledge

of INTR
Bus Idle (BI) DAD

M, S1, S0) and the three control signals (RD,

RD and WR are used

STATUS CONTROL

IO/MS1S0RD WR INTA

(INA) 1 1111 0

0 1011 1

Ack. of
RST,

TRAP
HALT TS 0 0 TS TS 1

1 1111 1

A machine cycle normally consists of three T states, with the
exception of OPCODE FETCH, which normally has either
four or six T states (unless WAIT or HOLD states are forced
by the receipt of

READY or HOLD inputs). Any T state must

be one of ten possible states, shown in Table 11.

TABLE 11. HS-80C85RH MACHINE STATE CHART

MA­CHINE
STATE

T1 XXX X 1 11†
T2 XXX X X X0
TWAIT X X X X X X 0
T3 XXX X X X0
T4 1 0†† XTS 1 10
T5 1 0†† XTS 1 10
T6 1 0†† XTS 1 10
TRESET X TS TS TS TS 1 0
THALT 0 TS TS TS TS 1 0
THOLD X TS TS TS TS 1 0
0 = Logic “0”

1 = Logic “1”

STATUS & BUSES CONTROL

S1, S0 IO/M A8-15 AD0-7 RD,WR INTA ALE

TS = High Impedance
X = Unspecified

† ALE not generated during 2nd and 3rd machine cycles of DAD

instruction.

†† IO/M = 1 during T4, T6 of INA machine cycle.

CLK

A8-A15

AD0-7

ALE

RD

WR

IO/

STATUS

M1

T1 T2 T3 T4 T1 T2 T3 T1 T2 T3 T

PCH (HIGH ORDER ADDRESS) (PC + 1)H IO PORT

(PC+1)LPCL

(LOW ORDER

ADDRESS)

M

DATA FROM

MEMORY

(INSTRUCTION)

S1-S0 (FETCH) 10 (READ) 01 WRITE 11

FIGURE 15. 80C85RH BASIC SYSTEM TIMING

DATA TO

MEMORY OR

PERIPHERAL

M3M2

IO PORT

DATA FROM

MEMORY (I/O

PORT ADDRESS)

Spec Number 518054

16

Metallization Topology

DIE DIMENSIONS:

229 mils x 240 mils x 14 mils ±1 mil

METALLIZATION:

Type: SiAl
Thickness: 11k

Å ±2kÅ

GLASSIVATION:

Type: SiO

2

Thickness: 8kÅ ±1kÅ

Metallization Mask Layout

(5) SID

(4) SOD

(3) RESET OUT

(2) X2

HS-80C85RH

HS-80C85RH

(1) X1

(40) VDD

(39) HOLD

(38) HLDA

RESET IN

(37) CLOCK OUT

(36)

TRAP (6)

RST 7.5 (7)

RST 6.5 (8)

RST 5.5 (9)

INTR (10)

INTA (11)

AD0 (12)

AD1 (13)
AD2 (14)

(35) READY

M

(34) IO/

(33) S1

RD

(32)

(31) WR
(30) ALE

(29) S0
(28) A15

(27) A14
(26) A13

(25) A12

AD3 (15)
AD4 (16)

AD5 (17)

AD6 (18)

17

AD7 (19)

GND (20)

A8 (21)

A9 (22)

A10 (23)

A11 (24)

Spec Number 518054

Packaging

HS-80C85RH

1

E

e

b

E1

L

Q

M

c1

SECTION A-A

E2

LEAD FINISH

BASE

METAL

b1

M

(b)

A

(c)

N

A
A

S1

C

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat­ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.

2. If a pin one identification mark is used in addition to a tab, the lim­its of dimension k do not apply.

3. This dimension allows for off-center lid, meniscus, and glass
overrun.

4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum lim­its of lead dimensions b and c or M shall be measured at the cen­troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.

5. N is the maximum number of terminal positions.

6. Measure dimension S1 at all four corners.

7. For bottom-brazed lead packages, no organic or polymeric mate­rials shall be molded to the bottom of the package to cover the
leads.

8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol­der dip lead finish is applied.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

11. The basic lead spacing is 0.050 inch (1.27mm) between center
lines. Each lead centerline shall be located within ±0.005 inch
(0.13mm) of its exact longitudinal position relative to lead 1 and
the highest numbered (N) lead.

K42.A TOP BRAZED

42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

INCHES MILLIMETERS

SYMBOL

D

A - 0.100 - 2.54 ­b 0.017 0.025 0.43 0.64 -

b1 0.017 0.023 0.43 0.58 -

c 0.007 0.013 0.18 0.33 -

c1 0.007 0.010 0.18 0.25 -

D 1.045 1.075 26.54 27.31 3

E 0.630 0.650 16.00 16.51 ­E1 - 0.680 - 17.27 3
E2 0.530 0.550 13.46 13.97 -

e 0.050 BSC 1.27 BSC 11

k-----

L 0.320 0.350 8.13 8.89 -

Q 0.045 0.065 1.14 1.65 8
S1 0.000 - 0.00 - 6

M - 0.0015 - 0.04 ­N42 42-

NOTESMIN MAX MIN MAX

Rev. 0 6/17/94

18

Spec Number 518054

HS-80C85RH

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]

Spec Number

19