Intersil Corporation HS-565ARH-T Datasheet

HS-565ARH-T

Data Sheet July 1999 File Number

Radiation Hardened High Speed, Monolithic Digital-to-Analog Converter

Intersil’sSatellite Applications FlowTM(SAF) devices are fully tested and guaranteed to 100kRAD total dose. This QML Class T device is processed to a standard ﬂow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability.

The HS-565ARH-T is a fast, radiation hardened 12-bit current output, digital-to-analog converter. The monolithic chip includes a precision voltage reference, thin-ﬁlm R-2R ladder, reference control ampliﬁer and twelve high-speed bipolar current switches.

The Intersil Semiconductor Dielectric Isolation process provides latch-up free operation while minimizing stray capacitance and leakage currents, to produce an excellent combination of speed and accuracy. Also, ground currents are minimized to produce a low and constant current through the ground terminal, which reduces error due to codedependent ground currents.

4607.1

Features

• qml Class T, Per MIL-PRF-38535

• Radiation Performance

- Gamma Dose (γ) 1 x 10

RAD(Si)

- No Latch-Up, Dielectrically Isolated Device Islands

• DAC and Reference on a Single Chip

• Pin Compatible with AD-565A and HI-565A

• Very High Speed: Settles to 0.50 LSB in 500ns Max

• Monotonicity Guaranteed Over Temperature

• 0.50 LSB Max Nonlinearity Guaranteed Over Temperature

• Low Gain Drift (Max., DAC Plus Reference) 50ppm/

• ±0.75 LSB Accuracy Guaranteed Over Temperature (±0.125 LSB Typical at 25

Pinouts

HS1-565ARH-T (SBDIP), CDIP2-T24

TOP VIEW

HS-565ARH-T die are laser trimmed for a maximum integral nonlinearity error of ±0.25 LSB at 25

C. In addition, the low noise buried zener reference is trimmed both for absolute value and minimum temperature coefficient.

Speciﬁcations

Speciﬁcations for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed below must be used when ordering.

Detailed Electrical Speciﬁcations for the HS-565ARH-T are contained in SMD 5962-96755. A “hot-link” is provided from our website for downloading. www.intersil.com/spacedefense/ne wsafc lasst.asp

Intersil‘s Quality Management Plan (QM Plan), listing all Class T screening operations, is also available on our website.

www.intersil.com/quality/manuals.asp

Ordering Information

TEMP.

ORDERING

NUMBER

5962R9675501TJC HS1-565ARH-T -55 to 125 5962R9675501TXC HS9-565ARH-T -55 to 125

NOTE:

Minimumorderquantity for -T is 150 units through

distribution, or 450 units direct.

PART

NUMBER

RANGE

(oC)

BIPOLAR RIN

NC NC

REF OUT REF GND

REF IN

-V

BIPOLAR RIN

IDAC OUT 10V SPAN 20V SPAN

PWR GND

NC NC

REF OUT

REF GND

REF IN

-V

IDAC OUT 10V SPAN 20V SPAN PWR GND

1 2 3 4 5 6 7 8

9 10 11 12

BIT 1 IN (MSB)

BIT 2 IN

23 22

BIT 3 IN BIT 4 IN

BIT 5 IN

BIT 6 IN

BIT 7 IN

BIT 8 IN

BIT 9 IN

16 15

BIT 10 IN BIT 11 IN

14 13

BIT 12 IN (LSB)

HS9-565ARH-T (FLATPACK), CDFP4-F24

TOP VIEW

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

BIT 1 IN (MSB)

BIT 2 IN BIT 3 IN BIT 4 IN BIT 5 IN BIT 6 IN BIT 7 IN BIT 8 IN BIT 9 IN BIT 10 IN BIT 11 IN BIT 12 IN

(LSB)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

www.intersil.com or 407-727-9207

Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.

Functional Diagram

HS-565ARH-T

REF

GND

REF OUT V

19.95K

10V

3.5K

REF

0.5mA

-V

Deﬁnitions of Speciﬁcations

Digital Inputs

The HS-565ARH-T accepts digital input codes in binary format and may be user connected for any one of three binary codes. Straight binary, Two’s Complement (see note below), or Offset Binary, (see Operating Instructions).

DIGITAL

INPUT

STRAIGHT

BINARY

000 . . . 000 Zero - fS (Full Scale) Zero 100 . . . 000 0.50 f 111 . . . 111 + fS - 1 LSB + fS - 1 LSB Zero - 1 LSB 011 . . . 111 0.50 fS- 1 LSB Zero - 1 LSB + fS - 1 LSB

NOTE: Invert MSB with external inverter to obtain Two’s

Complement Coding.

Accuracy

Nonlinearity - Nonlinearity of a D/A converter is an

important measure of its accuracy. It describes the deviation from an ideal straight line transfer curve drawn between zero (all bits OFF) and full scale (all bits ON).

Differential Nonlinearity - For a D/A converter, it is the differencebetween the actual output voltagechange and the ideal (1 LSB) voltage change for a one bit change in code. A Differential Nonlinearity of ±1 LSB or less guarantees monotonicity; i.e., the output always increases and never decreases for an increasing input.

Settling Time

Settling time is the time required for the output to settle to within the speciﬁed error band for any input code transition. It is usually speciﬁed for a full scale or major carry transition, settling to within 0.50 LSB of ﬁnal value.

Drift

Gain Drift - The change in full scale analog output over the

speciﬁed temperature range expressed in parts per million of

ANALOG OUTPUT

OFFSET BINARY

(NOTE)

TWO’S

COMPLEMENTMSB . LSB

Zero - f

712

PWR

GND

BIP.

9.95K

DAC

(4X IREF

X CODE)

24. . . 13

MSB LSB

OFF.

2.5K

20V SPAN

10V SPAN

OUT

full scale range peroC (ppm of FSR/oC). Gain error is measured with respect to 25 temperatures. Gain drift is calculated for both high (t

C) and low ranges (25oC - tL) by dividing the gain error

C at high (tH) and low (tL)

bythe respectivechange in temperature. The speciﬁcation is the larger of the two representing worst case drift.

Offset Drift - The change in analog output with all bits OFF over the speciﬁed temperature range expressed in parts per million of full scale range per error is measured with respect to 25 (t

) temperatures.Offset drift is calculated for both high (tD-

C) and low (25oC-tL) ranges by dividing the offset error

C (ppm of FSR/oC). Offset

C at high (tH) and low

by the respective change in temperature. The speciﬁcation given is the larger of the two, representing worst case drift.

Power Supply Sensitivity

Power Supply Sensitivity is a measure of the change in gain and offset of the D/A converter resulting from a change in -15V or +15V supplies. It is specified under DC conditions and expressed as parts per million of full scale range per percent of change in power supply (ppm of FSR/%).

Compliance

Compliance Voltage is the maximum output voltage range that can be tolerated and still maintain its speciﬁed accuracy. Compliance Limit implies functional operation only and makes no claims to accuracy.

Glitch

A glitch on the output of a D/A converter is a transient spike resulting from unequal internal ON-OFF switching times. Worst case glitches usually occur at half scale or the major carry code transition from 011 . . . 1 to 100 . . . 0 or vice versa. For example, if turn ON is greater than turn OFF for 011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0 exists, such that, the output momentarily glitches toward zero output. Matched switching times and fast switching will reduce glitches considerably.

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