intersil HS-3282 DATA SHEET

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REFERENCE AN400

March 1997

HS-3282

CMOS ARINC Bus Interface Circuit

Features

• ARlNC Specification 429 Compatible

• Data Rates of 100 Kilobits or 12.5 Kilobits

• Separate Receiver and Transmitter Section

• Dual and Independent Receivers, Connecting Directly to ARINC Bus

• Serial to Parallel Receiver Data Conversion

• Parallel to Serial Transmitter Data Conversion

• Word Lengths of 25 or 32 Bits

• Parity Status of Received Data

• Generate Parity of Transmitter Data

• Automatic Word Gap Timer

• Single 5V Supply

• Low Power Dissipation

• Full Military Temperat ure Range

Ordering Information

PKG.

PACKAGE TEMP. RANGE PART NUMBER

CERDIP -55

SMD# 5962-8688001QA F40.6

CLCC -40

SMD# 5962-8688001XA J44.A

C to +125oC HS1-3282-8 F40.6

C to +85oC HS4-3282-9+ J44.A

C to +125oC HS4-3282-8 J44.A

-55

NO.

Description

The HS-3282 is a high performance CMOS bus interface circuit that is intended to meet the requirements of ARINC Specification 429, and similar encoded, time multiplexed serial data protocols. This device is intended to be used with the HS-3182, a monolithic Dl bipolar differential line driver designed to meet the specifications of ARINC 429. The ARINC 429 bus interface circuit cons ists of two (2) receivers and a transmitter operating independently as shown in Figure 1. The two receivers operate at a frequency that is ten (10) times the receiver data rate, which can be the same or different from the transmitter data rate. Although the two receivers operate at the same frequency, they are functionally independent and each receive s serial data asynchronously. The transmitter section of the ARINC bus interfa ce circ uit consis ts m ainly of a First -In Fi rst- Ou t (FIFO ) memory and tim ing circuit. The FIFO memory is used to hold up to eight (8) ARINC data words for transmission serially. The timing circuit is used to correctly separate each ARINC word as required by ARINC Specification 429. Even though ARINC Specification 429 specifies a 32-bit word, including parity, the HS-3282 can be programm ed to also operate with a word length of 25 bits. The incoming receiver data word parity is checked, and a parity status is stor ed in the receiver latch and output on Pin BD08 during the 1st word. [A logic “0” indicates that an odd number of logic “1” s were received and stored; a l ogic “1” indicat es that an even number of l ogic “1”s were received and stored]. In the transmitter the parity generator will generate either odd or even parity depending upon the status of PARCK control signal. A logic “0” on BD12 will cause odd parity to be used in the output data stream.

Versatility is provided in both the transmitter and receiver by the external clock input which allows the bus interface circuit to operate at data rates from 0 to 100 kilobits. The external clock must be ten (10) times the data rate to insure no data ambiguity.

The ARINC bus interface circuit is fully guaranteed to support the data rates of ARINC specification 429 over both the voltage (±5%) and full military temperature range. It interfaces with UL, CMOS or NMOS support circuitry, and uses the standard 5-volt V

| Intersil (and design) is a trademark of Intersil Americas Inc.

183

supply.

FN2964.2

Pinouts

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429DI1(A) 429DI1(B) 429DI2(A) 429DI2(B)

D/R1 D/R2

SEL EN1

EN2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06

HS-3282

HS-3282 (CERDIP)

TOP VIEW

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

NC MR TX CLK CLK NC NC CWSTR ENTX 429D0 429D0 TX/R PL2 PL1 BD00 BD01 BD02 BD03 BD04 BD05 GND

NC D/R1 D/R2

SEL EN1

EN2

BD15 BD14

BD13 BD12 BD11

HS-3282 (CLCC)

TOP VIEW

429DI1(A)

429DI1(B)

429DI2(A)

429DI2(B)

7 8

9 10 11 12 13 14 15 16 17

BD10

46 3

BD09

BD08

BD07

TXCLK

CLK

GND

BD06

BD05

40414243

CWSTR ENTX

429D0

TX/R

PL2

PL1

BD00

BD01

2827262524232221201918

BD04

BD03

BD02

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HS-3282

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Pin Description

PIN SYMBOL SECTION DESCRIPTION

2 429 DI1 (A) Receiver ARlNC 429 data input to Receiver 1.

3 429 DI1 (B) Receiver ARlNC 429 data input to Receiver 1.

4 429 Dl2 (A) Re ce iv er ARINC 42 9 data inpu t to Rece iv er 2.

5 429 DI2 (B) Receiv er ARINC 42 9 da t a in pu t to Receiver 2.

6D/R1

7D/R2

8 SEL Receiver Bus Data Selector - Input signal to select one of two 16-bit words from either Receiver 1 or 2.

9EN1

10 EN2

11 BD15 Recs/Trans Bi-directional data bus for fetching dat a from either of the Receivers, or for loading data in to

12 BD14 Recs/Trans See Pin 11.

13 BD13 Recs/Trans See Pin 11.

14 BD12 Recs/Trans See Pin 11.

Recs/Trans Supply pin 5 volts ±5%.

Receiver Device ready flag output from Receiver 1 indicating a valid data word is ready to be fetched.

Receiver Device ready flag output from Receiver 2 indicating a valid data word is ready to be fetched.

Receiver Input signal to enable data from Receiver 1 onto the data bus.

Receiver Input signal to enable data from Receiver 2 onto the data bus.

the Transmitter memo ry o r con trol word re gister. Se e Contro l W ord T able f or descripti on o f Control Word bits.

15 BD11 Recs/Trans See Pin 11.

16 BD10 Recs/Trans See Pin 11.

17 BD09 Recs/Trans See Pin 11.

18 BD08 Recs/Trans See Pin 11.

19 BD07 Recs/Trans See Pin 11.

20 BD06 Recs/Trans See Pin 11.

21 GND Recs/T rans Circuit Gr ound.

22 BD05 Recs/Trans See Pin 11.

23 BD04 Recs/Tr ans See Pin 11. Control Word function not applicable.

24 BD03 Recs/Tr ans See Pin 11. Control Word function not applicable.

25 BD02 Recs/Tr ans See Pin 11. Control Word function not applicable.

26 BD01 Recs/Tr ans See Pin 11. Control Word function not applicable.

27 BD00 Recs/Tr ans See Pin 11. Control Word function not applicable.

28 PL1

29 PL2

Transmitter Paralle l load input signal loading the first 16-bit word into the T ransmitter memory.

Transmitter Parallel load input signal loading the first 16-bit word into the Transmitter memory and ini-

tiates data transfer into the memory stack.

30 TX/R Transmitter Transmit ter flag output to indicate the memory is empty.

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HS-3282

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Pin Description (Continued)

PIN SYMBOL SECTION DESCRIPTION

31 429D0 Transmitter Data output from Transmitter

32 429D0

33 ENTX Transmitter Transmitter Enable input signal to initiate data transmission from FIFO memory.

34 CWSTR

35 - - No co nn ec tion. Mu st be lef t op en .

36 - - No connection. Must be left open or tied low but never tied high.

37 CLK Recs/Trans External clock input. May be either ten (10) or eighty (80) times the data rate. If using both

38 TXCLK Transmitter Transmitter Clock output. Delivers a clock frequency equal to the transmitter data rate.

39 MR

40 - - No Connection.

Transmitter Data output from Transmitter.

Recs/Trans Control word input strobe signal to latch the control word from the databus into the control

word register.

ARINC data rates it must be ten (10) times the highest data rate, (typically 1MHz).

Recs/Trans Master Reset. Active low pulse used to reset FIFO, bit counters, gap timer, word count signal,

TX/R an d various other flags and contr ols. Master reset does not reset t he control word register. Usually only used on Power-Up or System Reset.

Pinout

13 12345678910111214151617181920

28 40393837363534333231302927262524232221

NCNC NC

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Operational Description

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HS-3282

The HS-3282 is designed to support ARINC Specification 429 and other serial data protocols that use a similar format by collecting the receiving, transmitting, synchronizing, timing and parity fu nctions on a single, low power LSl circui t. It goes beyond the ARlNC requirements by providing for either odd or even parity, and giving the user a choice of either 25 or 32-bit word le ngths. The rece iver and transmit ter sections operate independently of each other. The serial-toparallel conversion required of the receiver and the parallelto-serial conversion requirements of the transmitter have been incorporated into the bus interface circuit.

Provisions have been made through the external clock input to provide dat a rate flexibi li ty. This requires an external clock that is 10 times the data rate.

To obtain the flexibility discussed above, a number of external control signals are required, To reduce the pin count requirements, an internal contr ol word register is used. The control word is latched from the data bus into the register by the Control

Word Strobe (CWSTR) signal going to a logic “1”. Eleven (11) control functions are used, and along with the Bus Data (BD) line are list ed below:

Control Word

PIN NAME SYMBOL FUNCTION

BD05 SLFTST Conne cts the se lf test si gnal from t he transmi tter dire ctly to th e receiver shift reg isters, bypassin g the input

recei vers . Rec eiv er 1 r ece ives Dat a True an d Rec eive r 2 re cei ves Da ta Not . Not e tha t th e tran smit ter out put

remains active. (Logic “0” on SLFTST Enables Self Test). BD06 SDENB1 Signal to Activate the Source/Destination (S/D) Decoder for Receiver 1. (Logic “1” activates S/D Decoder). BD07 X1 If SDENB1 = “1” then this bit is compared with ARlNC Data Bit #9. If Y1 also matches (see Y1), the word will be

BD08 Y1 If SDENBI = “ 1” then th is bit is co mpa red with ARIN C Da ta B it # 10 . If X1 also matc he s (se e X1 ), th e wor d wil l

BD09 SDENB2 Signal to activate the Source/Destination (S/D) Decoder for Receiver 2. (Logic “1” activates S/D Decoder). BD10 X2 If SDENB2 = “1” then this bit is compared with ARlNC Data Bit #9. If Y2 also matches (see Y2), the word will be

BD11 Y2 If SDENB2 = “1” then this bit is compared with ARINC Data Bit #10. If X2 also matches (see X2), the word will

BD12 PARCK Signal us ed to inv ert the t ran smi t ter pa rit y bi t fo r te st of pa ri ty ci r cu its. Lo gic “ 0” se le ct s n orma l o dd par i ty. Log ic

BD13 TXSE L Selects hi gh o r low Tra nsm itter da ta rat e. I f TX SEL = “ 0” the n t ransm it ter da ta rate i s eq ua l to th e cl ock rat e

BD14 RCVSEL Selects high or low Receiver data rate. If RCVSEL = “0” then the received data rate should be equal to the clock

BD15 WLSEL Selects word length. If WLSEL = “0” a 32-bit word format will be selected. If WLSEL = “1” a 25-Bit word format

accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care.

be accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care.

accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care.

be accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care.

“I” selects even parity.

divide d by ten (10). If TXSE L = “1” then transmitter data rate is equal to the clock rate divided by eighty (80).

rate divide d by te n (10), i f RCVSEL = “1 “t hen th e re ceived data ra te shou ld be e qual to the cl ock rate di vide d

by eighty (80).

will be selected.

ARlNC 429 DATA FORMAT as input to the Receiver and output from the Transm itter is as follows:

TABLE 1. ARINC 429 32-BIT DATA FORMAT ARINC BIT # FUNCTION

1 - 8 Label

9 - 10 SDl or Data

11 LSB

12 - 27 Data

28 MSB 29 Sign

30, 31 SSM

32 Parity S tatus

This format is shuffled when seen on the sixteen bidirectional input/outputs. The format shown below is used from the receivers and input to the transmitter :

TABLE 2A. WORD 1 FORMAT

BI-DIRECTIONAL

BIT # FUNCTION ARINC BlT #

15, 14 Data 13, 12

13 LSB 11

12, 11 SDl or Data 10, 9

10, 9 SSM Status 31, 30

8 Parity Status 32

7 - 00 Label 1 - 8

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HS-3282

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TABLE 2B. WORD 2 FORMAT

BI-DIRECTIONAL

BlT# FUNCTION ARINC BIT#

15 Sign 29 14 MSB 28

13 - 00 Data 27 - 14

Receiver Parity Statu s:

0 = Odd Parity 1 = Even Parity If the receiver input data word string is broken before the

entire data word is received, the receiver will reset and ignore the partially received data word.

If the transmitter is used to transmit consecutive data words, each word wil l be separated by a four (4) bit “null” state (both positive and negative outputs will maintain a zero (0) volt level.)

TABLE 3. ARINC 25-BIT DATA FORMAT

ARINC BIT # FUNCTION

1 - 8 Label

9LSB

11 - 23 Data

24 MSB 25 Parity S tatus

• The Line Receiver functions as a voltage level translator. It transforms the 10 volt differential line voltage, ARINC 429 format, into 5 volt int ernal logic level.

• The output of the Line Receiver is one of two inputs to the Self-Test Data Selector (SEL). The other input to the Data Selector is the Self-Test Signal from the Transmitter section.

• The incoming data, either Self-Test or ARlNC 429, is double sampled by the Word Gap Timer to generate a Data Clock. The Receiver sample frequency (RCVCLK), 1MHz, or 125kHz, is generated by the Receiver/Transmitter Timing Circuit. Thi s sampli ng freque ncy is ten t imes the Data Rate to ensure no data ambiguity.

• The derived data clock then shifts the data down a 32-Bit long Data Shift Register (Data S/RI). The Data Word Length is selectable for either 25 Bits or 32 Bits long by the Control Signal (WLSEL). As soon as the data word is completely received, an internal signal (WDCNT1) is generated by the Word Gap Timer Circui t.

• The Source/Destination (S/D) Decoder compares the user set code (X and Y) with Bits 9 and 10 of the Data Word. If the two codes are matched, a positive signal is generated to enable the WDCNT1 signal to latch in the received data. Otherwise, the data word is ignored and no latching action takes place. The S/D Decoder can be Enabled and Disabled by the control signal S/D ENB. If the data word is latched, an indicator flag (D/R1 valid data word is ready t o be fet ched by the user.

) is set. This indicates a

TABLE 4A. WORD 1 FORMAT

BI-DIRECTIONAL

BIT# FUNCTION ARINC BIT#

15 - 9 Don’t Care XXX

8 Parity Status 25

7 - 0 Label 1 - 8

TABLE 4B. WORD 2 FORMAT

BI-DIRECTIONAL

BIT# FUNCTION ARINC BlT#

15 MSB 24

14 - 1 Data 23 -10

0LSB9

Receiver Parity Statu s:

0 = Odd Parity 1 = Even Parity

No Source/Desti nation (S/D) in 25-Bit format.

Receiver Operat ion

Since the two receivers are functionally identical, only one will be discussed in detail, and the block diagram will be used for reference in this discussion. The receiver consists of the following circuits:

• After the receiver data has been shifted down the shift register, it is placed in a holding regist er. The device ready flag will then be set indicating that data is ready to be fetched. If the data is ignored and left in the holding register, it will be written over when the next data word is received.

• The received data in the 32-bit holding register is placed on the bus in the form of two (2)16-bit words regardless of whether the format is for 32 or 25-bit data words. Either word can be accessed first or repeatedly until the next received data word falls into the holding regist er.

• The parity of the incoming word is checked and the status (i.e., logic “0” for odd parity and logic “1” for even parity) stored in the receiver latch and output on BD08 during the Word No. 1.

• Assuming the u ser desires to access the dat a, he first set s the Data Select Line (SEL) to a Logic “0” level and pulses the Enable (EN1 Selector (SELl) to select the first-data word, which contains the label field and Enable it onto the Data Bus. To obtain the second data word, the user sets the SEL line to a Logic “1” level and pulse the Enable (EN1 The Enable pulse duration is matched to the user circuit requirement needed to read the Data Word from the Data Bus. The second Enable pulse is also used to reset the Device Ready (D/R1 cycle.

) line. This action causes the Data

) line again.

) flip-flo p. This c omplete s a receiv ing

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