Intersil Corporation HMP8115 Datasheet

HMP8115

April 1998

Features

• (M) NTSC and (B, D, G, H, I, M, N, NC) PAL Operation

- Optional Auto Detect of Video Standard

- ITU-R BT.601 (CCIR601) and Square Pixel Operation

• Digital Output Formats

- VMI Compatible

- 8-Bit, 16-Bit 4:2:2 YCbCr

- 15-Bit (5,5,5), 16-Bit (5,6,5) RGB

- Linear or Gamma-Corrected

- 8-Bit BT.656

• Analog Input Formats

- Three Analog Composite Inputs

- Analog Y/C (S-Video) Input

• “Sliced” VBI Data Capture Capabilities

- Closed Captioning

- Widescreen Signalling (WSS)

- BT.653 System B, C and D Teletext

- NABTS (North American Broadcast Teletext)

- WST (World System Teletext)

NTSC/PAL Video Decoder

Description

The HMP8115 is a high quality NTSC and PAL decoder with
internal A/D converters. It is compatible with NTSC M, PAL
B, D, G, H,I, M, N, and combination N (N

Both composite and S-video (Y/C) input formats are sup­ported. A 2-line comb filter plus a user-selectable chromi­nance trap filter provide high quality Y/C separation. User
adjustments include brightness, contrast, saturation, hue,
and sharpness.

Data during the vertical blanking interval (VBI), such as
closed captioning, widescreen signalling and teletext, may
be captured and output as BT.656 ancillary data. Closed
captioning and widescreen signalling information may also
be read out via the I

2

C interface.

Ordering Information

TEMP.

PART NUMBER

HMP8115CN 0 to 70 80 Ld PQFP Q80.14x20
HMPVIDEVAL/ISA Evaluation Board: ISA Frame Grabber

RANGE (oC) PACKAGE PKG. NO.

) video standards.

C

• 2-Line (1H) Comb Filter Y/C Separator

• Fast I

• Two 8-Bit ADCs

2

C Interface

Applications

• Multimedia PCs

• Video Conferencing

• Video Compression Systems

• Video Security Systems

• LCD Projectors and Overhead Panels

• Related Products

- NTSC/PAL Encoders: HMP815x, HMP817x

- NTSC/PAL Decoders: HMP8112A

• Related Literature

- AN9644: Composite Video Separation Techniques

- AN9716: Widescreen Signalling

- AN9717: YCbCr to RGB Considerations

- AN9728: BT.656 Video Interface for ICs

- AN9738: VMI Video Interface for ICs

NOTES:

1. PQFP is also known as QFP and MQFP.

2. Evaluation Board and Reference Design descriptions are in the
Applications section.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

1

File Number 4283.5

HMP8115HMP8115

Table of Contents

PAGE

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

External Video Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

ANALOG VIDEO INPUTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

ANTI-ALIASING FILTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

S-VIDEO CHROMA GAIN CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Digitization of Video. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

A/D CONVERSION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

AGC AND DC RESTORATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

INPUT SIGNAL DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

VERTICAL SYNC AND FIELD DETECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Y/C SEPARATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

INPUT SAMPLE RATE CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

CHROMA DEMODULATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

OUTPUT SAMPLE RATE CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

CLK2 INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Digital Processing of Video. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

UV TO CbCr CONVERSION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

DIGITAL COLOR GAIN CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

COLOR KILLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Y PROCESSING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

CbCr PROCESSING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

YCbCr OUTPUT FORMAT PROCESSING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

RGB OUTPUT FORMAT PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

BUILT-IN VIDEO GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pixel Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

HSYNC AND VSYNC TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

FIELD TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

BLANK AND DVALID TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PIXEL OUTPUT PORT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

8-BIT YCbCr OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

16-BIT YCbCr, 15-BIT RGB, OR 16-RGB OUTPUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

8-BIT BT.656 OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Advanced Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

CLOSED CAPTIONING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

WIDESCREEN SIGNALLING (WSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

BT.656 ANCILLARY DATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

BT.656 CLOSED CAPTIONING AND WIDE SCREEN SIGNALLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

TELETEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

REAL TIME CONTROL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

HMP8115 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

PCB LAYOUT CONSIDERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

EVALUATION BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

RELATED APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2

HMP8115

RATE

OUTPUT

SAMPLE

CONVERTER

USER

ADJUST.

RGB

LOGIC

VBIVALID

HSYNC

BLANK

TIMING

OUTPUT

AND

DVALID

FIFO

P[15:0]

VBI STATUS BITS

ADC

8-BIT

VBI

DETECTION AND

DECODING LOGIC

USER

ADJUST

TRAP

COLOR

Y/C

SEPARATION

COLOR

ADJUST

COLOR

DEMODULATION

INPUT

RATE

SAMPLE

CONVERTER

HSYNC

DETECT

PLL

CHROMA

ADC

8-BIT

LINE

LOCK

VSYNC

DETECT

PLL

SCL

SDA

CONTROL

INTERFACE AND

MICROPROCESSOR

LOCKED

VSYNC

FIELD

INTREQ

RESET

Functional Block Diagram

FILTER

EXTERNAL

ANTIALIASING

YIN

YOUT

NTSC-PAL1

-

+

MUX

INPUT

NTSC-PAL2

NTSC-PAL3/Y

BLACK LEVEL

WHITE PEAK LEVEL

DIGITAL COMPARATORS

AND

AGC

CLAMP

L_CAP

SYNC LEVEL

LOGIC

LAGC_CAP

DIGITAL COMPARATOR

AND

LOGIC

CLAMP

GAIN_CTRL

3

CLAMP

GAIN

CONTROL

C_CAP

-

+

C

FILTER

EXTERNAL

ANTIALIASING

Functional Block Diagram

(Continued)

(24.54, 27.0 OR 29.5MHz)

4FSC

CLOCK

CR[7:0]

C

M
U
X

C,CVBS

DAT A

4

INPUT

SAMPLE

RATE

CONVERTER

Y,CVBS

Y DATA

CLK

CHROMA
PLL NCO

CLK TO

4FSC RATIO

C,CVBS

DAT A

LINE
DELAY
COMB
FILTER

Y DATA

Y DATA

CHROMA

PLL LOOP

FILTER

C DATA

DEMODULATOR

M
U
X

CHROMA

Y DATA

HUE

ADJUST

AGC

ADJUST

U,V

HORIZONTAL

AND VERTICAL

SHARPNESS

ADJUST

CHROMA

PHASE

DETECTOR

SATURATION

ADJUST

CHROMA

TRAP

VSYNC

DETECT

U, V TO CbCr

COLOR

SPACE
CONVERTER
AND COLOR

KILLER

FIELD
VSYNC

GENLOCK LOSS

LP FILTER

ENABLE

LINE LOCKED

PLL LOOP FILTER

LINE LOCKED

NCO

CbCr

OUTPUT

SAMPLE

RATE

CONVERTER

Y

HSYNC

DETECT

HSYNC

LOCKED

SYNC

STRIPPER,

BRIGHTNESS,

AND CONTRAST

ADJUST

HMP8115

VBI DETECTION

AND DECODING LOGIC

SHARPNESS

ADJUST

ENABLE

LP FILTER

ENABLE

M
U
X

HSYNC,VSYNC, BLANK,

FIELD,

STANDARD

SELECT

P[15:0]

DVALID, VBIVALID

RGB

LOGIC

MUX MUX

OUTPUT

TIMING

AND

FIFO

HMP8115

Introduction

The HMP8115 is designed to decode baseband composite
or S-video NTSC and PAL signals, and convert them to
either digital YCbCr or RGB data. In addition to performing
the basic decoding operations, the HMP8115 includes hard­ware to decode different types of VBI data and to generate
digital video patterns for a blue screen, black screen and full
screen color bars.

The digital PLLs are designed to synchronize to all NTSC
and PAL standards. A chroma PLL is used to maintain
chroma lock for demodulation of the color information; a line­locked PLL is used to maintain vertical spatial alignment.
The PLLs are designed to maintain lock even in the event of
VCR headswitches and multipath noise.

The HMP8115 contains two 8-bit A/D converters and an I

2

interface for programming internal registers.

External Video Processing

Before a video signal can be digitized the decoder has some
external processing considerations that need to be
addressed. This section discusses those external aspects of
the HMP8115.

ANALOG VIDEO INPUTS

The HMP8115 supports either three composite or two com­posite and one S-video input.

inside the decoder as determined by bits 7 and 6 of the
COLOR PROCESSING register 06

. In addition to the inter-

H

nal AGC, the designer can also apply some gain to the
chroma before it reaches the internal AGC logic. This gain is
controlled by pin 28. The voltage at this pin determines the
gain of the chroma before it gets digitized by the chroma A/D
with a typical gain performance as shown in Figure 2.

7

TEMPERATURE = 25oC
V

= 5V

CC

6

5

4

C

3

LINEAR GAIN

2

1

0

1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
CONTROL VOLTAGE ON THE GAIN_CTRL PIN

FIGURE 2. CHROMINANCE AMPLIFIER GAIN

Digitization of Video

Three analog video inputs (NTSC/PAL 1-3) are used to
select which one of three composite video sources are to be
decoded. To support S-video applications, the Y channel
drives the NTSC/PAL 3 analog input, and the C channel
drives the C analog input.

The analog inputs must be AC-coupled to the video signals,
as shown in the Applications section.

ANTI-ALIASING FILTERS

An external anti-alias filter is required to achieve optimum
performance and prevent high frequency components from
being aliased back into the video image.

For the NTSC/PAL 1-3 inputs, a single filter is connected
between the YOUT and YIN pins. For the C input, the anti­aliasing filter should be connected before the C input. A rec­ommended filter is shown in Figure 1.

R

YOUT YIN

FIGURE 1. RECOMMENDED ANTI-ALIASING FILTER

332

1

C

33pF

L

1

8.2µH

C

1

82pF

2

R

2

4.02K

S-VIDEO CHROMA GAIN CONTROL

The Chroma portion of S-video is AC coupled through an
anti-aliasing filter as shown in the applications section.
Unlike the composite/luma inputs, the Automatic Gain Con­trol (AGC) for the chroma portion of S-video is done digitally

Prior to A/D conversion, the video signal is DC restored and
gained to generate known video levels into the digital pro­cessing logic. This process is addressed in the “AGC and
DC Restoration” section. After digitization, sample rate con­verters and a comb filter are used to perform color separa­tion and demodulation.

A/D CONVERSION

Video data is sampled at the CLK2 frequency then pro­cessed by the input sample rate converter. The output levels
of the ADC after AGC processing are:

(M) NTSC (B, D, G, H, I, N

)

C

(M, N) PAL PAL

white 224 213
black 76 64
blank 64 64
sync 0 0

AGC AND DC RESTORATION

The AGC amplifier attenuates or amplifies the analog video
signal to ensure that the sync tip level generates code 0. The
difference from the ideal sync tip level of 0 is used to control
the amount of attenuation or gain of the analog video signal.
The capacitor on the LAGC_CAP pin is used to store the
voltage which sets the gain level of the input video amplifier.

DC restoration positions the video signal such that the DC
level of the back porch generates an average code 64. The
back porch is sampled to determine the average value. The
capacitor on the L_CAP pin is used to store the voltage

5

HMP8115

which sets the DC offset level into the input video amplifier.
During the S-video mode of operation the capacitor on the
C_CAP pin performs the same function as the L_CAP
capacitor, except the chroma video amplifier’s DC offset is
set so that the chroma A/D generates a code of 128 during
the back porch. The internal timing windows for AGC and DC
Restoration are show in Figure 3.

VIDEO INPUT

DC RESTORE

AGC

FIGURE 3. AGC AND DC RESTORE INTERNAL TIMING

INPUT SIGNAL DETECTION

It is assumed there is no video input if a horizontal sync is
not detected for 16 consecutive lines. When no video has
been detected, nominal video timing is generated for the
previously detected or programmed standard. A maskable
interrupt is included to flag when no video has been detected
(bit 6 of the INTERRUPT MASK register 0F

) allowing for

H

blue/black/color bar output modes to be enabled if desired.
The vertical sync interrupt can be used in determining when
a video signal is present at the currently selected video mux
input. Bit 0 of register 0F

is used to enable vertical sync

H

interrupts.

VERTICAL SYNC AND FIELD DETECTION

The vertical sync and field detect circuit uses a low time
counter to detect the vertical sync sequence in the video
data stream. The low time counter accumulates the low time
encountered during any sync pulse, including serration and
equalization pulses. When the low time count exceeds the
vertical sync detect threshold,
ately. FIELD is asserted at the same time that
asserted. FIELD is asserted low for odd fields and high for
evenfields. Field is determined from the location in the video
line where VSYNC is detected. If VSYNC is detected in the
first half of the line, the field is odd. If VSYNC is detected in
the second half of a line, the field is even.

In the case of lost vertical sync or excessive noise that would
prevent the detection of vertical sync, the FIELD output will
continue to toggle. Lost vertical sync is declared if after 337
lines, a vertical sync period was not detected for 1 or 3
(selectable) successive fields as specified by bit 2 of the
GENLOCK CONTROL register 04
PLLs are initialized to the acquisition state.

VSYNC is asserted immedi-

VSYNC is

. When this occurs, the

H

Y/C SEPARATION

A composite video signal has the luma (Y) and chroma (C)
information mixed in the same video signal. The Y/C separa­tion process is responsible for separating the composite
video signal into these two components. The HMP8115 uti­lizes a comb filter to minimize the artifacts that are associ­ated with the Y/C separation process.

INPUT SAMPLE RATE CONVERTER

The input sample rate converter is used to convert video
data sampled at the CLK2 rate to a virtual 4xf

sample rate

SC

for comb filtering and color demodulation. An interpolating
filter is used to generate the 4xf

samples as illustrated in

SC

Figure 4.

INCOMING VIDEO SAMPLES

TIME

RESAMPLED VIDEO

TIME

4xf

SC

FIGURE 4. SAMPLE RATE CONVERSION

COMB FILTER

A 2-line comb filter, using a single line delay, is used to per­form part of the Y/C separation process. During S-video
operation, the Y signal bypasses the comb filter; the C signal
is processed by the comb filter since it is an integral part of
the chroma demodulator. During PAL operation, the chroma
trap filter should also be enabled for improved performance.

Since a single line store is used, the chroma will normally
have a half-line vertical offset from the luma data. This may
be eliminated, vertically aligning the chroma and luma sam­ples, at the expense of vertical resolution of the luma. Bit 0 of
the OUTPUT FORMAT register 02

controls this option.

H

CHROMA DEMODULATION

The output of the comb filter is further processed using a
patented frequency domain transform to complete the Y/C
separation and demodulate the chromanance.

Demodulation is done at a virtual 4xf

sample rate using

SC

the interpolated data samples to generate U and V data. The
demodulation process decimates by 2 the U/V sample rate.

OUTPUT SAMPLE RATE CONVERTER

The output sample rate converter converts the Y, U and V
data from a virtual 4xf
sample rate (i.e., 13.5MHz). It also vertically aligns the sam­ples based on the horizontal sync information embedded in
the digital video data stream. The output sample rate is
determined by the selected video standard and whether

sample rate to the desired output

SC

6

HMP8115

square or rectangular pixels are output. The output format is
4:2:2 for all modes except the RGB modes which use a 4:4:4
output format.

CLK2 INPUT

Note that the color subcarrier is derived from CLK2. Any jitter
on CLK2 will be transferred to the color subcarrier, resulting
in color changes. Thus, CLK2 should be derived from a sta­ble clock source, such as a crystal. The use of a PLL to gen­erate CLK2 is not recommended. CLK2 must have a 50ppm
accuracy and at least a 60/40% duty cycle to ensure proper
operation.

The CLK2 clockrate must be one of the followingfrequencies:

24.54MHz

27.00MHz

29.50MHz

The frequency of CLK2 must be 2x the desired output sam­ple rate. The values in Table 1 below indicate the CLK2 clock
rate based on the video standard and pixel mode. The out­put sample rate for the given video standard and pixel mode
is half the CLK2 clock rate.

TABLE 1. VIDEO STANDARD CLOCK RATE SELECTION

SUMMARY

ALLOWABLE CLK2

FREQUENCIES (MHz)

RECTANGULAR

VIDEO FORMAT

(M) NTSC 27.00 24.54
(B, D, G, H, I, N) PAL 27.00 29.50
(M) PAL 27.00 24.54
(NC) PAL 27.00 29.50

PIXEL MODE

SQUARE

PIXEL MODE

with the two previous lines having a color burst to limit line­to-line variations. A gain of 0.5x to 4x is used for Cb and Cr.

If “fixed gain control” is selected, the amplitude of the color
difference signals (CbCr) is multiplied by a constant, regard­less of variations in the color burst amplitude. The constant
gain value is specified by the COLOR GAIN register 1C

.A

H

gain of 0.5x to 4x is used for Cb and Cr. Limiting the gain to
4x limits the amount of amplified noise.

If “freeze automatic gain control” is selected, the amplitude
of the color difference signals (CbCr) is multiplied by a con­stant. This constant is the value the AGC circuitry generated
when the “freeze automatic gain” command was selected.

COLOR KILLER

If “enable color killer” is selected, the color output is turned
off when the running average of the color burst amplitude is
below approximately 25% of nominal for four consecutive
fields. When the running average of the color burst ampli­tude is above approximately 25% of nominal for four consec­utive fields, the color output is turned on. The color output is
also turned off when excessive phase error of the chroma
PLL is present.

If “force color off” is selected, color information is never
present on the outputs.

If “force color on” is selected, color information is present on
the outputs regardless of the color burst amplitude or
chroma PLL phase error.

Y PROCESSING

The black level is subtracted from the luminance data to
remove sync and any blanking pedestal information. Nega­tive values of Y are supported at this point to allow proper
decoding of “below black” luminance levels.

Digital Processing of Video

Once the luma and chroma have been separated the
HMP8115 then performs programmable modifications (i.e.
contrast, coring, color space conversions, color AGC,etc.) to
the decoded video signal.

UV TO CbCr CONVERSION

The baseband U and V signals are scaled and offset to gen­erate a nominal range of 16-240 for both the Cb and Cr data.

DIGITAL COLOR GAIN CONTROL

There are four types of color gain control modes available:
no gain control, automatic gain control, fixed gain control,
and freeze automatic gain control.

If “no gain control” is selected, the amplitude of the color dif­ference signals (CbCr) is not modified, regardless of varia­tions in the color burst amplitude. Thus, a gain of 1x is
always used for Cb and Cr.

If “automatic gain control” is selected, the amplitude of the
color difference signals (CbCr) is compensated for variations
in the color burst amplitude. The burst amplitude is averaged

Scaling is done to position black at 8-bit code 0 and white at
8-bit code 219.

A chroma trap filter may be used to remove any residual
color subcarrier from the luminance data. The center fre­quency of the chroma trap is automatically determined from
the video standard being decoded. The chroma trap should
be disabled during S-video operation to maintain maximum
luminance bandwidth. Alternately, a 3MHz lowpass filter may
be used to remove high-frequency Y data. This may make a
noisy image more pleasing to the user, although softer.

Coring of the high-frequency Y data may be done to reduce
low-level high frequency noise.

Coring of the Y data may also be done to reduce low-level
noise around black. This forces Y data with the following val­ues to a value of 0:

coring = 1: ± 1
coring = 2: ± 1, ± 2
coring = 3: ± 1, ± 2. ± 3

High-frequency components of the luminance signal may be
“peaked” to control the sharpness of the image. Maximum
gain may be selected to occur at either 2.6MHz or the color

7

HMP8115

subcarrier frequency. This may be used to make the dis­played image more pleasing to the user. It should not be
used if the output video will be compressed, as the circuit
introduces high-frequency components that will reduce the
compression ratio.

The brightness control adds or subtracts a user-specified
DC offset to the Y data. The contrast control multiplies the Y
data by a user-specified amount. These may be used to
make the displayed image more pleasing to the user.

Finally, a valueof 16 is added to generate a nominal range of
16 (black) to 235 (white).

CbCr PROCESSING

The CbCr data is lowpass filtered to either 0.85 or 1.5MHz.
Coring of the CbCr data may be done to reduce low-level

noise around zero. This forces CbCr data with the following
values to a value of 128.

coring = 1: 127, 129
coring = 2: 126, 127, 129, 130
coring = 3: 125, 126, 127, 129, 130, 131

The saturation control multiplies the CbCr data by a user­specified amount. This may be used to make the displayed
image more pleasing to the user. The CbCr data may also
be optionally multiplied by the contrast value to avoid color
shifts when changing contrast.

The hue control provides a user-specified phase offset to the
color subcarrier during decoding. This may be used to cor­rect slight hue errors due to transmission.

YCbCr OUTPUT FORMAT PROCESSING

Y has a nominal range of 16 to 235. Cb and Cr have a nomi­nal range of 16 to 240, with 128 corresponding to zero. Val­ues less than 1 are made 1 and values greater than 254 are
made 254.

While

BLANK is asserted, Y is forced to have a value of 16,
with Cb and Cr forced to have a value of 128, unless VBI
data is present.

RGB OUTPUT FORMAT PROCESSING

The 4:2:2 YCbCr data is converted to 4:4:4 YCbCr data and
then converted to either 15-bit or 16-bit gamma-corrected
RGB (R′G′B′) data. While
forced to a value of 0.

BLANK is asserted, RGB data is

The 15-bit R′G′B′ data may be converted to 15-bit linear
RGB, using the following equations. Although the PAL speci­fications specify a gamma of 2.8, a gamma of 2.2 is normally
used. The HMP8115 allows the selection of the gamma to
be either 2.2 or 2.8, independent of the video standard.

for gamma = 2.2:

for R′G′B′ < 0.0812*31

R = (31)((R′/31)/4.5)
G = (31)((G′/31)/4.5)
B = (31)((B′/31)/4.5)

for R′G′B′ >= 0.0812*31

R = (31)(((R′/31) + 0.099)/1.099)
G = (31)(((G′/31) + 0.099)/1.099)
B = (31)(((B′/31) + 0.099)/1.099)

2.2

2.2

2.2

for gamma = 2.8:

R = (31)(R′/31)
G = (31)(G′/31)
B = (31)(B′/31)

2.8

2.8

2.8

16-Bit R′G′B′

The following YCbCr to R′G′B′ equations are used to main­tain the proper black and white levels:

R′ = 0.142(Y - 16) + 0.194(Cr - 128)
G′ = 0.288(Y - 16) - 0.201(Cr - 128) - 0.097(Cb - 128)
B′ = 0.142(Y - 16) + 0.245(Cb - 128)

The resulting 16-bit R′G′B′ data has a range of 0 to 31 for R′
and B′, and a range of 0 to 63 for G′. Values less than 0 are
made 0; R′ and B′ values greater than 31 are made 31, G′
values greater than 63 are made 63.

The 16-bit R′G′B′ data may be converted to 16-bit linear
RGB, using the following equations. Although the PAL speci­fications specify a gamma of 2.8, a gamma of 2.2 is normally
used. The HMP8115 allows the selection of the gamma to
be either 2.2 or 2.8, independent of the video standard.

for gamma = 2.2:

for R′B′ < 0.0812*31, G′ < 0.0812*63

R = (31)((R′/31)/4.5)
G = (63)((G′/63)/4.5)
B = (31)((B′/31)/4.5)

15-Bit R′G′B′

The following YCbCr to R′G′B′ equations are used to main­tain the proper black and white levels:

R′ = 0.142(Y - 16) + 0.194(Cr - 128)
G′ = 0.142(Y - 16) - 0.099(Cr - 128) - 0.048(Cb - 128)
B′ = 0.142(Y - 16) + 0.245(Cb - 128)

The resulting 15-bit R′G′B′ data has a range of 0 to 31. Val­ues less than 0 are made 0 and values greater than 31 are
made 31.

for R′B′ >= 0.0812*31, G′ >= 0.0812*63

R = (31)(((R′/31) + 0.099)/1.099)
G = (63)(((G′/63) + 0.099)/1.099)
B = (31)(((B′/31) + 0.099)/1.099)

2.2

2.2

2.2

for gamma = 2.8:

R = (31)(R′/31)
G = (63)(G′/63)
B = (31)(B′/31)

2.8

2.8

2.8

8

HMP8115

BUILT-IN VIDEO GENERATION

When the blue screen, black screen or color bar output is
selected, a full-screen of blue, black or 75% colorbar output
is generated using the currently selected output format. The
type of screen to be generated is determined by bits 2 and 1
of the OUTPUT FORMAT register 02

. When built-in video

H

generation is not desired, the bits need to be set for normal
operation to pass decoded video.

If a video source is input, it will be used to provide the video
timing. If an input video source is not detected, internally­generated video timing will be used.

Pixel Port Timing

The the timing and format of the output data and control sig­nals is presented in the following sections.

HSYNC AND VSYNC TIMING

The HSYNC and VSYNC output timing is VMI v1.4 compati­ble. Figures 5-8 illustrate the video timing. The leading edge
of HSYNC is synchronous to the video input signal and has

NTSC(M)

LINE #

PAL(M)
LINE #

523

1

2345678910525524

5245251234567522521

a fixed latency due to internal pipeline processing. The pulse
width of the
36H, where the trailing edge of

HSYNC is defined by the END HSYNC register

HSYNC has a programmable

delay of 0-510 CLK2 cycles from the leading edge.
The leading edge of

VSYNC is asserted approximately half
way through the first serration pulse of each field. For an odd
field, the trailing edge of
the trailing edge of the

VSYNC is 5±1 CLK2 cycles after

HSYNC that follows the last equaliza­tion pulse. Refer to Figures 5 and 7. For an even field, the
trailing edge of
ing edge of the

VSYNC is 5±1 CLK2 cycles leading the lead-

HSYNC that follows the last equalization

pulse. Refer to Figures 6 and 8.

FIELD TIMING

When field information can be determined from the input
video source, the FIELD output pin reflects the video source
field state. When field information cannot be determined
from the input video source, the FIELD output pin alternates
its state at the beginning of each field. FIELD changes state
5

±1 CLK2 cycles before the leading edge of VSYNC.

VIDEO
INPUT

HSYNC

VSYNC

FIELD

NOTE:

3. The trailing edge of VSYNC is 5±1 clocks after the trailing edge of HSYNC to be VMI compatible and to indicate atransitiontoanoddfield.

FIGURE 5. NTSC(M) AND PAL(M) HSYNC, VSYNC AND FIELD TIMING DURING AN EVEN TO ODD FIELD TRANSITION

NTSC(M)

LINE #

PAL(M)

LINE #

VIDEO
INPUT

HSYNC

VSYNC

‘EVEN’ FIELD

264
261

265 266 267 268 269 270 271 272 273263262
262 263 264 265 266 267 268 269 270260259

‘ODD’ FIELD

FIELD

NOTE:

4. The trailingedgeof VSYNC is5±1clocksafter the leading edge of HSYNC to be VMI compatible and to indicate a transitiontoaneven field.

FIGURE 6. NTSC(M) AND PAL(M) HSYNC, VSYNC AND FIELD TIMING DURING AN ODD TO EVEN FIELD TRANSITION

‘ODD’ FIELD ‘EVEN’ FIELD

9

VIDEO

INPUT

HSYNC

VSYNC

HMP8115

623LINE # 6246251234567622621

FIELD

NOTE:

5. The trailing edgeofVSYNCis5±1 clocks after the trailing edge of HSYNC istobeVMIcompatibleandtoindicateatransitiontoanoddfield.

FIGURE 7. PAL(B,D,G,H,I,N,NC) HSYNC, VSYNC AND FIELD TIMING DURING AN EVEN TO ODD FIELD TRANSITION

VIDEO
INPUT

HSYNC

VSYNC

FIELD

NOTE:

6. The trailingedgeof VSYNC is5±1clocksafter the leading edge of HSYNC to be VMI compatible and to indicate a transitiontoaneven field.

FIGURE 8. PAL(B,D,G,H,I,N,NC) HSYNC, VSYNC AND FIELD TIMING DURING AN ODD TO EVEN FIELD TRANSITION

‘EVEN’ FIELD

311LINE # 312 313 314 315 316 317 318 319 320310309

‘ODD’ FIELD ‘EVEN’ FIELD

BLANK AND DVALID TIMING

DVALID is asserted when P15-P0 contain valid data. The
timing and behavior of
video format and the programmed values for bit 4
(DVLD_DCYC) and bit 5 (DVLD_LTC) of the GENLOCK
CONTROL register 04
format sections that follow for the specific behavior for
DVALID.

BLANK is used to determine if the HMP8115 is generating
active video data.
DVALID to capture digital data from the decoder. BLANK,
DVALID and the video data are output after the internal pipe­line latency and synchronous with the rising edge of CLK2.

DVALID is dependent on the output

. Refer to the specific output video

H

BLANK should be used in conjunction with

‘ODD’ FIELD

During active scan lines

BLANK is negated when the hori­zontal pixel count matches the value in the END H_BLANK
register 32
the leading edge of the sync tip after leaving the part.

. A count of 00Hcorresponds to the 50% point of

H

BLANK
is asserted when the horizontal pixel count matches the value
in the START H_BLANK register 31
tally,

BLANK is programmable with two pix el resolution.

START V_BLANK register 34
ister 35

determine which scan lines are blanked for each

H

H

field. During inactive scan lines,

/30H. Note that horizon-

H

/33Hand END V_BLANK reg-

BLANK is asserted during
the entire scan line. Half-line blanking of the output video
cannot be done. Reference Figure 9 for active video timing
and use Table 2 for typical blanking programming values.

VIDEO STANDARD

(MSB/LSB)

RECTANGULAR PIXELS

NTSC (M), PAL (M)

PAL (B, D, G, H, I,N, NC)

SQUARE PIXELS

NTSC (M), PAL (M)

PAL (B, D, G, H, I,N, NC)

TABLE 2. TYPICAL VALUES FOR HBLANK AND VBLANK REGISTERS

ACTIVE
PIXELS/

LINE

720
720

640
768

TOTAL

PIXELS/

LINE

858
864

780
944

LAST

PIXEL

COUNT

857 (0359H)
863 (035FH)

779 (030BH)
943 (03AFH)

START
H_BLANK
(31H/30H)

842 (034AH)
852 (0354H)

758 (02F6H)
922 (039AH)

END

H_BLANK

(32H)

122 (7AH)
132 (84H)

118 (76H)
154 (9AH)

10

START
V_BLANK
(34H/33H)

259 (0103H)
310 (0136H)

259 (0103H)
310 (0136H)

END

V_BLANK

(35H)

19 (13H)
22 (16H)

19 (13H)
22 (16H)

HMP8115

480 ACTIVE
LINES/FRAME
(NTSC, PAL M)

NTSC M PAL B, D, G, H, I, N, N

LINES 1 - 22 NOT ACTIVE

240 ACTIVE LINES

PER FIELD

(LINES 23-262)

LINES 263 - 284 NOT ACTIVE

240 ACTIVE LINES

PER FIELD

(LINES 285 - 524)

LINE 525

NOT ACTIVE

TOTAL PIXELS

ACTIVE PIXELS

ODD FIELD

SYNC AND

PORCH

VERTICAL
BLANKING

EVEN FIELD

FRONT
PORCH

NUMBER OF PIXELS

RECTANGULAR (SQUARE)

NTSC PAL

858
720

(780)
(640)

864
720

BACK

(944)
(768)

LINES 1 - 22 NOT ACTIVE

288 ACTIVE LINES

PER FIELD

(LINES 23 - 310)

LINES 311 - 335 NOT ACTIVE

288 ACTIVE LINES

PER FIELD

(LINES 336 - 623)

LINES 624-625

TOTAL PIXELS

ACTIVE PIXELS

C

NOT ACTIVE

576 ACTIVE

LINES/FRAME

NOTE:

7. The line numbering for PAL (M) followings NTSC (M) line count minus 3 per the video standards.

FIGURE 9. TYPICAL ACTIVE VIDEO REGIONS

TABLE 3. PIXEL OUTPUT FORMATS

PIN NAME 8-BIT, 4:2:2, YCbCr 16-BIT, 4:2:2, YCbCr 15-BIT, RGB, (5,5,5) 16-BIT, RGB, (5,6,5) BT.656

P0
P1
P2
P3
P4
P5
P6
P7

P8
P9

P10
P11
P12
P13
P14
P15

0
0
0
0
0
0
0
0

Y0, Cb0, Cr0
Y1, Cb1, Cr1
Y2, Cb2, Cr2
Y3, Cb3, Cr3
Y4, Cb4, Cr4
Y5, Cb5, Cr5
Y6, Cb6, Cr6
Y7, Cb7, Cr7

Cb0, Cr0
Cb1, Cr1
Cb2, Cr2
Cb3, Cr3
Cb4, Cr4
Cb5, Cr5
Cb6, Cr6
Cb7, Cr7

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

B0
B1
B2
B3

B4
G0
G1
G2

G3
G4
R0
R1
R2
R3
R4

0

B0
B1
B2
B3
B4
G0
G1
G2

G3
G4
G5
R0
R1
R2
R3
R4

YCbCr Data,

Ancillary Data,

SAV and EAV

Sequences

(PAL)

0
0
0
0
0
0
0
0

PIXEL OUTPUT PORT

Pixel data is output via the P0-P15 pins. Refer to Table 3 for
the output pin definition as a function of the output mode.

8-BIT YCbCr OUTPUT

The DVALID output pin may be configured to operate in one
of two ways. The configuration is determined by the
DVLD_LTC bit (bit 4) of the GENLOCK CONTROL register
04

.

H

If DVLD_LTC=0, the
during the entire active video time on active scan lines if CLK2
is exactly 2x the desired output sample rate.
asserted indicates valid pixel data is present on the P15-P8
pixel outputs.
intervals. Refer to Figure 10.

DVALID output is continuously asserted

DVALID being

DVALID is never asserted during the blanking

If DLVD_LTC=1,

DVALID has the same internal timing as the
first mode, but is ANDed with the CLK2 signal, and the result
is output onto the

DVALID pin. This results in a gated CLK2
signal being output during the active video time on active
scan lines. Refer to Figure 11.

If 8-bit YCbCr data is generated, it is output following each
rising edge of CLK2. The YCbCr data is multiplexedas [Cb Y
Cr Y′ CbYCrY′...], with the first active data each scan line
containing Cb data. The pixel output timing is shown in Fig­ures 10 and 11.

BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2. When
is asserted and

VBIVALID is deasserted, the YCbCr outputs

have a value of 16 for Y and 128 for Cb and Cr.

11

BLANK

CLK

DVALID

BLANK

HMP8115

P[15-8]

NOTE:

t

DVLD

Cb

Y

0

0

Cr

Y

0

Cb

1

Y

2

2

Cr

Y

2

3

Cb

Y

4

4

8. Y0is the first active luminance pixel data of a line. Cb0and Cr0are first active chrominance pixel data in a line. Cb and Cr will alternate
every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values on the ports are forced to
blanking levels.

FIGURE 10. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 0)

CLK

DVALID

BLANK

P[15-8]

NOTES:

t

DVLD

Cb

Y

0

0

Cr

Y

0

Cb

1

Y

2

2

Cr

Y

2

Cb

3

Y

4

4

9. Y0is the first active luminance pixel data of a line. Cb0and Cr0are first active chrominance pixel data in a line. Cb and Cr will alternate
every cycle due to the 4:2:2 subsampling. Pixel data is not output during the blanking period, but the values on the ports are forced to
blanking levels.

10. When DVLD_LTC is set to 1, the polarityof DVALID needs to be set to active low, otherwiseDVALID will stay low during active video and
be gated with the clock only during the blanking interval.

FIGURE 11. OUTPUT TIMING FOR 8-BIT YCbCr MODE (DVLD_LTC = 1)

16-BIT YCbCr, 15-BIT RGB, OR 16-RGB OUTPUT

In these output modes, DVALID may be configured to oper­ate in one of four modes as controlled by the DVLD_LTC and
DVLD_DCYC bits of the GENLOCK CONTROL register
(04

). Bit 4 is the DVLD_LTC bit and bit 5 is the

H

DVLD_DCYC bit.
If DVLD_LTC=0 and DVLD_DCYC=0,

only during the active video time on active scan lines. Thus,
DVALID being asserted indicates valid pixel data is present
on the P0-P15 pixel outputs.

DVALID is never asserted dur­ing the blanking intervals. In this mode
50% duty cycle only during the active video times. The tim­ing diagrams for this mode can be found in Figures 12 and

13.
If DVLD_LTC=0 and DVLD_DCYC=1,

same as the first mode, with the exception that
not have a 50% duty cycle. This mode is intended for back­ward compatibility with HMP8112(A) timing dependencies in

DVALID is present

DVALID will have a

DVALID behaves the

DVALID does

which

DVALID did not have a 50% duty cycle timing and
other timing variations. The timing diagrams for this mode
can be found in Figures 14 and 15.

If DVLD_LTC=1 and DVLD_DCYC=0,
entire line time on all scan lines.

DVALID is present the

DVALID may occasionally
be negated for two consecutive CLK2 cycles just prior to
active video. In this mode

DVALID is guaranteed have a 50%
duty cycle only during the active video times. The timing for
this mode differs from the timing shown in Figures 12 and 13
only in that

DVALID will also be asserted during the blanking

portion of the video line time as described above.
If DVLD_LTC=1 and DVLD_DCYC=1,

during the entire line time on all scan lines.

DVALID is present

DVALID is
asserted during the blanking intervals as needed to ensure a
constant number of total samples per line. The timing for this
mode differs from the timing shown in Figures 14 and 15
only in that

DVALID will also be asserted during the blanking

portion of the video line time as described above.

12

HMP8115

If 16-bit YCbCr, 15-bit RGB data, or 16-bit RGB data is gen­erated, it is output following the rising edge of CLK2 while
DVALID is asserted. Either linear or gamma-corrected RGB
data may be output. The pixel output timing is shown in Fig­ures 12 to 15.

CLK

DVALID

BLANK

Cb

Y

0

0

Y

1

Cr

0

P15-P8

P7-P0

t

DVLD

BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2. When
is asserted and

VBIVALID is deasserted, the YCbCr outputs

BLANK

havea value of 16 for Y and 128 for Cb and Cr; the RGB out­puts have a value of 0.

Cb

Y

2

2

Y

3

Cr

2

Cb

Y

4

4

NOTES:

11. Y0is the first active luminance pixel data of a line. Cb0and Cr0are first active chrominance pixel data in a line. Cb and Cr will alternate
every cycle due to the 4:2:2 subsampling.

12. BLANK is asserted per Figure 9.

FIGURE 12. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 0)

CLK

DVALID

P15-P11

[P14-P10]

P10-P5

[P9-P5]

P4-P0

t

NOTE:

DVLD

13. BLANK is asserted per Figure 9.

FIGURE 13. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 0)

R

0

G

0

B

0

R

1

G

1

B

1

R

2

G

2

B

2

R

3

G

3

B

3

R

4

G

4

B

4

13