intersil HM-6642-883 DATA SHEET

®

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HM-6642/883

Data Sheet March 2004

512 x 8 CMOS PROM

The HM-6642/883 is a 512 x 8 CMOS NiCr fusible link
Programmable Read Only Memory in the popular 24 pin,
byte wide pinout. Synchronous circuit design techniques
combine with CMOS processing to give this device high
speed performance with very low power dissipation.

On-chip address latches are provided, allowing easy
interfacing with recent generation microprocessors that use
multiplexed address/data bus structures, such as the 8085.
The output enable controls, both active low and active high,
further simplify microprocessor system interfacing by
allowing output data bus control independent of the chip
enable control. The data output latches allow the use of the
HM-6642/883 in high speed pipelined architecture systems,
and also in synchronous logic replacement functions.

Applications for the HM-6642/883 CMOS PROM include low
power hand held microprocessor based instrumentation and
communications systems, remote data acquisition and
processing systems, processor control store, and
synchronous logic replacement.

FN3013.2

Features

• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.

• Low Power Standby and Operating Power

- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz

• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 120/200ns

• Wide Operating . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

• Temperature Range

• Industry Standard Pinout

• Single 5.0V Supply

• CMOS/TTL Compatible Inputs

• Field Programmable

• Synchronous Operation

• On-Chip Address Latches

• Separate Output Enable

All bits are manufactured storing a logical “0” and can be
selectively programmed for a logical “1” at any bit location.

Ordering Information

TEMP.

PKG.

RANGE (°C) 120ns 200ns

SBDIP -55 to +125 HM1-6642B/883 HM1-6642/883 D24.6

SLIM

-55 to +125 HM6-6642B/883 HM6-6642/883 D24.3

SBDIP

CLCC -55 to +125 - HM4-6642/883 J28.A

PKG.

DWG. #

Pinouts

M-6642/883 (SBDIP)

TOP VIEW

A7

A6

A5

A4

A3

A2

A1

A0

Q0

Q1

Q2

GND

1

2

3

4

5

6

7

8

9

10

11

12

24

V

CC

A8

23

22

G1

21

G2

20

G3

E

19

P

18

17

Q7

Q6

16

Q5

15

Q4

14

Q3

13

Pin Description

PIN DESCRIPTION

NC No Connect

A0-A8 Address Inputs

E

Q Data Output

V

Power (+5V)

CC

, G2, G3 Output Enable

G1

P (Note) Program Enable

NOTE: P should be hardwired to GND except during programming.

A4

5

A3

6

A2

7

A1

8

9

A0

NC

10

Q0

11

Chip Enable

HM-6642/883 (CLCC)

TOP VIEW

A5

A6

A7

NC

3 2 14

14 15 16 17 1812 13

Q1

Q2

GND

NC

CC

A8

V

28 27 26

Q3Q5Q4

G1

25

G2

24

G3

E

23

22

P

21

NC

20

Q7

19

Q6

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2004. All Rights Reserved

Functional Diagram

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HM-6642/883

A8

A7

A6

A5

A4
A3

A2

A1
A0

E

G1

G2

G3

LATCHED
ADDRESS

REGISTER

LATCHED
ADDRESS

REGISTER

A

6

GATED

ROW

A

DECODER

6

A

3

A

3

64

8 8

D

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

64 x 64

MATRIX

8 8

8 8

GATED COLUMN

DECODER

8-BIT DATA LATCH

ALL LINES POSITIVE LOGIC - ACTIVE HIGH
THREE STATE BUFFERS:

A HIGH

DATA LATCHES:

8

8

L HIGH
Q LATCHES ON RISING EDGE OF E

ADDRESS LATCHES AND GATED DECODERS:

LATCH ON FALLING EDGE OF E
GATE ON FALLING EDGE OF E

P SHOULD BE HARDWIRED TO GND EXCEPT

DURING PROGRAMMING

OUTPUT ACTIVE

Q = D

2

HM-6642/883

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Absolute Maximum Ratings Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V

Input, Output or I/O Voltage. . . . . . . . . . . . GND-0.3V to VCC+0.3V

Typical Derating Factor . . . . . . . . . . . 5mA/MHz Increase in ICCOP

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range . . . . . . . . . . . . . . . .-55°C to +125°C

Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V

Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 to VCC+0.3V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

TABLE 1. HM-6642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS

Device Guaranteed and 100% Tested

(NOTES 1, 4)

PARAMETER SYMBOL

High Level Output Voltage VOH VCC = 4.5V, IO = -1.0mA 1, 2, 3 -55 ≤ T

Low Level Output Voltage VOL VCC = 4.5V, IO = +3.2mA 1, 2, 3 -55 ≤ TA ≤ +125 - 0.4 V

High Impedance Output
Leakage Current

Input Leakage Current II VCC = 5.5V, VI = GND or VCC,

Standby Supply Current ICCSB VI = VCC or GND, VCC = 5.5V,

Operating Supply Current ICCOP VCC = 5.5V, G

Functional Test FT VCC = 4.5V (Note 5) 7, 8A, 8B -55 ≤ T

IIOZ VCC = 5.5V, G

CONDITIONS

= 5.5V,

VI/O = GND or VCC

P Not Tested

IO = 0mA

= GND,
G = VCC, (Note 3), f = 1MHz,
IO = 0mA, VI = VCC or GND

Thermal Resistance (Typical) θ

SBDIP Package . . . . . . . . . . . . . . . . . . 52 14

Slim SBDIP . . . . . . . . . . . . . . . . . . . . . 70 19

CLCC Package . . . . . . . . . . . . . . . . . . 58 14

Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1680 Gates

GROUP A

SUBGROUPS

1, 2, 3 -55 ≤ TA ≤ +125 -1.0 1.0 µA

1, 2, 3 -55 ≤ T

1, 2, 3 -55 ≤ T

1, 2, 3 -55 ≤ T

TEMPERATURE

(°C) MIN MAX UNITS

≤ +125 2.4 - V

A

≤ +125 -1.0 1.0 µA

A

≤ +125 - 100 µA

A

≤ +125 - 20 mA

A

≤ +125 - - -

A

(°C/W) θ

JA

JC

(°C/W)

Device Guaranteed and 100% Tested

PARAMETER SYMBOL

Address Access Time TAVQV VCC = 4.5V and 5.5V 9, 10, 11 -55 ≤ T

Output Enable Access Time TGVQV VCC = 4.5V and 5.5V 9, 10, 11 -55 ≤ T

Chip Enable Access Time TELQV VCC = 4.5V and 5.5V 9, 10, 11 -55 ≤ TA ≤ +125 - 120 - 200 ns

Address Setup Time TAVEL VCC = 4.5V and 5.5V 9, 10, 11 -55 ≤ T

Address Hold Time TELAX VCC = 4.5V and 5.5V 9, 10, 11 -55 ≤ T

Chip Enable Low Width TELEH VCC = 4.5V and 5.5V 9, 10, 11 -55 ≤ T

Chip Enable High Width TEHEL VCC = 4.5V and 5.5V 9, 10, 11 -55 ≤ T

Read Cycle Time TELEL VCC = 4.5V and 5.5V 9, 10, 11 -55 ≤ T

NOTES:

1. All voltages referenced to VSS.

2. A.C. measurements assume transition time < 5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1TTL equivalent load
and CL ≅ 50pF.

3. Typical derating = 5mA/MHz increase in ICCOP.

4. All tests performed with P hardwired to GND.

5. Tested as follows: f = 1MHz, VIH = 2.4V, VIL = 0.8V, IOH = -1mA, IOL = +1mA, VOH ≥ 1.5V, VOL ≤ 1.5V.

TABLE 2. HM-6642/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS

(NOTES 1, 2, 4)

CONDITIONS

GROUP A

SUB-

GROUPS

TEMPERATURE

(°C)

≤ +125 - 140 - 220 ns

A

≤ +125 - 50 - 150 ns

A

≤ +125 20 - 20 - ns

A

≤ +125 25 - 60 - ns

A

≤ +125 120 - 200 - ns

A

≤ +125 40 - 150 - ns

A

≤ +125 160 - 350 - ns

A

HM-6642B/883 HM-6642/883

UNITSMIN MAX MIN MAX

3