HM-6642/883
March 1997
Features
• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby and Operating Power
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . .20mA at 1MHz
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 120/200ns
• Wide Operating . . . . . . . . . . . . . . . . . . -55
o
C to +125oC
• Temperature Range
• Industry Standard Pinout
• Single 5.0V Supply
• CMOS/TTL Compatible Inputs
• Field Programmable
• Synchronous Operation
• On-Chip Address Latches
• Separate Output Enable
Ordering Information
PACKAGE TEMP. RANGE 120ns 200ns
SBDIP -55oC to +125oC HM1-
6642B/883
SLIM
SBDIP
CLCC -55oC to +125oC - HM4-
-55oC to +125oC HM66642B/883
HM16642/883
HM66642/883
6642/883
PKG.
NO.
D24.6
D24.3
J28.A
512 x 8 CMOS PROM
Description
The HM-6642/883 is a 512 x 8 CMOS NiCr fusible link
Programmable Read Only Memory in the popular 24 pin,
byte wide pinout. Synchronous circuit design techniques
combine with CMOS processing to give this device high
speed performance with very low power dissipation.
On-chip address latches are provided, allowing easy
interfacing with recent generation microprocessors that use
multiplexed address/data bus structures, such as the 8085.
The output enable controls, both active low and active high,
further simplify microprocessor system interfacing by
allowing output data bus control independent of the chip
enable control. The data output latches allow the use of the
HM-6642/883 in high speed pipelined architecture systems,
and also in synchronous logic replacement functions.
Applications for the HM-6642/883 CMOS PROM include low
power hand held microprocessor based instrumentation and
communications systems, remote data acquisition and
processing systems, processor control store, and synchronous logic replacement.
All bits are manufactured storing a logical “0” and can be
selectively programmed for a logical “1” at any bit location.
Pinouts
M-6642/883 (BDIP)
TOP VIEW
A7
1
A6
2
A5
3
A4
4
A3
5
A2
6
A1
7
A0
8
Q0
9
Q1
10
Q2
11
GND
12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
24
V
CC
A8
23
22
G1
21
G2
20
G3
19
E
P
18
17
Q7
Q6
16
Q5
15
Q4
14
13
Q3
A4
A3
A2
A1
A0
10
NC
11
Q0
| Copyright © Intersil Corporation 1999
HM-6642/883 (CLCC)
A6
A5
3 2 14
5
6
7
8
9
Q1
Q2
TOP VIEW
NC
A7
14 15 16 17 1812 13
NC
GND
6-243
CC
A8
V
28 27 26
Q3Q5Q4
G1
25
24
23
22
21
20
19
G2
G3
E
P
NC
Q7
Q6
PIN DESCRIPTION
PIN DESCRIPTION
NC No Connect
A0-A8 Address Inputs
E Chip Enable
Q Data Output
V
CC
G1, G2, G3 Output Enable
P (Note) Program Enable
NOTE: P should be hardwired to GND
Power (+5V)
except during programming.
File Number 3013.1
Functional Diagram
HM-6642/883
A8
A7
A6
A5
A4
A3
A2
A1
A0
E
G1
G2
G3
LATCHED
ADDRESS
REGISTER
LATCHED
ADDRESS
REGISTER
A
6
GATED
ROW
A
DECODER
6
A
3
A
3
64
8 8
D
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
64 x 64
MATRIX
8 8
8 8
GATED COLUMN
DECODER
8-BIT DATA LATCH
ALL LINES POSITIVE LOGIC - ACTIVE HIGH
THREE STATE BUFFERS:
A HIGH
DATA LATCHES:
8
8
L HIGH
Q LATCHES ON RISING EDGE OF
ADDRESS LATCHES AND GATED DECODERS:
LATCH ON FALLING EDGE OF
GATE ON FALLING EDGE OF
P SHOULD BE HARDWIRED TO GND EXCEPT
DURING PROGRAMMING
OUTPUT ACTIVE
Q = D
E
E
E
6-244
HM-6642/883
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VCC+0.3V
Typical Derating Factor. . . . . . . . . . . . 5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±4.5V
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 to VCC+0.3V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
TABLE 1. HM-6642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
(NOTES 1, 4)
PARAMETER SYMBOL
CONDITIONS
Thermal Resistance (Typical) θ
SBDIP Package. . . . . . . . . . . . . . . . . . 52oC/W 14oC/W
Slim SBDIP . . . . . . . . . . . . . . . . . . . . . 70oC/W 19oC/W
CLCC Package . . . . . . . . . . . . . . . . . . 58oC/W 14oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
JA
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1680 Gates
LIMITS
GROUP A
SUBGROUPS TEMPERATURE
θ
JC
UNITSMIN MAX
High Level Output
Voltage
Low Level Output
Voltage
High Impedance
Output Leakage
Current
Input Leakage
Current
Standby Supply
Current
Operating Supply
Current
Functional Test FT VCC = 4.5V (Note 5) 7, 8A, 8B -55oC ≤ TA≤ +125oC---
Device Guaranteed and 100% Tested
PARAMETER SYMBOL
VOH VCC = 4.5V,
IO = -1.0mA
VOL VCC = 4.5V,
IO = +3.2mA
IIOZ VCC = 5.5V, G = 5.5V,
VI/O = GND or VCC
II VCC = 5.5V, VI = GND or
VCC, P Not Tested
ICCSB VI = VCC or GND,
VCC = 5.5V, IO = 0mA
ICCOP VCC = 5.5V, G = GND,
G = VCC, (Note 3),
f = 1MHz,IO = 0mA,
VI = VCC or GND
TABLE 2. HM-6642/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
(NOTES 1, 2, 4)
CONDITIONS
1, 2, 3 -55oC ≤ TA≤ +125oC 2.4 - V
1, 2, 3 -55oC ≤ TA≤ +125oC - 0.4 V
1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 1.0 µA
1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 1.0 µA
1, 2, 3 -55oC ≤ TA≤ +125oC - 100 µA
1, 2, 3 -55oC ≤ TA≤ +125oC - 20 mA
GROUP A
SUB-
GROUPS TEMPERATURE
6642B/883
MIN MAX MIN MAX
HM-
LIMITS
HM-
6642/883
UNITS
Address Access Time TAVQV VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC - 140 - 220 ns
Output Enable Access Time TGVQV VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC - 50 - 150 ns
Chip Enable Access Time TELQV VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC - 120 - 200 ns
Address Setup Time TAVEL VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC 20 - 20 - ns
Address Hold Time TELAX VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC 25 - 60 - ns
Chip Enable Low Width TELEH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC 120 - 200 - ns
Chip Enable High Width TEHEL VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC 40 - 150 - ns
6-245