Intersil Corporation HM-6617-883 Datasheet

HM-6617/883

March 1997

Features

• This Circuit is Processed in Accordance to MIL-STD­883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.

• Low Power Standby and Operating Power

- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . .20mA at 1MHz

• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 90/120ns

• Industry Standard Pinout

• Single 5.0V Supply

• CMOS/TTL Compatible Inputs

• High Output Drive . . . . . . . . . . . . . . . . 12 LSTTL Loads

• Synchronous Operation

• On-Chip Address Latches

• Separate Output Enable

o

• Operating Temperature Range. . . . . . -55

C to +125oC

Ordering Information

2K x 8 CMOS PROM

Description

The HM-6617/883 is a 16,384-bit fuse link CMOS PROM in
a 2K word by 8-bit/word format with “Three-State” outputs.
This PROM is available in the standard 0.600 inch wide 24
pin SBDIP, the 0.300 inch wide slim SBDIP, and the JEDEC
standard 32 pad CLCC.

The HM-6617/883 utilizes a synchronous design technique.
This includes on-chip address latches and a separate output
enable control which makes this device ideal for applications
utilizing recent generation microprocessors. This design
technique, combined with the Intersil advanced self-aligned
silicon gate CMOS process technology offers ultra-low
standby current. Low ICCSB is ideal for battery applications
or other systems with low power requirements.

The Intersil NiCr fuse link technology is utilized on this and
other Intersil CMOS PROMs. This gives the user a PROM
with permanent, stable storage characteristics over the full
industrial and military temperature voltage ranges. NiCr fuse
technology combined with the low power characteristics of
CMOS provides an excellent alternative to standard bipolar
PROMs or NMOS EPROMs.

All bits are manufactured storing a logical “0” and can be
selectively programmed for a logical “1” at any bit location.

PACKAGE TEMPERATURE RANGE 90ns 120ns PACKAGE NO.

SBDIP -55oC to +125oC HM1-6617B/883 HM1-6617B/883 D24.6
SLIM SBDIP -55oC to +125oC HM6-6617B/883 HM6-6617B/883 D24.3
CLCC -55oC to +125oC HM4-6617B/883 HM4-6617B/883 J32.A

Pinouts

HM-6617/883 (SBDIP)

TOP VIEW

1

A7

2

A6

3

A5

4

A4

5

A3

6

A2

7

A1

8

A0

9

Q0

10

Q1

11

Q2

12

GND

24

V

CC

23

A8

22

A9

21

P

20

G

19

A10

18

E

17

Q7

16

Q6

15

Q5

14

Q4

13

Q3

A6
A5

A4
A3
A2
A1
A0

NC

Q0

HM-6617/883 (CLCC)

TOP VIEW

NC

NC

A7

NC

1

3 2

4 32 31 30

5
6

7
8

9
10
11
12
13

14

16 17 18 19 20

15

Q1

Q2

NC

GND

CC

NC

NC

V

Q3Q4Q5

PIN DESCRIPTION

PIN DESCRIPTION

29

A8

28

A9

27

NC

26

P
G

25

A10

24

E

23
22

Q7
Q6

21

NC No Connect
A0-A10 Address Inputs
E Chip Enable
Q Data Output
V

CC

Power (+5V)
G Output Enable
P (Note) Program Enable

NOTE: P should be hardwired to V

except during programming.

CC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

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File Number 3016.1

Functional Diagram

HM-6617/883

MSB

A10

A9
A8

A7
A6
A5
A4

LSB

E

G

ALL LINES POSITIVE LOGIC: ACTIVE HIGH
THREE-STATE BUFFERS:

A HIGH OUTPUT ACTIVE

ADDRESS LATCHES AND GATED DECODERS:

LATCH ON FALLING EDGE OF E
GATE ON FALLING EDGE OF

LATCHED
ADDRESS

REGISTER

A

7

DECODER

A

7

L

G

GATED

ROW

128 x 128

128

G

16

G

L

MSB LSB

MATRIX

16 16 16 16 16 16 16

GATED COLUMN

DECODER AND DATA

OUTPUT CONTROL

A

4

LATCHED ADDRESS

REGISTER

A

4

8

A0A1A2A3

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

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HM-6617/883

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V

Typical Derating Factor. . . . . . . . . . . . 5mA/MHz Increase in ICCOP

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating Conditions

Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC

Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V

Input High Voltage . . . . . . . . . . . . . . . . . . . . . . +2.4V to VCC +0.3V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

TABLE 1. HM-6617/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS

Device Guaranteed and 100% Tested

(NOTES 1, 4)

PARAMETER SYMBOL

High Level Output Voltage VOH1 VCC = 4.5V, IO = -2.0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC 2.4 - V

Low Level Output Voltage VOL VCC = 4.5V, IO = +4.8mA 1, 2, 3 -55oC ≤ TA ≤ +125oC - 0.4 V

CONDITIONS

Thermal Resistance θ

JA

θ

JC

SBDIP Package. . . . . . . . . . . . . . . . . . 48oC/W 9oC/W

Slim SBDIP . . . . . . . . . . . . . . . . . . . . . 65oC/W 14oC/W

CLCC Package . . . . . . . . . . . . . . . . . . 58oC/W 19oC/W

Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5473 Gates

LIMITS

GROUP A

SUBGROUPS TEMPERATURE

UNITSMIN MAX

High Impedance Output
Leakage Current

Input Leakage Current II VCC = 5.5V, VI = GND or

IIOZ VCC = 5.5V, G = 5.5V,

VI/O = GND or VCC

1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 1.0 µA

1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 1.0 µA

VCC, P Not Tested

Standby Supply Current ICCSB VI = VCC or GND,

1, 2, 3 -55oC ≤ TA ≤ +125oC - 100 µA

VCC = 5.5V, IO = 0mA

Operating Supply Current ICCOP VCC = 5.5V, G = GND,

1, 2, 3 -55oC ≤ TA ≤ +125oC - 20 mA
(Note 3), f = 1MHz, IO =
0mA, VI = VCC or GND

Functional Test FT VCC = 4.5V (Note 6) 7, 8A, 8B -55oC ≤ TA ≤ +125oC- -

TABLE 2. HM-6617/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS

Device Guaranteed and 100% Tested

(NOTES 1, 2, 4)

PARAMETER SYMBOL

Address Access Time TAVQV VCC = 4.5V and 5.5V

Output Enable Access
Time

Chip Enable Access
Time

Address Setup Time TAVEL VCC = 4.5V and 5.5V 9, 10, 11 -55

TGLQV VCC = 4.5V and 5.5V 9, 10, 11 -55

TELQV VCC = 4.5V and 5.5V 9, 10, 11 -55

CONDITIONS

(Note 5)

GROUP A

SUBGROUPS TEMPERATURE

9, 10, 11 -55oC ≤ TA ≤ +125oC - 105 - 140 ns

LIMITS

HM-6617B/883

o

C ≤ TA ≤ +125oC-40-50ns

o

C ≤ TA ≤ +125oC - 90 - 120 ns

o

C ≤ TA ≤ +125oC15-20-ns

LIMITS

HM-6617/883

UNITSMIN MAX MIN MAX

Address Hold Time TELAX VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC20-25-ns

Chip Enable Low Width TELEH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 95 - 120 - ns

Chip Enable High Width TEHEL VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC40-40-ns

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