Intersil Corporation HM-6617 Datasheet

HM-6617

March 1997

Features

• Low Power Standby and Operating Power

- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . .20mA at 1MHz

• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 90/120ns

• Industry Standard Pinout

• Single 5.0V Supply

• CMOS/TTL Compatible Inputs

• High Output Drive . . . . . . . . . . . . . . . . 12 LSTTL Loads

• Synchronous Operation

• On-Chip Address Latches

• Separate Output Enable

Ordering Information

PACKAGE TEMP. RANGE 90ns 120ns

SBDIP -40oC to +85oC HM1-

6617B-9

SMD# -55oC to +125oC 5962-

8954002JA

SLIM SBDIP

-40oC to +85oC HM66617B-9

SMD# -55oC to +125oC 5962-

8954002LA

CLCC -40oC to +85oC HM4-

6617B-9

SMD# -55oC to +125oC 5962-

8954002XA

HM16617-9

59628954001JA

HM66617-9

59628954001LA

HM46617-9

59628954001XA

PKG.

NO.

D24.6

D24.3

J32.A

2K x 8 CMOS PROM

Description

The HM-6617 is a 16,384 bit fuse link CMOS PROM in a 2K word by 8-bit/word format with “Three-State” outputs. This PROM is available in the standard 0.600 inch wide 24 pin SBDIP, the 0.300 inch wide slimline SBDIP, and the JEDEC standard 32 pad CLCC.

The HM-6617 utilizes a synchronous design technique. This includes on-chip address latches and a separate output enable control which makes this device ideal for applications utilizing recent generation microprocessors. This design technique, combined with the Intersil advanced self-aligned silicon gate CMOS process technology offers ultra-low standby current. Low ICCSB is ideal for battery applications or other systems with low power requirements.

The Intersil NiCr fuse link technology is utilized on this and other Intersil CMOS PROMs. This gives the user a PROM with permanent, stable storage characteristics over the full industrial and military temperature voltage ranges. NiCr fuse technology combined with the low power characteristics of CMOS provides an excellent alternative to standard bipolar PROMs or NMOS EPROMs.

All bits are manufactured storing a logical “0” and can be selectively programmed for a logical “1” at any bit location.

Pinouts

HM-6617 (SBDIP)

TOP VIEW

GND

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207

A10

A6 A5

A4 A3 A2 A1 A0

HM-6617 (CLCC)

TOP VIEW

3 2

4 32 31 30

5 6

7 8

9 10 11 12 13

16 17 18 19 20

GND

Q3Q4Q5

6-1

P G

A10

23 22

Q7 Q6

PIN DESCRIPTION

NC No Connect A0-A10 Address Inputs E Chip Enable Q Data Output V

Power (+5V) G Output Enable P (Note) Output Enable

NOTE: P should be hardwired to V

except during programming.

File Number 3017.1

Functional Diagram

HM-6617

MSB

A10

A9 A8

A7 A6 A5 A4

LSB

ALL LINES POSITIVE LOGIC: ACTIVE HIGH THREE-STATE BUFFERS:

A HIGH OUTPUT ACTIVE

ADDRESS LATCHES AND GATED DECODERS:

LATCH ON FALLING EDGE OF E GATE ON FALLING EDGE OF

LATCHED ADDRESS

DECODER

GATED

ROW

128 x 128

128

MSB LSB

MATRIX

16 16 16 16 16 16 16

GATED COLUMN

DECODER AND DATA

OUTPUT CONTROL

LATCHED ADDRESS

A0A1A2A3

6-2

HM-6617

Background Information Programming Algorithm

The HM-6617 CMOS PROM is manufactured with all bits containing a logical zero (output low). Any bit can be programmed selectively to a logical one (output high) state by following the procedure shown below. To accomplish this, a programmer can be built that meets the speciﬁcations shown, or any of the approved commercial prog rammers can be used.

Programming Sequence Of Events

1. Apply a voltage of V

2. Read all fuse locations to verify that the PROM is blank (output low).

3. Place the PROM in the initial state for programming: E = V

, P = VIH, G = VIL.

4. Apply the correct binary address for the word to be programmed. No inputs should be left open circuit.

5. After a delay of tD, apply voltage of VIL to E (pin 18) to access the addressed word.

6. The address may be held through the cycle, but must be held valid at least for a time equal to tD after the falling edge of

E. None of the inputs should be allowed to float

to an invalid logic level.

7. After a delay of tD, disable the outputs by applying a voltage of V

to G (pin 20).

8. After a delay of tD, apply voltage of V

9. After delay of tD, raise V rise time of tR. All outputs at V V

-2.0V to VCC +0.3V. This could be accomplished by

pulling outputs at V value Rn.

to VCC of the PROM.

CC1

to P (pin 21).

(pin 24) to VCCPROG with a

to VCC through pull-up resistors of

should track VCC with

Post-Programming Veriﬁcation

17. Place the PROM in the post-programming veriﬁcation mode:

E = VIH, G = VIL, P = VIH, VCC (pin 24) = V

CC1

18. Apply the correct binary address of the word to be veriﬁed to the PROM.

19. After a delay of tD , apply a v oltage of VIL to E (pin 18).

20. After a delay of tD , e xamine the outputs f or correct data. If any location fails to verify correctly, the PROM should be considered a programming reject.

21. Repeat steps 17 through 20 for all possible programming locations

Post-Programming Read

22. Apply a voltage of V

23. After a delay of tD , apply a v oltage of V

= 4.0V to VCC (pin 24).

CC2

to E (pin 18).

24. Apply the correct binary address of the word to be read.

25. After a delay of TAVEL, apply a voltage of V

to E (pin

18).

26. After a delay of TELQV, examine the outputs for correct data. If any location fails to verify correctly, the PROM should be considered a programming reject.

27. Repeat steps 23 through 26 for all address locations.

28. Apply a voltage of V

= 6.0V to VCC (pin 24).

CC2

29. Repeat steps 23 through 26 for all address locations.

10. After a delay of tD, pull the output which corresponds to the bit to be programmed to V

. Only one bit should be

programmed at a time.

11. After a delay of tPW, allow the output to be pulled to V

through pull-up resistor Rn.

12. After a delay of tD, reduce V time of tF. All outputs at V to V

+0.3V. This could be accomplished by pulling out-

puts at V

13. Apply a voltage of V

to VCC through pull-up resistors of value Rn.

(pin 24) to V

should track VCC with VCC 2.0V

to P (pin 21).

14. After a delay of tD, apply a voltage of V

with a fall

CC1

to G (pin 20).

15. After a delay of tD, examine the outputs for correct data. If any location verifies incorrectly, repeat steps 4 through 14 (attempting to program only those bits in the word which verified incorrectly) up to a maximum of eight attempts for a given word. If a word does not program within eight attempts, it should be considered a programming reject.

16. Repeat steps 3 through 15 for all other bits to be programmed in the PROM.

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