HM-6617
March 1997
Features
• Low Power Standby and Operating Power
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . .20mA at 1MHz
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . 90/120ns
• Industry Standard Pinout
• Single 5.0V Supply
• CMOS/TTL Compatible Inputs
• High Output Drive . . . . . . . . . . . . . . . . 12 LSTTL Loads
• Synchronous Operation
• On-Chip Address Latches
• Separate Output Enable
Ordering Information
PACKAGE TEMP. RANGE 90ns 120ns
SBDIP -40oC to +85oC HM1-
6617B-9
SMD# -55oC to +125oC 5962-
8954002JA
SLIM
SBDIP
-40oC to +85oC HM66617B-9
SMD# -55oC to +125oC 5962-
8954002LA
CLCC -40oC to +85oC HM4-
6617B-9
SMD# -55oC to +125oC 5962-
8954002XA
HM16617-9
59628954001JA
HM66617-9
59628954001LA
HM46617-9
59628954001XA
PKG.
NO.
D24.6
D24.6
D24.3
D24.3
J32.A
J32.A
2K x 8 CMOS PROM
Description
The HM-6617 is a 16,384 bit fuse link CMOS PROM in a 2K
word by 8-bit/word format with “Three-State” outputs. This
PROM is available in the standard 0.600 inch wide 24 pin
SBDIP, the 0.300 inch wide slimline SBDIP, and the JEDEC
standard 32 pad CLCC.
The HM-6617 utilizes a synchronous design technique. This
includes on-chip address latches and a separate output
enable control which makes this device ideal for applications
utilizing recent generation microprocessors. This design
technique, combined with the Intersil advanced self-aligned
silicon gate CMOS process technology offers ultra-low
standby current. Low ICCSB is ideal for battery applications
or other systems with low power requirements.
The Intersil NiCr fuse link technology is utilized on this and
other Intersil CMOS PROMs. This gives the user a PROM
with permanent, stable storage characteristics over the full
industrial and military temperature voltage ranges. NiCr fuse
technology combined with the low power characteristics of
CMOS provides an excellent alternative to standard bipolar
PROMs or NMOS EPROMs.
All bits are manufactured storing a logical “0” and can be
selectively programmed for a logical “1” at any bit location.
Pinouts
HM-6617 (SBDIP)
TOP VIEW
1
A7
2
A6
3
A5
4
A4
5
A3
6
A2
7
A1
8
A0
9
Q0
10
Q1
11
Q2
12
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
24
V
CC
23
A8
22
A9
21
P
20
G
19
A10
18
E
17
Q7
16
Q6
15
Q5
14
Q4
13
Q3
A6
A5
A4
A3
A2
A1
A0
NC
Q0
| Copyright © Intersil Corporation 1999
HM-6617 (CLCC)
TOP VIEW
NC
NC
A7
NC
1
3 2
4 32 31 30
5
6
7
8
9
10
11
12
13
14
16 17 18 19 20
15
Q1
Q2
NC
GND
CC
NC
V
Q3Q4Q5
6-1
NC
29
A8
28
A9
27
NC
26
P
G
25
A10
24
E
23
22
Q7
Q6
21
PIN DESCRIPTION
PIN DESCRIPTION
NC No Connect
A0-A10 Address Inputs
E Chip Enable
Q Data Output
V
CC
Power (+5V)
G Output Enable
P (Note) Output Enable
NOTE: P should be hardwired to V
except during programming.
File Number 3017.1
CC
Functional Diagram
HM-6617
MSB
A10
A9
A8
A7
A6
A5
A4
LSB
E
G
ALL LINES POSITIVE LOGIC: ACTIVE HIGH
THREE-STATE BUFFERS:
A HIGH OUTPUT ACTIVE
ADDRESS LATCHES AND GATED DECODERS:
LATCH ON FALLING EDGE OF E
GATE ON FALLING EDGE OF
LATCHED
ADDRESS
REGISTER
A
7
DECODER
A
7
L
G
GATED
ROW
128 x 128
128
G
16
G
L
MSB LSB
MATRIX
16 16 16 16 16 16 16
GATED COLUMN
DECODER AND DATA
OUTPUT CONTROL
A
4
LATCHED ADDRESS
REGISTER
A
4
8
A0A1A2A3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
6-2
HM-6617
Background Information Programming
Algorithm
The HM-6617 CMOS PROM is manufactured with all bits
containing a logical zero (output low). Any bit can be programmed selectively to a logical one (output high) state by
following the procedure shown below. To accomplish this, a
programmer can be built that meets the specifications
shown, or any of the approved commercial prog rammers can
be used.
Programming Sequence Of Events
1. Apply a voltage of V
2. Read all fuse locations to verify that the PROM is blank
(output low).
3. Place the PROM in the initial state for programming: E =
V
, P = VIH, G = VIL.
IH
4. Apply the correct binary address for the word to be programmed. No inputs should be left open circuit.
5. After a delay of tD, apply voltage of VIL to E (pin 18) to access the addressed word.
6. The address may be held through the cycle, but must be
held valid at least for a time equal to tD after the falling
edge of
E. None of the inputs should be allowed to float
to an invalid logic level.
7. After a delay of tD, disable the outputs by applying a voltage of V
to G (pin 20).
IH
8. After a delay of tD, apply voltage of V
9. After delay of tD, raise V
rise time of tR. All outputs at V
V
-2.0V to VCC +0.3V. This could be accomplished by
CC
pulling outputs at V
value Rn.
to VCC of the PROM.
CC1
to P (pin 21).
IL
(pin 24) to VCCPROG with a
CC
to VCC through pull-up resistors of
IH
should track VCC with
IH
Post-Programming Verification
17. Place the PROM in the post-programming verification
mode:
E = VIH, G = VIL, P = VIH, VCC (pin 24) = V
CC1
18. Apply the correct binary address of the word to be verified to the PROM.
19. After a delay of tD , apply a v oltage of VIL to E (pin 18).
20. After a delay of tD , e xamine the outputs f or correct data.
If any location fails to verify correctly, the PROM should
be considered a programming reject.
21. Repeat steps 17 through 20 for all possible programming
locations
Post-Programming Read
22. Apply a voltage of V
23. After a delay of tD , apply a v oltage of V
= 4.0V to VCC (pin 24).
CC2
to E (pin 18).
IH
24. Apply the correct binary address of the word to be read.
25. After a delay of TAVEL, apply a voltage of V
to E (pin
IL
18).
26. After a delay of TELQV, examine the outputs for correct
data. If any location fails to verify correctly, the PROM
should be considered a programming reject.
27. Repeat steps 23 through 26 for all address locations.
28. Apply a voltage of V
= 6.0V to VCC (pin 24).
CC2
29. Repeat steps 23 through 26 for all address locations.
.
10. After a delay of tD, pull the output which corresponds to
the bit to be programmed to V
. Only one bit should be
IL
programmed at a time.
11. After a delay of tPW, allow the output to be pulled to V
IH
through pull-up resistor Rn.
12. After a delay of tD, reduce V
time of tF. All outputs at V
to V
+0.3V. This could be accomplished by pulling out-
CC
puts at V
13. Apply a voltage of V
to VCC through pull-up resistors of value Rn.
IH
IH
(pin 24) to V
CC
should track VCC with VCC 2.0V
IH
to P (pin 21).
14. After a delay of tD, apply a voltage of V
with a fall
CC1
to G (pin 20).
IL
15. After a delay of tD, examine the outputs for correct data. If
any location verifies incorrectly, repeat steps 4 through 14
(attempting to program only those bits in the word which
verified incorrectly) up to a maximum of eight attempts for
a given word. If a word does not program within eight attempts, it should be considered a programming reject.
16. Repeat steps 3 through 15 for all other bits to be programmed in the PROM.
6-3
Programming Cycle
HM-6617
PROGRAMMING
VCC PROG
A
E
G
P
V
CC
Q
V
V
V
V
VCC PROG
V
V
VCC PROG
V
V
VCC PROG
V
CC
GND
V
PROG
CC
V
IH/VOH
VIL/V
OL
IH
IL
IH
IL
IH
IL
IH
IL
tD
tD
VALID
tD
tD
tD
tR
tD tD
tPW
tF
VERIFY
VALID
TEHEL
READ DATA
FIGURE 1. HM-6617 PROGRAMMING CYCLE
V
IH
A
V
IL
V
IH
E
V
IL
6.0V
5.0V
4.0V
V
CC
0.0V
V
OH
Q
V
OL
TAVEL
TEHEL
VALID
TELQV
READ
TEHEL
TELQV
TEHEL
tDtD
TELQV
READ READ
FIGURE 2. HM-6617 POST PROGRAMMING VERIFY CYCLE
6-4
HM-6617
Background Information HM-6617 Programming
Programming Specifications
SYMBOL PARAMETER MIN TYP MAX UNITS
V
IL
V
IH
VCCPROG Programming VCC (Note 2) 12.0 12.0 12.5 V
V
CC1
V
CC2
tD Delay Time 1.0 1.0 - µs
tR Rise Time 1.0 10.0 10.0 µs
tF Fall Time 1.0 10.0 10.0 µs
TEHEL Chip Enable Pulse Width 50 - - ns
TAVEL Address Valid to Chip Enable Low Time 20 - - ns
TELQV Chip Enable Low to Output Valid Time - - 120 ns
tPW Programming Pulse Width (Note 4) 90 100 110 µs
tIP Input Leakage at VCC = VCCPROG -10 +1.0 10 µA
IOP Data Output Current at VCC = VCCPROG - -5.0 -10 mA
Rn Output Pull-Up Resistor (Note 5) 5 10 15 kΩ
T
A
Input “0” 0.0 0.2 0.8 V
Voltage “1” (Note 6) VCC-2 V
Operating V
Special Verify VCC (Note 3) 4.0 - 6.0 V
Ambient Temperature - 25 -
CC
4.5 5.5 5.5 V
CC
VCC+0.3 V
o
C
NOTES:
1. All inputs must track VCC (pin 24) within these limits.
2. VCCPROG must be capable of supplying 500mA.
3. See Steps 22 through 29 of the Programming Algorithm.
4. See Step 11 of the Programming Algorithm.
5. All outputs should be pulled up to VCC through a resistor of value Rn.
6. Except during programming (See Programming Cycle Waveforms).
6-5
HM-6617
Absolute Maximum Ratings Thermal Information
Supply Voltage (All Voltages Reference to Device GND). . . . .+7.0V
Input or Output Voltage Applied for All Grades. . . . . . .GND -0.3V to
VCC +0.3V
Typical Derating Factor. . . . . . . . . . . . 5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range: HM-6617-9, B-9 . . . -40oC to +85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Thermal Resistance (Typical) θ
SBDIP Package. . . . . . . . . . . . . . . . . . 48oC/W 9oC/W
Slim SBDIP . . . . . . . . . . . . . . . . . . . . . 65oC/W 14oC/W
CLCC Package . . . . . . . . . . . . . . . . . . 58oC/W 19oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC
JA
θ
JC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5473 Gates
DC Electrical Specifications V
SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS
V
IH
V
IL
VOH1 Logical One Output Voltage 2.4 - V IOH = -2.0mA, VCC = 4.5V
VOH2 Logical One Output Voltage
VOL Logical Zero Output Voltage - 0.4 V IOL = +4.8mA, VCC = 4.5V
II Input Leakage -1.0 +1.0 µAVIN = VCC or GND, VCC = 5.5V
IOZ Output Leakage -1.0 +1.0 µAVO = VCC or GND, G = VCC, VCC = 5.5V
ICCSB Standby Power Supply Current - 100 µAVIN = VCC or GND, VCC = 5.5V, IO= 0
ICCOP Operating Power Supply Current
Logical One Input Voltage 2.4 VCC+0.3 V VCC = 5.5V
Logical Zero Input Voltage -0.3 0.8 V VCC = 4.5V
(Note 2)
(Note 3)
= 5V ±10%; (HM-6617B-9, HM-6617-9)
CC
VCC-1.0 - V IOH = -100µA, VCC = 4.5V
- 20 mA f = 1MHz, VCC = 5.5V, IO = 0,
VIN = VCC or GND
AC Electrical Specifications
HM-6617B-9 HM-6617-9
SYMBOL PARAMETER
(1) TAVQV Address Access Time - 105 - 140 ns (Notes 1, 4)
(2) TELQV Chip Enable Access Time - 90 - 120 ns (Notes 1, 4)
(3) TELQX Chip Enable Time 5 - 5 - ns (Notes 2, 4)
(4) TAVEL Address Setup Time 15 - 20 - ns (Notes 1, 4)
(5) TELAX Address Hold Time 20 - 25 - ns (Notes 1, 4)
(6) TELEH Chip Enable Low Width 95 - 120 - ns (Notes 1, 4)
(7) TEHEL Chip Enable High Width 40 - 40 - ns (Notes 1, 4)
(8) TELEL Cycle Time 136 - 160 - ns (Notes 1, 4)
(9) TGLQV Output Access Time - 40 - 50 ns (Notes 1, 4)
(10) TGLQX Output Enable Time 5 - 5 - ns (Notes 2, 4)
(11) TGHQZ Output Disable Time - 40 - 50 ns (Notes 2, 4)
(12) TEHQZ Chip Enable Disable Time - 45 - 50 ns (Notes 2, 4)
UNITS TEST CONDITIONSMIN MAX MIN MAX
6-6
HM-6617
Capacitance T
= +25oC
A
SYMBOL PARAMETER MAX UNITS TEST CONDITIONS
CIN Input Capacitance (Note 2) 10 pF f = 1MHz, All Measurement are Referenced to Device GND
COUT Output Capacitance (Note 2) 12 pF f = 1MHz, All Measurement are Referenced to Device GND
NOTES:
1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. Typical derating 5mA/MHz increase in ICCOP.
4. VCC = 4.5V and 5.5V.
Switching Waveforms
TAVQV
ADDRESSES
DAT A
OUTPUT
Q0-Q7
(1)
VALID
ADDRESSES
TEHQZ
(12)
TAVEL
TEHEL
(7)
VALID
ADDRESS
(4)
TELAX
1.5V
(10) TGLQX
1.5V
(5)
TELQV
1.5V
(3)
TELQX
(2)
TELEH
(6)
TGLQV
(9)
TELEL
(8)
1.5V
1.5V
(11)
TGHQZ
VALID
DAT A
1.5V
E
G
1.5V
1.5V
3.0V
0V
3.0V
0V
3.0V
0V
T
S
Test Circuit
DUT
C
L
(NOTE)
NOTE:
TEST HEAD
CAPACITANCE
FIGURE 3. READ CYCLE
I
OH
EQUIVALENT CIRCUIT
FIGURE 4. TEST CIRCUIT
1.5V I
±
OL
6-7
HM-6617
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries f or its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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P. O. Box 883, Mail Stop 53-204
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6-8
ASIA
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