Intersil Corporation HM-65642-883 Datasheet

6-220

March 1997

HM-65642/883

8K x 8 Asynchronous

CMOS Static RAM

Features

• This Circuit is Processed in Accordance to MIL-STD­883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.

• Full CMOS Design

• Six Transistor Memory Cell

• Low Standby Supply Current . . . . . . . . . . . . . . . .100µA

• Low Operating Supply Current. . . . . . . . . . . . . . . 20mA

• Fast Address Access Time. . . . . . . . . . . . . . . . . .150ns

• Low Data Retention Supply Voltage. . . . . . . . . . . . 2.0V

• CMOS/TTL Compatible Inputs/Outputs

• JEDEC Approved Pinout

• Equal Cycle and Access Times

• No Clocks or Strobes Required

• Gated Inputs

- No Pull-Up or Pull-Down Resistors Required

• Temperature Range -55

o

C to +125oC

• Easy Microprocessor Interfacing

• Dual Chip Enable Control

Description

The HM-65642/883 is a CMOS 8192 x 8-bit Static Random
Access Memory. The pinout is the JEDEC 28 pin, 8-bit wide
standard, which allows easy memory board layouts which
accommodate a variety of industry standard ROM, PROM,
EPROM, EEPROM and RAMs. The HM-65642/883 is ideally
suited for use in microprocessor based systems. In particu­lar, interfacing with the Intersil 80C86 and 80C88 micropro­cessors is simplified by the convenient output enable (

G)

input.
The HM-65642/883 is a full CMOS RAM which utilizes an

array of six transistor (6T) memory cells for the most stable
and lowest possible standby supply current over the full mili­tary temperature range. In addition to this, the high stability
of the 6T RAM cell provides excellent protection against soft
errors due to noise and alpha particles. This stability also
improves the radiation tolerance of the RAM over that of four
transistor or MIX-MOS (4T) devices

Ordering Information

PACKAGE TEMPERATURE RANGE 150ns/75µA 150ns/150µA 200ns/250µA PKG. NO.

CERDIP -55oC to +125oC HM1-65642B/883 HM1-65642/883 HM1-65642C/883 F28.6
CLCC -55oC to +125oC HM4-65642B/883 HM4-65642/883 - J32.A

Pinouts

HM-65642/883 (CERDIP)

TOP VIEW

HM4-65642/883 (CLCC)

TOP VIEW

28
27
26
25
24
23
22
21
20
19
18
17
16
15

NC

A12

A7
A6
A5
A4
A3
A2
A1

A0
DQ0
DQ1
DQ2

GND

1
2
3
4
5
6
7
8

9
10
11
12
13
14

VCC

E2
A8
A9
A11

A10

DQ7
DQ6
DQ5
DQ4
DQ3

W

G

E1

5
6

7
8

11

10

9

13

12

27

28

29

26
25
24
23
22
21

3 2

1

4 32 31 30

16 17 18 19 20

14

15

A6
A5

A4
A3
A2
A1
A0

NC

DQ0

DQ1

DQ2

GND

NC

DQ3

DQ4

DQ5

VCC

NC

NC

A7

A12

E2

W

A8
A9

A11

G
A10
E1
DQ7
DQ6

NC

PIN DESCRIPTION

A Address Input

DQ Data Input/Output

E1 Chip Enable
E2 Chip Enable

W Write Enable
G Output Enable

NC No Connections
GND Ground
VCC Power

File Number 3004.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

6-221

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V

Input or Output Voltage Applied for all Grades. . . . . . .GND -0.3V to

VCC +0.3V

Typical Derating Factor. . . . . . . . . . . . 5mA/MHz Increase in ICCOP

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Thermal Resistance (Typical) θ

JA

θ

JC

CERDIP Package . . . . . . . . . . . . . . . . 45oC/W 8oC/W

CLCC Package . . . . . . . . . . . . . . . . . . 55oC/W 10oC/W

Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101,000 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions

Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC

Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V

Input High Voltage. . . . . . . . . . . . . . . . . . . . . . .+2.2V to VCC +0.3V

Data Retention Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 2.0V

Input Rise and Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . .40ns Max.

TABLE 1. HM-65642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS

Device Guaranteed and 100% Tested

PARAMETER SYMBOL

(NOTE 1)

CONDITIONS

GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

High Level Output
Voltage

VOH 1 VCC = 4.5V, IO = -1.0mA 1, 2, 3 -55oC≤ TA≤ +125oC 2.4 - V

Low Level Output
Voltage

VOL VCC = 4.5V, IO = 4.0mA 1, 2, 3 -55oC≤ TA≤ +125oC - 0.4 V

High Impedance
Output Leakage
Current

IIOZ HM-65642B/883, HM-65642/883

VCC = 5.5V, G = 2.2V,
VI/O = GND or VCC

1, 2, 3 -55oC≤ TA≤ +125oC -1.0 +1.0 µA

HM-65642C/883
VCC = 5.5V, G = 2.2V,
VI/O = GND or VCC

1, 2, 3 -55oC≤ TA≤ +125oC -2.0 +2.0 µA

Input Leakage
Current

II HM-65642B/883, HM-65642/883

VCC = 5.5V, VI = GND or VCC

1, 2, 3 -55oC≤ TA≤ +125oC -1.0 +1.0 µA

HM-65642C/883
VCC = 5.5V, VI = GND or VCC

1, 2, 3 -55oC≤ TA≤ +125oC -2.0 +2.0 µA

Standby Supply
Current

ICCSB1 HM-65642B/883

VCC = 5.5V, E1 = VCC -0.3V or
E2 = GND +0.3V

1, 2, 3 -55oC≤ TA≤ +125oC - 100 µA

HM-65642/883
VCC = 5.5V, E1 = VCC -0.3V or
E2 = GND +0.3V

1, 2, 3 -55oC≤ TA≤ +125oC - 250 µA

HM-65642C/883
VCC = 5.5V, E1 = VCC -0.3V or
E2 = GND +0.3V

1, 2, 3 -55oC≤ TA≤ +125oC - 400 µA

Standby Supply
Current

ICCSB VCC = 5.5V, IO = 0mA, E1 = 2.2V or

E2 = 0.8V

1, 2, 3 -55oC≤ TA≤ +125oC- 5 mA

Enable Supply
Current

ICCEN VCC = 5.5V, IO = 0mA, E1 =0.8V,

E2 = 2.2V

1, 2, 3 -55oC≤ TA≤ +125oC- 5 mA

Operating Supply
Current

ICCOP VCC = 5.5V, G = 5.5V, (Note 2),

f = 1MHz, E1 = 0.8V, E2 = 2.2V

1, 2, 3 -55oC≤ TA≤ +125oC - 20 mA

HM-65642/883

6-222

Data Retention
Supply Current

ICCDR HM-65642B/883

VCC = 2.0V, E1 = VCC -0.3V or
E2 = GND +0.3V

1, 2, 3 -55oC≤ TA≤ +125oC- 75 µA

HM-65642/883
VCC = 2.0V, E1 = VCC -0.3V or
E2 = GND +0.3V

1, 2, 3 -55oC≤ TA≤ +125oC - 150 µA

HM-65642C/883
VCC = 2.0V, E1 = VCC -0.3V or
E2 = GND +0.3V

1, 2, 3 -55oC≤ TA≤ +125oC - 250 µA

Functional Test FT VCC = 4.5V (Note 3) 7, 8A, 8B -55oC≤ TA≤ +125oC- - -

NOTES:

1. All voltages referenced to device GND.

2. Typical derating 5mA/MHz increase in ICCOP.

3. Tested as follows: f = 2MHz, VIH = 2.4V, VIL = 0.4V, IOH = -4.0mA, IOL = 4.0mA, VOH ≥ 1.5V, and VOL ≤ 1.5V.

TABLE 1. HM-65642/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)

Device Guaranteed and 100% Tested

PARAMETER SYMBOL

(NOTE 1)

CONDITIONS

GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

TABLE 2. HM-65642/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS

PARAMETERS SYMBOL

(NOTES 1, 2)

CONDITIONS

GROUP A

SUB-

GROUPS TEMPERATURE

LIMITS

UNITS

HM-

65642B/883

HM-

65642/883

HM-

65642C/883

MIN MAX MIN MAX MIN MAX

Read/Write/
Cycle Time

TAVAX VCC = 4.5V and

5.5V

9, 10, 11 -55

o

C ≤ TA≤ +125oC 150 - 150 - 200 - ns

Address Access
Time

TAVQV VCC = 4.5V and

5.5V

9, 10, 11 -55oC ≤ TA≤ +125oC - 150 - 150 - 200 -

Output Enable
Access Time

TGLQV VCC = 4.5V and

5.5V

9, 10, 11 -55oC ≤ TA≤ +125oC - 70 - 70 - 70 ns

Chip Enable
Access Time

TE1LQV
TE2HQV

VCC = 4.5V and

5.5V

9, 10, 11 -55oC ≤ TA≤ +125oC - 150 - 150 - 200 ns

Write Recovery
Time

TWHAX

TE1HAX

TE2LAX

VCC = 4.5V and

5.5V

9, 10, 11 -55

o

C ≤ TA≤ +125oC10-10-10- ns

Chip Enable to
End-of-Write

TE1LE1H
TE2HE2L

VCC = 4.5V and

5.5V

9, 10, 11 -55

o

C ≤ TA≤ +125oC 90 - 90 - 120 - ns

Address Setup
Time

TAVWL
TAVE1L
TAVE2H

VCC = 4.5V and

5.5V

9, 10, 11 -55

o

C ≤ TA≤ +125oC0-0-0-ns

Write Enable
Pulse Width

TWLWH VCC = 4.5V and

5.5V

9, 10, 11 -55

o

C ≤ TA≤ +125oC 90 - 90 - 120 - ns

Data Setup Time TDVWH

TDVE1H

TDVE2L

VCC = 4.5V and

5.5V

9, 10, 11 -55

o

C ≤ TA≤ +125oC60-60-80- ns

HM-65642/883