Intersil Corporation HM-6561 Datasheet
HM-6561
March 1997
Features
• Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 200ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 1 TTL Load
• On-Chip Address Registers
• Common Data In/Out
• Three-State Output
• Easy Microprocessor Interfacing
Ordering Information
PACKAGE TEMPERA TURE RANGE 220ns 300ns PKG. NO.
CERDIP -40oC to +85oC HM1-6561B-9 HM1-6561-9 F18.3
256 x 4 CMOS RAM
Description
The HM-6561 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation.
On-chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays. The data inputs
and outputs are multiplexed internally for common I/O bus
compatibility.
The HM-6561 is a fully static RAM and may be maintained in
any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temper ature.
Pinout
HM-6561
(CERDIP)
TOP VIEW
1
A3
A2
2
A1
3
A0
4
A5
5
A6
6
A7
7
GND
8
9
E
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
S Chip Select
DQ Data In/Out
18
V
CC
A4
17
16
W
15
S1
14
DQ3
13
DQ2
12
DQ1
DQ0
11
10
S2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
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File Number 2991.1
Functional Diagram
HM-6561
A0
A1
A5
A6
A7
DQ0
DQ1
DQ2
DQ3
S1
S2
LATCHED
ADDRESS
REGISTER
A Q
A Q
A Q
A Q
W
E
A
A
L
LATCH
LATCH
LATCH
LATCH
5
5
GATED
ROW
DECODER
D
L
D
L
D
L
D
L
32 x 32
32
G
A
A
A
A
G
L
MATRIX
8 888
GATED COLUMN
DECODER
AND DATA I / O
33
A A
LATCHED ADDRESS
REGISTER
A2
A3
A4
NOTES:
1. All lines positive logic-active high.
2. Three-state Buffers: A high → output active.
3. Data Latches: L high → Q = D and Q latches on falling edge of L.
4. Address Latches and Gated Decoders: Latch on falling edge of E and gate on falling edge of E.
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HM-6561
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input or Output Voltage. . . . . . . . . . . . . . . GND -0.3V to VCC+0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range
Thermal Resistance θ
CERDIP Package . . . . . . . . . . . . . . . . 74oC/W 18oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . .+175oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . .+300oC
JA
θ
JC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1944 Gates
HM-6561B-9, HM6561-9 . . . . . . . . . . . . . . . . . . . .-40oC to +85oC
DC Electrical Specifications V
SYMBOL PARAMETER
ICCSB Standby Supply Current - 10 µA IO = 0mA, VI = VCCor GND,
ICCOP Operating Supply Current (Note 1) - 4 mA E = 1MHz, IO = 0mA, VCC = 5.5V,
ICCDR Data Retention Supply Current - 10 µAVCC = 2.0V, IO = 0mA, VI = VCC or
VCCDR Data Retention Supply Voltage 2.0 - V
II Input Leakage Current -1.0 +1.0 µA VI = VCC or GND, VCC = 5.5V
IIOZ Input/Output Leakage Current -1.0 +1.0 µA VIO = VCC or GND, VCC = 5.5V
VIL Input Low Voltage -0.3 0.8 V VCC = 4.5V
VIH Input High Voltage VCC -2.0 VCC +0.3 V VCC = 5.5V
VOL Output Low Voltage - 0.4 V IO = 1.6mA, VCC = 4.5V
VOH Output High Voltage 2.4 - V IO = -0.4mA, VCC = 5.5V
Capacitance T
SYMBOL PARAMETER MAX UNITS TEST CONDITIONS
= +25oC
A
= 5V ± 10%; TA = -40oC to +85oC (HM-6561B-9, HM-6561-9)
CC
LIMITS
UNITS TEST CONDITIONSMIN MAX
VCC = 5.5V
VI = VCC or GND, W = GND
GND, E = V
CC
CI Input Capacitance (Note 2) 6 pF f = 1MHz, All measurements are
CIO Input/Output Capacitance (Note 2) 10 pF
NOTES:
1. Typical derating 1.5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
referenced to device GND
6-3
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