Intersil Corporation HM-6551-883 Datasheet
HM-6551/883
March 1997
Features
• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 220ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 1 TTL Load
• Internal Latched Chip Select
• High Noise Immunity
• On-Chip Address Register
• Latched Outputs
• Three-State Output
Ordering Information
PACKAGE TEMPERA TURE RANGE 220ns 300ns PKG. NO.
CERDIP -55oC to +125oC HM-6551B/883 HM1-6551/883 F22.4
256 x 4 CMOS RAM
Description
The HM-6551/883 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous circuit design techniques are employed to achieve high performance and low power operation. On chip latches are
provided for address and data outputs allowing efficient
interfacing with microprocessor systems. The data output
buffers can be forced to a high impedance state for use in
expanded memory arrays.
The HM-6551/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
Pinout
HM-6551/883 (CERDIP)
TOP VIEW
A3
1
2
A2
A1
3
4
A0
A5
5
A6
6
A7
7
8
GND
D0
9
10
Q0
D1
11
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
S Chip Select
D Data Input
Q Data Output
VCC
22
A4
21
W
20
S1
19
E
18
S2
17
Q3
16
D3
15
Q2
14
13
D2
Q1
12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
6-101
File Number 2988.1
Functional Diagram
HM-6551/883
A0
A1
A5
A6
A7
D0
D1
D2
D3
S2
S1
LATCHED
ADDRESS
REGISTER
A
A
A
A
E
W
A
5
GATED
ROW
DECODER
A
5
L
DQ
SELECT
LATCH
32
32 x 32
MATRIX
GATED COLUMN
DECODER
AND DATA I/O
33
A A
LATCHED ADDRESS
REGISTER
A2
A3
8 888
D
D
OUTPUT
D
LATCHES
D
A4
NOTES:
1. Select Latch: L Low → Q = D and Q latches on rising edge of L.
2. Address Latches And Gated Decoders: Latch on falling edge of E and gate on falling edge of E.
3. All lines positive logic-active high.
4. Three-State Buffers: A high → output active.
5. Data Latches: L High → Q = D and Q latches on falling edge of L.
DAT A
Q
Q
Q
Q
L
Q0
A
Q1
A
Q2
A
Q3
A
6-102
HM-6551/883
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range. . . . . . . . . . . . . . . .-55oC to +125oC
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
TABLE 1. HM-6551/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
Thermal Resistance θ
CERDIP Package . . . . . . . . . . . . . . . . 60oC/W 15oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . .+175oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . .+300oC
JA
θ
JC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1930 Gates
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VCC -2.0V to VCC
Input Rise and Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max.
(NOTE 1)
PARAMETER SYMBOL
Output Low Voltage VOL VCC = 4.5V
Output High Voltage VOH VCC = 4.5V
Input Leakage Current II VCC = 5.5V,
Output Leakage
Current
Data Retention Supply
Current
Operating Supply
Current
Standby Supply
Current
NOTES:
1. All voltages referenced to device GND.
2. Typical derating 1.5mA/MHz increase in ICCOP.
IOZ VCC = 5.5 V,
ICCDR VCC = 2.0V, E = VCC
ICCOP VCC = 5.5V, (Note 2)
ICCSB VCC = 5.5V,
CONDITIONS
IOL = 1.6mA
IOH = -0.4mA
VI = GND or VCC
VO = GND or VCC
IO = 0mA,
VI = VCC or GND
E = 1MHz, IO = 0mA
VI = VCC or GND
IO = 0mA
VI = VCC or GND
GROUP A
SUBGROUPS TEMPERATURE
1, 2, 3 -55oC ≤ TA≤ +125oC - 0.4 V
1, 2, 3 -55oC ≤ TA≤ +125oC 2.4 - V
1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 +1.0 µA
1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 +1.0 µA
1, 2, 3 -55oC ≤ TA≤ +125oC- 10 µA
1, 2, 3 -55oC ≤ TA≤ +125oC- 4 mA
1, 2, 3 -55oC ≤ TA≤ +125oC- 10 µA
LIMITS
UNITSMIN MAX
6-103
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