Intersil Corporation HM-6551 Datasheet
HM-6551
March 1997
Features
• Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 220ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 1 TTL Load
• Internal Latched Chip Select
• High Noise Immunity
• On-Chip Address Register
• Latched Outputs
• Three-State Output
Ordering Information
PACKAGE TEMPERA TURE RANGE 220ns 300ns PKG. NO.
Plastic DIP -40oC to +85oC
CERDIP -40oC to +85oC HM1-6551B-9 HM1-6551-9 F22.4
Pinout
256 x 4 CMOS RAM
Description
The HM-6551 is a 256 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous
circuit design techniques are employed to achieve high
performance and low power operation.
On chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays.
The HM-6551 is a fully static RAM and may be maintained in
any state for an indefinite period of time. Data retention
supply voltage and supply current are guaranteed overtemperature.
HM3-6551B-9 HM3-6551-9 E22.4
HM-6551
(PDIP, CERDIP)
TOP VIEW
A3
1
2
A2
A1
3
4
A0
A5
5
A6
6
A7
7
8
GND
D0
9
10
Q0
D1
11
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write E5able
S Chip Select
D Data Input
Q Data Output
V
22
CC
A4
21
W
20
S1
19
E
18
S2
17
Q3
16
D3
15
Q2
14
13
D2
Q1
12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
6-1
File Number 2989.1
Functional Diagram
HM-6551
A0
A1
A5
A6
A7
D0
D1
D2
D3
S2
S1
LATCHED
ADDRESS
REGISTER
A
A
A
A
E
W
A
5
GATED
ROW
DECODER
A
5
L
DQ
SELECT
LATCH
32
32 x 32
MATRIX
GATED COLUMN
DECODER
AND DATA I/O
33
A A
LATCHED ADDRESS
REGISTER
A2
A3
8 888
D
D
OUTPUT
D
LATCHES
D
A4
NOTES:
1. Select Latch: L Low → Q = D and Q latches on rising edge of L.
2. Address Latches And Gated Decoders: Latch on falling edge of E and gate on falling edge of E.
3. All lines positive logic-active high.
4. Three-State Buffers: A high → output active.
5. Data Latches: L High → Q = D and Q latches on falling edge of L.
DAT A
Q
Q
Q
Q
L
Q0
A
Q1
A
Q2
A
Q3
A
6-2
HM-6551
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC+0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
HM-6551B-9, HM-6551-9 . . . . . . . . . . . . . . . . . . . -40oC to +85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Thermal Resistance (Typical, Note 1) θ
CERDIP Package . . . . . . . . . . . . . . . . 60oC/W 15oC/W
Plastic DIP Package . . . . . . . . . . . . . . 75oC/W N/A
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . .+300oC
JA
θ
JC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1930 Gates
DC Electrical Specifications V
SYMBOL PARAMETER
ICCSB Standby Supply Current - 10 µA IO = 0mA, VI = VCC or GND,
ICCOP Operating Supply Current (Note 1) - 4 mA E = 1MHz, IO = 0mA, VCC = 5.5V,
ICCDR Data Retention Supply Current - 10 µAVCC = 2.0V, IO = 0mA, VI = VCC or
VCCDR Data Retention Supply Voltage 2.0 - V
II Input Leakage Current -1.0 +1.0 µA VI = VCC or GND, VCC = 5.5V
IOZ Output Leakage Current -1.0 +1.0 µA VO = VCC or GND, VCC = 5.5V
VIL Input Low Voltage -0.3 0.8 V VCC = 4.5V
VIH Input High Voltage VCC -2.0 VCC +0.3 V VCC = 5.5V
VOL Output Low Voltage - 0.4 V IO = 1.6mA, VCC = 4.5V
VOH Output High Voltage 2.4 - V IO = -0.4mA, VCC = 4.5V
Capacitance T
SYMBOL PARAMETER MAX UNITS TEST CONDITIONS
= +25oC
A
= 5V ±10%; TA = -40oC to +85oC (HM-6551B-9, HM-6551-9)
CC
LIMITS
UNITS TEST CONDITIONSMIN MAX
VCC = 5.5V
VI = VCC or GND, W = GND
GND, E = V
CC
CI Input Capacitance (Note 2) 6 pF f = 1MHz, All measurements are
CO Output Capacitance (Note 2) 10 pF
NOTES:
1. Typical derating 1.5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
referenced to device GND
6-3
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