March 1997
HM-65262/883
16K x 1 Asynchronous
CMOS Static RAM
Features
• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/85ns Max
• Low Standby Current. . . . . . . . . . . . . . . . . . . .50
• Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max
• Data Retention at 2.0V. . . . . . . . . . . . . . . . . . .20µA Max
• TTL Compatible Inputs and Outputs
µA Max
Description
The HM-65262/883 is a CMOS 16384 x 1-bit Static Random Access Memory manufactured using the Intersil
Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle times and ease of use.
The HM-65262/883 is available in both JEDEC Standard 20
pin, 0.300 inch wide CERDIP and 20 pad CLCC packages,
providing high board-level packing density. Gated inputs
lower standby current, and also eliminate the need for pullup or pull-down resistors.
The HM-65262/883, a full CMOS RAM, utilizes an array of
six transistor (6T) memory cells for the most stable and
• JEDEC Approved Pinout
• No Clocks or Strobes Required
o
• Temperature Range. . . . . . . . . . . . . . . +55
C to +125oC
• Gated Inputs-No Pull-Up or Pull-Down Resistors
Required
lowest possible standby supply current over the full military
temperature range. In addition to this, the high stability of
the 6T RAM cell provides excellent protection against soft
errors due to noise and alpha particles. This stability also
improves the radiation tolerance of the RAM over that of
four transistor (4T) devices.
• Equal Cycle and Access Time
• Single 5V Supply
Ordering Information
70ns/20µA 85ns/20µA 85ns/400µA TEMP. RANGE PACKAGE PKG. NO.
- HM1-65262/883 - -55oC to +125oC CERDIP F20.3
HM4-65262B/883 HM4-65262/883 - -55oC to +125oC CLCC J20.C
Pinouts
HM1-65262/883 (CERDIP)
TOP VIEW
1
A0
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
8
Q
9
W
10
GND
VCC
20
A13
19
A12
18
A11
17
A10
16
A9
15
A8
14
A7
13
12
D
11
E
HM-65262 (CLCC)
TOP VIEW
A1A2VCC
220119
3
A3
4
A4
5
A5
6
A6
7
Q
8
9101112
W
A0
GND
A13
18
A12
A11
17
A10
16
A9
15
A8
14
A7
13
E
D
A0 - A13 Address Input
E Chip Enable/Power Down
Q Data Out
D Data In
VSS/GND Ground
VCC Power (+5)
W Write Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
6-204
File Number 3003.2
HM-65262/883
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input or Output Voltage Applied for all Grades . . . . . -0.3V to VCC +0.3V
Typical Derating Factor. . . . . . . . . . . . . . . .5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1
Thermal Resistance (Typical) θ
CERDIP Package. . . . . . . . . . . . . . . . . . 66oC/W 13oC/W
CLCC Package. . . . . . . . . . . . . . . . . . . . 75
Maximum Storage Temperature Range. . . . . . . . . . . . .-65
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . +300
JA
o
C/W 18oC/W
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26256 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage (VIH). . . . . . . . . . . . . . . . . . . . . . . . . .±2.2V to VCC
Data Retention Supply Voltage. . . . . . . . . . . . . . . . . . . 2.0V to 4.5V
Input Rise and Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . .40ns Max.
θ
JC
o
C to +150oC
o
o
C
C
Device Guaranteed and 100% Tested
DC PARAMETER SYMBOL
High Level Output Voltage VOH1 VCC = 4.5V, IO = -4.0mA 1, 2, 3 -55oC ≤ TA≤ +125oC 2.4 - V
Low Level Output Voltage VOL VCC = 4.5V, IO = 8.0mA 1, 2, 3 -55
High Impedance Output
Leakage Current
Input Leakage Current II VCC = 5.5V, VI = GND or VCC 1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 1.0 µA
Standby Supply Current ICCSB1 VCC = 5.5V, IO = 0mA,
Standby Supply Current ICCSB VCC = 5.5V, IO = 0mA, E = 2.2V 1, 2, 3 -55oC ≤ TA≤ +125oC- 5 mA
Operating Supply
Current
Data Retention Supply
Current
Enable Supply Current ICCEN VCC = 5.5V, IO = 0mA, E = 0.8V 1, 2, 3 -55oC ≤ TA≤ +125oC - 50 mA
Functional Test FT VCC = 4.5V (Note 3) 7, 8A, 8B -55
IOZ VCC = 5.5V,
or VCC
-0.3V
ICCOP VCC = 5.5V, (Note 2), f = 1MHz,
= 0.8V
ICCDR VCC = 2.0V, IO = 0mA,E = VCC
-0.3V
(NOTE 1)
CONDITIONS
E = 5.5V, VO = GND
E = VCC
GROUP A
SUB-GROUPS TEMPERATURE MIN MAX UNITS
o
C ≤ TA≤ +125oC - 0.4 V
1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 1.0 µA
1, 2, 3 -55oC ≤ TA≤ +125oC- 50 µA
E
1, 2, 3 -55oC ≤ TA≤ +125oC - 50 mA
1, 2, 3 -55oC ≤ TA≤ +125oC- 20 µA
o
C ≤ TA≤ +125oC- - -
NOTES:
1. All voltages referenced to device GND.
2. Typical derating 1.5mA/MHz increase in ICCOP.
3. Tested as follows: f = 2MHz, VIH = 2.4V, VIL = 0.4V, IOH = -4.0mA, IOL = 4.0mA, VOH ≥ 1.5V, and VOL ≤ 1.5V.
TABLE 1. HM-65262/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
AC PARAMETER SYMBOL
TABLE 2. HM-65262/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Read/Write/Cycle
Time
Address Access
Time
(1) TAVAX VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC 70 - 85 - ns
(2) TAVQV VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA≤ +125oC - 70 - 85 ns
(NOTES 1, 2)
CONDITIONS
GROUP A
SUB-
GROUPS TEMPERATURE
6-206
HM-
65262B/883
LIMITS
HM-65262/883
LIMITS
UNITSMIN MAX MIN MAX