Intersil Corporation HM-65262 Datasheet

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March 1997

HM-65262

16K x 1 Asynchronous

CMOS Static RAM

Features

• Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/85ns Max

• Low Standby Current. . . . . . . . . . . . . . . . . . . .50µA Max

• Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max

• Data Retention at 2.0V. . . . . . . . . . . . . . . . . . .20µA Max

• TTL Compatible Inputs and Outputs

• JEDEC Approved Pinout

• No Clocks or Strobes Required

• Temperature Range. . . . . . . . . . . . . . . +55

• Equal Cycle and Access Time

• Single 5V Supply

• Gated Inputs-No Pull-Up or Pull-Down Resistors Required

C to +125oC

Description

The HM-65262 is a CMOS 16384 x 1-bit Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle times and ease of use. The HM-65262 is available in both JEDEC standard 20 pin, 0.300 inch wide CERDIP and 20 pad CLCC packages, providing high boardlevel packing density. Gated inputs lower standby current, and also eliminate the need for pull-up or pull-down resistors.

The HM-65262, a full CMOS RAM, utilizes an array of six transistor (6T) memory cells for the most stable and lowest possible standby supply current over the full military temperature range. In addition to this, the high stability of the 6T RAM cell provides excellent protection against soft errors due to noise and alpha particles. This stability also improves the radiation tolerance of the RAM over that of four transistor (4T) devices.

Ordering Information

(NOTE 1)

PACKAGE TEMP. RANGE 70ns/20µA (NOTE 1) 85ns/20µA (NOTE 1)

CERDIP -40oC to +85oC HM1-65262B-9 HM1-65262-9 - F20.3

JAN # -55oC to +125oC 29109BRA 29103BRA - F20.3

85ns/400µA PKG. NO.

SMD# -55oC to +125oC 8413203RA 8413201RA - F20.3

CLCC (SMD#) -55oC to +125oC 8413203YA 8413201YA - J20.C

NOTE:

1. Access Time/Data Retention Supply Current.

Pinouts

HM-65262 (CERDIP)

TOP VIEW

A0 A1

7 8

GND

A13

A12

A11

A10

13 12

HM-65262 (CLCC)

TOP VIEW

A1A2VCCA13

220119

9101112

GND

A12 A11

A10

A0 - A13 Address Input

E Chip Enable/Power Down Q Data Out D Data In

VSS/GND Ground

W Write Enable

Power (+5)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207

6-1

File Number 3002.2

Functional Diagram

HM-65262

A0 A1 A2 A3 A4

A12 A13

ROW

ADDRESS

BUFFER

DECODER (1 OF 128)

ROW

MEMORY ARRAY

128

128 X 128

128

COLUMN DECODER

(1 OF 128)

AND I / O CIRCUITRY

COLUMN

ADDRESS BUFFERS

A7A6A8

A10

A11

6-2

HM-65262

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V

Input or Output Voltage Applied for all grades . . . . . -0.3V to V

Typical Derating Factor. . . . . . . . . . . . . . . .5mA/MHz Increase in ICCOP

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

+0.3V

Thermal Resistance (Typical) θ

CERDIP Package. . . . . . . . . . . . . . . . . . 66oC/W 13oC/W

CLCC Package. . . . . . . . . . . . . . . . . . . . 75

Maximum Storage Temperature Range. . . . . . . . . . . . . -65

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . +300

C/W 18oC/W

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26256 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range

HM-65262B-9, HM-65262-9, HM-65262C-9 . . . . .-40oC to +85oC

C to +150oC

o o

C C

DC Electrical Speciﬁcations V

= 5V ±10%; TA = -40oC to +85oC (HM-65262B-9, HM-65262-9, HM-65262C-9)

LIMITS

SYMBOL PARAMETER

UNITS TEST CONDITIONSMIN MAX

ICCSB1 Standby Supply Current -od 50 µA HM-65262B-9, HM-65262-9, IO = 0mA,

E = VCC -0.3V, VCC = 5.5V

- 900 µA HM-65262C-9, IO = 0mA, E = VCC -0.3V, VCC = 5.5V

ICCSB Standby Supply Current - 5 mA E = 2.2V, IO = 0mA, VCC = 5.5V ICCEN Enabled Supply Current - 50 mA E = 0.8V, IO = 0mA, VCC = 5.5V ICCOP Operating Supply Current (Note 1) - 50 mA E = 0.8V, IO = 0mA, f = 1MHz,

VCC = 5.5V

ICCDR Data Retention Supply Current - 20 µA HM-65262B-9, HM-65262-9,

VCC = 2.0V, E = V

- 400 µA HM-65262C-9, VCC = 2.0V, E = V

ICCDR1 Data Retention Supply Current - 30 µA HM-65262B-9, HM-65262-9,

VCC = 3.0V, E = V

- 550 µA HM-65262C-9, VCC = 3.0V, E = V

VCCDR Data Retention Supply Voltage 2.0 - V

II Input Leakage Current -1.0 +1.0 µA VI = VCC or GND, VCC = 5.5V

IOZ Output Leakage Current -1.0 +1.0 µA VIO = VCC or GND, VCC = 5.5V

VIL Input Low Voltage -0.3 0.8 V VCC = 4.5V

VIH Input High Voltage 2.2 VCC +0.3 V VCC = 5.5V

VOL Output Low Voltage - 0.4 V IO = 8.0mA, VCC = 4.5V VOH1 Output High Voltage 2.4 - V IO = -4.0mA, VCC = 4.5V VOH2 Output High Voltage (Note 2) VCC -0.4 - V IO = -100µA, VCC = 4.5V

Capacitance T

= +25oC

SYMBOL PARAMETER MAX UNITS TEST CONDITIONS

CI Input Capacitance (Note 2) 10 pF f = 1MHz, All measurements are

CIO Input/Output Capacitance (Note 2) 12 pF

referenced to device GND

NOTES:

1. Typical derating 5mA/MHz increase in ICCOP.

2. Tested at initial design and after major design changes.

6-3

HM-65262

AC Electrical Speciﬁcations V

SYMBOL PARAMETER

READ CYCLE

(1) TAVAX Read/Cycle Time 70 - 85 - 85 - ns (2) TAVQV Address Access Time - 70 - 85 - 85 ns (3) TELQV Chip Enable Access Time - 70 - 85 - 85 ns (4) TELQX Chip Enable Output Enable

(5)

TEHQX

(6) TAXQX Address Invalid Output Hold

(7) TEHQZ Chip Enable Output Disable

Time Chip Disable Output Hold

Time

= 5V 10%,TA = -40oC to +85oC (HM-65262B-9, HM-65262-9, HM-65262C-9)

LIMITS

HM-65262B-9 HM-65262-9

MIN MAX MIN MAX MIN MAX

5-5-5-ns

-30-30-30ns

HM-65262C-9

UNITS

TEST

CONDITIONS

(Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 2, 3)

(Notes 2, 3)

WRITE CYCLE

(8) TAVAX Write Cycle Time 70 - 85 - 85 - ns (9) TELWH Chip Selection to End of

Write (10) TWLWH Write Enable Pulse Width 40 - 45 - 45 - ns (11) TAVWL Address Setup Time 0 - 0 - 0 - ns (12) TWHAX Address Hold Time 0 - 0 - 0 - ns (13) TDVWH Data Setup Time 30 - 35 - 35 - ns (14) TWHDX Data Hold Time 0 - 0 - 0 - ns (15) TWLQZ Write Enable Output Disable

Time (16) TWHQX Write Disable Output Enable

Time (17) TAVWH Address Valid to End of Write 55 - 65 - 65 - ns (18) TAVEL Address Setup Time 0 - 0 - 0 - ns (19) TEHAX Address Hold Time 0 - 0 - 0 - ns (20) TAVEH Address Valid to End of Write 55 - 65 - 65 - ns (21) TELEH Enable Pulse Width 55 - 65 - 65 - ns (22) TWLEH Write Enable Pulse Setup

Time (23) TDVEH Chip Setup Time 30 - 35 - 35 0 ns (24) TEHDX Data Hold Time 0 - 0 - 0 - ns

55 - 65 - 65 - ns

-30-30-30ns

0-0-0-ns

40 - 45 - 45 - ns

(Notes 1, 3) (Notes 1, 3)

(Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 2, 3)

(Notes 2, 3)

(Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3)

(Notes 1, 3) (Notes 1, 3)

NOTES:

1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference lev el: 1.5V; Output load: 1 TTL gate equivalent and CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.

2. Tested at initial design and after major design changes.

3. VCC = 4.5 and 5.5V.

6-4

Timing Waveforms

HM-65262

(4) TELQX

(3) TELQV

(7) TEHQZ

(5) TEHQX

NOTE:

1. W is high for entire cycle and D is ignored. Address is stable by the time E goes low and remains valid until E goes high.

FIGURE 1. READ CYCLE 1: CONTROLLED BY E

(1) TAVAX

(2) TAVQV

(4) TELQX

(7) TEHQZ

(6) TAXQX

NOTE:

1. W is high for the entire cycle and D is ignored. E is stable prior to A becoming valid and after A becomes invalid.

FIGURE 2. READ CYCLE 2: CONTROLLED BY ADDRESS

(8) TAVAX

(17) TAVWH

(11)

TAVWL

(4)

TELQX

(9) TELWH

(10) TWLWH

(13) TDVWH

(15) TWLQZ

(12) TWHAX

(14) TWHDX

(16) TWHQX

NOTE:

1. In this mode, E rises after W. The address must remain stable whenever both E and W are low.

FIGURE 3. WRITE CYCLE 1: CONTROLLED BY W (LATE WRITE)

(7) TEHQZ

6-5

HM-65262

Timing Waveforms

(18) TAVEL

(Continued)

(8) TAVAX

(20) TAVEH

(21) TELEH

(22) TWLEH

(23) TDVEH

(4) TELQX

(15) TWLQZ (7) TEHQZ

(19) TEHAX

(24)

TEHDX

(16) TWHQX

NOTE:

1. In this mode, W rises after E. If W falls beforeE by a time exceeding TWLQZ (Max) TELQX (Min), and rises afterE by a time exceeding TEHQZ (Max) TWHQZ (Min), then Q will remain in the high impedance state throughout the cycle.

FIGURE 4. WRITE CYCLE 2: CONTROLLED BY E (EARLY WRITE)

Low Voltage Data Retention

Intersil CMOS RAMs are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention:

1. Chip Enable ( within V

E) must be held high during data retention;

to VCC +0.3V.

2. On RAMs which have selects or output enables (e.g., S, G), one of the selects or output enables should be held in

DATA RETENTION

MODE

4.5V

VCC≥ 2.0V

VCC -0.3V TO VCC +0.3V

the deselected state to keep the RAM outputs high impedance, minimizing power dissipation.

3. Inputs which are to be held high (e.g., between V

+0.3V and 70% of VCC during the power

E) must be kept

up and down transitions.

4. The RAM can begin operation > 55ns after V

reaches

the minimum operating voltage (4.5V).

4.5V

>55ns

FIGURE 5. DATA RETENTION TIMING

6-6

Typical Performance Curve

-3

-4

-5

-6

/(1A))

-7

-8

-9

LOGIC (I

-10

-11

-12

HM-65262

= 2.0V

-55 -35 -15 5 25 45 65 85 105 125 TA (oC)

FIGURE 6. TYPICAL ICCDR vs T

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil products are sold by description only. Intersil Cor poration reserves the right to make changes in circuit design and/or speciﬁcations at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Ofﬁce Headquarters

NORTH AMERICA

Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240

EUROPE

Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05

6-7

ASIA

Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029

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