Intersil Corporation HM-65262 Datasheet

March 1997

HM-65262

16K x 1 Asynchronous

CMOS Static RAM

Features

• Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/85ns Max

• Low Standby Current. . . . . . . . . . . . . . . . . . . .50µA Max

• Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max

• Data Retention at 2.0V. . . . . . . . . . . . . . . . . . .20µA Max

• TTL Compatible Inputs and Outputs

• JEDEC Approved Pinout

• No Clocks or Strobes Required

• Temperature Range. . . . . . . . . . . . . . . +55

• Equal Cycle and Access Time

• Single 5V Supply

• Gated Inputs-No Pull-Up or Pull-Down Resistors
Required

o

C to +125oC

Description

The HM-65262 is a CMOS 16384 x 1-bit Static Random
Access Memory manufactured using the Intersil Advanced
SAJI V process. The device utilizes asynchronous circuit
design for fast cycle times and ease of use. The HM-65262
is available in both JEDEC standard 20 pin, 0.300 inch wide
CERDIP and 20 pad CLCC packages, providing high board­level packing density. Gated inputs lower standby current,
and also eliminate the need for pull-up or pull-down resis­tors.

The HM-65262, a full CMOS RAM, utilizes an array of six
transistor (6T) memory cells for the most stable and lowest
possible standby supply current over the full military temper­ature range. In addition to this, the high stability of the 6T
RAM cell provides excellent protection against soft errors
due to noise and alpha particles. This stability also improves
the radiation tolerance of the RAM over that of four transistor
(4T) devices.

Ordering Information

(NOTE 1)

PACKAGE TEMP. RANGE 70ns/20µA (NOTE 1) 85ns/20µA (NOTE 1)

CERDIP -40oC to +85oC HM1-65262B-9 HM1-65262-9 - F20.3

JAN # -55oC to +125oC 29109BRA 29103BRA - F20.3

85ns/400µA PKG. NO.

SMD# -55oC to +125oC 8413203RA 8413201RA - F20.3

CLCC (SMD#) -55oC to +125oC 8413203YA 8413201YA - J20.C

NOTE:

1. Access Time/Data Retention Supply Current.

Pinouts

HM-65262 (CERDIP)

TOP VIEW

1

A0
A1

2

A2

3

A3

4

A4

5

A5

6

A6

7
8

Q

9

W

10

GND

V

20

CC

A13

19

A12

18

A11

17

A10

16

A9

15

A8

14

A7

13
12

D

11

E

HM-65262 (CLCC)

TOP VIEW

A1A2VCCA13

220119

3

A3

4

A4

5

A5

6

A6

7

Q

8

9101112

W

A0

GND

18

A12
A11

17

A10

16

A9

15

A8

14

A7

13

E

D

A0 - A13 Address Input

E Chip Enable/Power Down
Q Data Out
D Data In

VSS/GND Ground

V

CC

W Write Enable

Power (+5)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

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File Number 3002.2

Functional Diagram

HM-65262

A0
A1
A2
A3
A4

A12
A13

A

ROW

ADDRESS

BUFFER

D

E

W

7

DECODER
(1 OF 128)

A

7

ROW

MEMORY ARRAY

128

128 X 128

128

COLUMN DECODER

(1 OF 128)

AND I / O CIRCUITRY

A

A

7

COLUMN

ADDRESS BUFFERS

A7A6A8

A9

A10

A11

Q

7

A5

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HM-65262

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V

Input or Output Voltage Applied for all grades . . . . . -0.3V to V

Typical Derating Factor. . . . . . . . . . . . . . . .5mA/MHz Increase in ICCOP

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CC

+0.3V

Thermal Resistance (Typical) θ

CERDIP Package. . . . . . . . . . . . . . . . . . 66oC/W 13oC/W

CLCC Package. . . . . . . . . . . . . . . . . . . . 75

Maximum Storage Temperature Range. . . . . . . . . . . . . -65

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . +300

JA

o

C/W 18oC/W

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26256 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range

HM-65262B-9, HM-65262-9, HM-65262C-9 . . . . .-40oC to +85oC

θ

JC

o

C to +150oC

o
o

C
C

DC Electrical Specifications V

= 5V ±10%; TA = -40oC to +85oC (HM-65262B-9, HM-65262-9, HM-65262C-9)

CC

LIMITS

SYMBOL PARAMETER

UNITS TEST CONDITIONSMIN MAX

ICCSB1 Standby Supply Current -od 50 µA HM-65262B-9, HM-65262-9, IO = 0mA,

E = VCC -0.3V, VCC = 5.5V

- 900 µA HM-65262C-9, IO = 0mA,
E = VCC -0.3V, VCC = 5.5V

ICCSB Standby Supply Current - 5 mA E = 2.2V, IO = 0mA, VCC = 5.5V
ICCEN Enabled Supply Current - 50 mA E = 0.8V, IO = 0mA, VCC = 5.5V
ICCOP Operating Supply Current (Note 1) - 50 mA E = 0.8V, IO = 0mA, f = 1MHz,

VCC = 5.5V

ICCDR Data Retention Supply Current - 20 µA HM-65262B-9, HM-65262-9,

VCC = 2.0V, E = V

CC

- 400 µA HM-65262C-9, VCC = 2.0V, E = V

ICCDR1 Data Retention Supply Current - 30 µA HM-65262B-9, HM-65262-9,

VCC = 3.0V, E = V

CC

- 550 µA HM-65262C-9, VCC = 3.0V, E = V

VCCDR Data Retention Supply Voltage 2.0 - V

II Input Leakage Current -1.0 +1.0 µA VI = VCC or GND, VCC = 5.5V

IOZ Output Leakage Current -1.0 +1.0 µA VIO = VCC or GND, VCC = 5.5V

VIL Input Low Voltage -0.3 0.8 V VCC = 4.5V

VIH Input High Voltage 2.2 VCC +0.3 V VCC = 5.5V

VOL Output Low Voltage - 0.4 V IO = 8.0mA, VCC = 4.5V
VOH1 Output High Voltage 2.4 - V IO = -4.0mA, VCC = 4.5V
VOH2 Output High Voltage (Note 2) VCC -0.4 - V IO = -100µA, VCC = 4.5V

CC

CC

Capacitance T

= +25oC

A

SYMBOL PARAMETER MAX UNITS TEST CONDITIONS

CI Input Capacitance (Note 2) 10 pF f = 1MHz, All measurements are

CIO Input/Output Capacitance (Note 2) 12 pF

referenced to device GND

NOTES:

1. Typical derating 5mA/MHz increase in ICCOP.

2. Tested at initial design and after major design changes.

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