Intersil Corporation HM-6518-883 Datasheet

HM-6518/883

March 1997

Features

• This Circuit is Processed in Accordance to MIL-STD­883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.

• Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max

• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max

• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max

• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min

• TTL Compatible Input/Output

• High Output Drive - 2 TTL Loads

• High Noise Immunity

• On-Chip Address Register

• Two-Chip Selects for Easy Array Expansion

• Three-State Output

Pinout

1024 x 1 CMOS RAM

Description

The HM-6518/883 is a 1024 x 1 static CMOS RAM
fabricated using self-aligned silicon gate technology.
Synchronous circuit design techniques are employed to
achieve high performance and low power operation.

On chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays.

The HM-6518/883 is a fully static RAM and may be
maintained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.

Ordering Information

PART

PACKAGE TEMP. RANGE

CERDIP -55oC to +125oC HM1-6518/883 F18.3

NUMBER PKG. NO.

HM-6518/883

(CERDIP)

TOP VIEW

1

S1

2

E

A0

3
4

A1
A2

5

A3

6

A4

7

Q

8

GND

9

PIN DESCRIPTION

A Address Input
E Chip Enable

W Write Enable

S Chip Select
D Data Input

18

VCC

17

S2

16

D

15

W

14

A9

13

A8

12

A7
A6

11

A5

10

Q Data Output

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

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File Number 2986.1

Functional Diagram

HM-6518/883

A5
A6
A7
A8
A9

S1,
S2

LATCHED
ADDRESS

REGISTER

D

W

E

A

5

A

5

GATED

ROW

DECODER

G

A

32 x 32

32

MATRIX

GATED COLUMN

DECODER

AND DATA I/O

55

A A

LATCHED ADDRESS

REGISTER

32

NOTES:

1. All lines positive logic - active high.

2. Three-state buffers: A high → output active.

3. Data latches: L high → Q = D; Q Latches on rising edge of L.

4. Address latches and gated decoders: Latch on falling edge of E and gate on falling edge of E.

D

LATCH

A4A3A2A1A0

Q

L

Q

A

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HM-6518/883

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating Conditions

Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range. . . . . . . . . . . . . . . .-55oC to +125oC

Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V

Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . .VCC -2.0V to VCC

Input Rise and Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . .40ns Max

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

TABLE 1. HM-6518/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS

Device Guaranteed and 100% Tested

(NOTE 1)

PARAMETER SYMBOL

CONDITIONS

Thermal Resistance (Typical, Note 1) θ

CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W

Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . .+175oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . .+300oC

JA

θ

JC

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1936 Gates

LIMITS

GROUP A

SUBGROUPS TEMPERATURE

UNITSMIN MAX

Output Low Voltage VOL VCC = 4.5V,

IOL = 3.2mA

Output High Voltage VOH VCC = 4.5V,

IOH = -0.4mA

Input Leakage Current II VCC = 5.5V,

VI = GND or VCC

Output Leakage Current IOZ VCC = 5.5V,

VO = GND or VCC

Data Retention Supply Current ICCDR VCC = 2.0V,

E = VCC,
IO = 0mA,

HM-6518/883 -10µA

Operating Supply Current ICCOP VCC = 5.5V,

Standby Supply Current ICCSB VCC = 5.5V,

NOTES:

1. All voltages referenced to device GND.

2. Typical derating 1.5mA/MHz increase in ICCOP.

VI = VCC or GND

(Note 2),
E = 1MHz,
IO = 0mA,
VI = VCC or GND

IO = 0mA,
VI = VCC or GND

1, 2, 3 -55oC ≤ TA≤ +125oC - 0.4 V

1, 2, 3 -55oC ≤ TA≤ +125oC 2.4 - V

1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 +1.0 µA

1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 +1.0 µA

1, 2, 3 -55oC ≤ TA≤ +125oC

-5µAHM-6518B/883

1, 2, 3 -55oC ≤ TA≤ +125oC- 4 mA

1, 2, 3 -55oC ≤ TA≤ +125oC- 10 µA

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