Intersil Corporation HM-6518 Datasheet
HM-6518
March 1997
Features
• Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . .at 2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 2 TTL Loads
• High Noise Immunity
• On-Chip Address Register
• Two-Chip Selects for Easy Array Expansion
• Three-State Output
Ordering Information
PACKAGE TEMP. RANGE 180ns 250ns PKG. NO.
CERDIP -40oC to +85oC HM1-
6518B-9
HM16518-9
F18.3
1024 x 1 CMOS RAM
Description
The HM-6518 is a 1024 x 1 static CMOS RAM fabricated
using self-aligned silicon gate technology. Synchronous
circuit design techniques are employed to achieve high
performance and low power operation.
On chip latches are provided for address and data outputs
allowing efficient interfacing with microprocessor systems.
The data output buffers can be forced to a high impedance
state for use in expanded memory arrays.
The HM-6518 is a fully static RAM and may be maintained in
any state for an indefinite period of time. Data retention
supply voltage and supply current are guaranteed overtemperature.
Pinout
HM-6518
(CERDIP)
TOP VIEW
1
S1
2
E
A0
3
4
A1
A2
5
A3
6
A4
7
Q
8
GND
9
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
S Chip Select
D Data Input
Q Data Output
18
V
CC
17
S2
16
D
15
W
14
A9
13
A8
12
A7
A6
11
A5
10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
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File Number 2987.1
Functional Diagram
HM-6518
A5
A6
A7
A8
A9
S1,
S2
LATCHED
ADDRESS
REGISTER
D
W
E
A
5
A
5
GATED
ROW
DECODER
G
A
32 x 32
32
MATRIX
GATED COLUMN
DECODER
AND DATA I/O
55
AA
LATCHED ADDRESS
REGISTER
32
NOTES:
1. All lines positive logic - active high.
2. Three-state buffers: A high → output active.
3. Data latches: L high → Q = D; Q Latches on rising edge of L.
4. Address latches and gated decoders: Latch on falling edge of E and gate on falling edge of E.
D
LATCH
A4A3A2A1A0
Q
L
Q
A
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HM-6518
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC+0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
HM-6518B-9, HM-6518-9 . . . . . . . . . . . . . . . . . . . -40oC to +85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Thermal Resistance (Typical, Note 1) θ
CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . .+175oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . .+300oC
JA
θ
JC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1936 Gates
DC Electrical Specifications V
PARAMETER SYMBOL
Standby Supply Current ICCSB - 10 µA IO = 0mA, VI = VCC or GND,
Operating Supply
Current (Note 1)
Data Retention Supply
Current
Data Retention Supply Voltage VCCDR 2.0 - V
Input Leakage Current II -1.0 +1.0 µA VI = VCC or GND, VCC = 5.5V
Output Leakage Current IOZ -1.0 +1.0 µA VO = VCC or GND, VCC = 5.5V
Input Low Voltage VIL -0.3 0.8 V VCC = 4.5V
Input High Voltage VIH VCC -2.0 VCC +0.3 V VCC = 5.5V
Output Low Voltage VOL - 0.4 V IO = 3.2mA, VCC = 4.5V
Output High Voltage VOH 2.4 - V IO = -0.4mA, VCC = 4.5V
Capacitance T
A
PARAMETER SYMBOL MAX UNITS TEST CONDITIONS
HM-6518B-9 ICCDR - 5 µAVCC = 2.0V, IO = 0mA, VI = VCC or
HM-6518-9 - 10 µA
= +25oC
= 5V ±10%; TA = -40oC to +85oC (HM-6518B-9, HM-6518-9)
CC
LIMITS
UNITS TEST CONDITIONSMIN MAX
ICCOP - 4 mA E = 1MHz, IO = 0mA, VI =VCC or
VCC = 5.5V
GND, VCC = 5.5V
GND, E = V
CC
Input Capacitance (Note 2) CI 6 pF f = 1MHz, All measurements are
Output Capacitance (Note 2) CO 10 pF
NOTES:
1. Typical derating 1.5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
referenced to device GND
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