March 1997
HM-65162/883
2K x 8 Asynchronous
CMOS Static RAM
Features
• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/90ns Max
• Low Standby Current. . . . . . . . . . . . . . . . . . . .50µA Max
• Low Operating Current . . . . . . . . . . . . . . . . . 70mA Max
• Data Retention at 2.0V. . . . . . . . . . . . . . . . . . .20µA Max
• TTL Compatible Inputs and Outputs
• JEDEC Approved Pinout (2716, 6116 Type)
• No Clocks or Strobes Required
o
• Wide Temperature Range . . . . . . . . . . -55
C to +125oC
Description
The HM-65162/883 is a CMOS 2048 x 8 Static Random
Access Memory manufactured using the Intersil Advanced
SAJI V process. The device utilizes asynchronous circuit
design for fast cycle time and ease of use. The pinout is the
JEDEC 24 pin DIP, and 32 pad 8-bit wide standard which
allows easy memory board layouts flexible to accommodate
a variety of industry standard PROMs, RAMs, ROMs and
EPROMs. The HM-65162/883 is ideally suited for use in
microprocessor based systems with its 8-bit word length
organization. The convenient output enable also simplifies
the bus interface by allowing the data outputs to be
controlled independent of the chip enable. Gated inputs
lower operating current and also eliminate the need for pullup or pull-down resistors.
• Equal Cycle and Access Time
• Single 5V Supply
• Gated Inputs
- No Pull-Up or Pull-Down Resistors Required
Ordering Information
70ns/20µA 90ns/40µA 90ns/300µA TEMP. RANGE PACKAGE PKG. NO.
HM1-65162B/883 HM1-65162/883 HM1-65162C/883 -55oC to 125oC CERDIP F24.6
HM4-65162B/883 HM4-65162/883 - -55oC to 125oC CLCC J32.A
Pinouts
HM-65162/883 (CERDIP)
TOP VIEW
A7
1
A6
2
A5
3
A4
4
A3
5
A2
6
A1
7
A0
8
DQ0
9
DQ1
10
DQ2
11
GND
12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
24
VCC
23
A8
22
A9
21
W
20
G
19
A10
18
E
17
DQ7
16
DQ6
15
DQ5
14
DQ4
13
DQ3
A6
A5
A4
A3
A2
A1
A0
NC
DQ0
| Copyright © Intersil Corporation 1999
HM-65162/883 (CLCC)
TOP VIEW
NC
A7
4 32 31 30
5
6
7
8
9
10
11
12
13
14
NC
NC
3 2
16 17 18 19 20
15
DQ1
DQ2
GND
1
NC
6-188
VCC
DQ3
NC
DQ4
NC
DQ5
29
A8
28
A9
27
NC
26
W
25
G
24
A10
23
E
22
DQ7
21
DQ6
PIN DESCRIPTION
NC No Connect
A0 - A10 Address Input
E Chip Enable/Power Down
VSS/GND Ground
DQ0 - DQ7 Data In/Data Out
VCC Power (+5V)
W Write Enable
G Output Enable
File Number 3001.1
HM-65162/883
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
Typical Derating Factor . . . . . . . . . .1.5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
CAUTION: Stresses abov e those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . .-55oC to +125oC
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Chip Enable High/Low Time. . . . . . . . . . . . . . . . . . . . . . . 40ns (Min)
TABLE 1. 65162/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
(NOTE 1)
PARAMETER SYMBOL
High Level Output Voltage
Low Level Output
Voltage
High Impedance
Output Leakage
Current
Input Leakage
Current
Standby Supply
Current
Standby Supply
Current
Operating Supply
Current
Enable Supply
Current
Data Retention
Supply Current
Functional Test FT VCC = 4.5V (Note 3) 7, 8A, 8B -55
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1
TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
VOH1 VCC = 4.5V, IO = -1.0mA 1, 2, 3 -55
VOL VCC = 4.5V, IO = 4.0mA 1, 2, 3 -55
IIOZ VCC = 5.5V,
E = 2.2V, VI/O = GND or VCC
II VCC = 5.5V,
VI = GND or VCC
ICCSB1 HM-65162B/883, IO = 0mA,
VCC = 5.5V,
HM-65162/883, IO = 0mA,
VCC = 5.5V,
HM-65162C/883, IO = 0mA,
VCC = 5.5V,
ICCSB VCC = 5.5V, IO = 0mA,
E = 2.2V
ICCOP VCC = 5.5V,
(Note 2), f = 1MHz, E = 0.8V
ICCEN VCC = 5.5V, IO = 0mA,
E = 0.8V
ICCDR HM-65162B/883, IO = 0mA,
VCC = 2.0V,
HM-65162/883, IO = 0mA,
VCC = 2.0V,
HM-65162C/883, IO = 0mA,
VCC = 2.0V,
CONDITIONS
G = 2.2V, or
E = VCC -0.3V
E = VCC - 0.3V
E = VCC - 0.3V
G = 5.5V,
E = VCC - 0.3V
E = VCC - 0.3V
E = VCC - 0.3V
Thermal Resistance θ
CERDIP Package . . . . . . . . . . . . . . . . 48oC/W 8oC/W
CLCC Package . . . . . . . . . . . . . . . . . . 66oC/W 12oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
JA
θ
JC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26000 Gates
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to VCC
Data Retention Supply Voltage. . . . . . . . . . . . . . . . . . . 2.0V to 4.5V
Input Rise and Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max
GROUP A
SUBGROUPS TEMPERATURE
o
C ≤ TA≤ +125oC 2.4 - V
o
C ≤ TA≤ +125oC - 0.4 V
1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 1.0 µA
o
1, 2, 3 -55
1, 2, 3 -55oC ≤ TA≤ +125oC - 50 µA
1, 2, 3 -55oC ≤ TA≤ +125oC - 100 µA
1, 2, 3 -55oC ≤ TA≤ +125oC - 900 µA
1, 2, 3 -55oC ≤ TA≤ +125oC- 8 mA
1, 2, 3 -55oC ≤ TA≤ +125oC - 70 mA
1, 2, 3 -55oC ≤ TA≤ +125oC - 70 mA
1, 2, 3 -55oC ≤ TA≤ +125oC- 20µA
1, 2, 3 -55oC ≤ TA≤ +125oC- 40µA
1, 2, 3 -55oC ≤ TA≤ +125oC - 300 µA
C ≤ TA≤ +125oC -1.0 1.0 µA
o
C ≤ TA≤ +125oC- - -
LIMITS
UNITSMIN MAX
6-190