Intersil Corporation HM-6514-883 Datasheet

HM-6514/883

March 1997

Features

• This Circuit is Processed in Accordance to MIL-STD­883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.

• Low Power Standby. . . . . . . . . . . . . . . . . . . 125µW Max

• Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max

• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min

• TTL Compatible Input/Output

• Common Data Input/Output

• Three-State Output

• Standard JEDEC Pinout

• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max

• 18 Pin Package for High Density

• Gated Inputs - No Pull Up or Pull Down Resistors
Required

• On-Chip Address Register

Ordering Information

120ns 200ns 300ns TEMPERATURE RANGE PACKAGE PKG. NO.

HM1-6514S/883 HM1-6514B/883 HM1-6514/883 -55oC to 125oC CERDIP F18.3

1024 x 4 CMOS RAM

Description

The HM-6514/883 is a 1024 x 4 static CMOS RAM fabri­cated using self-aligned silicon gate technology. The device
utilizes synchronous circuitry to achieve high performance
and low power operation.

On chip latches are provided for addresses allowing efficient
interfacing with microprocessor systems. The data output
can be forced to a high impedance state for use in expanded
memory arrays.

Gated inputs allow lower operating current and also eliminates
the need for pull up or pull down resistors. The HM-6514/883 is
fully static RAM and may be maintained in any state for an
indefinite period of time.

Data retention supply voltage and supply current are guaran­teed over temperature.

Pinout

HM-6514/883

(CERDIP)

TOP VIEW

1

A6

2

A5

3

A4

4

A3

5

A0

6

A1

7

A2

8

E

9

GND

PIN DESCRIPTION

A Address Input
E Chip Enable

W Write Enable

D Data Input
Q Data Output

18

VCC

17

A7

16

A8

15

A9

14

DQ0

13

DQ1

12

DQ2

11

DQ3

10

W

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

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File Number 2996.1

Functional Diagram

HM-6514/883

LSB

LSB

A9
A8
A7
A6
A5
A4

A2
A1
A0
A3

A

LATCHED

ADDRESS

REGISTER

L
L

LATCHED

ADDRESS

REGISTER

E

W

6

A

6

A

4

A

4

GATED

ROW

DECODER

G

64

16 16 16 16

I/O SELECT

G

64 x 64

MATRIX

GATED

COLUMN

4

1 OF 4

DQ

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HM-6514/883

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions

Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range. . . . . . . . . . . . . . . .-55oC to +125oC

Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V

TABLE 1. HM-6514/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS

Device Guaranteed and 100% Tested

(NOTE 1)

PARAMETER SYMBOL

CONDITIONS

Thermal Resistance θ

CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W

Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . .+175oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . .+300oC

JA

θ

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6910 Gates

Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VCC -2.0V to VCC

Input Rise and Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max

GROUP A

SUBGROUPS TEMPERATURE

LIMITS

UNITSMIN MAX

JC

Output Low Voltage VOL VCC = 4.5V

IOL = 3.2mA

Output High Voltage VOH VCC = 4.5V

IOH = -1.0mA

Input Leakage Current II VCC = 5.5V,

VI = GND or VCC

Input/Output Leakage
Current

Data Retention Supply
Current

Operating Supply
Current

Standby Supply
Current

NOTES:

1. All voltages referenced to device GND.

2. Typical derating 1.5mA/MHz increase in ICCOP.

IIOZ VCC = 5.5 V,

VIO = GND or VCC

ICCDR VCC = 2.0V,

E = VCC -0.3V,
IO = 0mA

ICCOP VCC = 5.5V, (Note 2)

E = 1MHz

ICCSB VCC = 5.5V,

E = VCC-0.3V,
IO = 0mA

1, 2, 3 -55oC ≤ TA≤ +125oC - 0.4 V

1, 2, 3 -55oC ≤ TA≤ +125oC 2.4 - V

1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 +1.0 µA

1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 +1.0 µA

1, 2, 3 -55oC ≤ TA≤ +125oC- 25 µA

1, 2, 3 -55oC ≤ TA≤ +125oC- 7 mA

1, 2, 3 -55oC ≤ TA≤ +125oC- 50 µA

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