Intersil Corporation HM-6508-883 Datasheet
HM-6508/883
March 1997
Features
• This Circuit is Processed in Accordance to
MIL-STD-883 and is Fully Conformant Under the Pro visions of Paragraph 1.2.1.
• Low Power Standby. . . . . . . . . . . . . . . . . . . . 50µW Max
• Low Power Operation . . . . . . . . . . . . . 20mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 180ns Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . .2.0V Min
• TTL Compatible Input/Output
• High Output Drive - 2 TTL Loads
• On-Chip Address Register
Ordering Information
PACKAGE TEMP. RANGE 180ns 250ns PKG. NO.
CERDIP -55oC to +125oC HM1-
6508B/883
HM16508/883
F16.3
1024 x 1 CMOS RAM
Description
The HM-6508/883 is a 1024 x 1 static CMOS RAM
fabricated using self-aligned silicon gate technology.
Synchronous circuit design techniques are employed to
achieve high performance and low power operation.
On chip latches are provided for address allowing efficient
interfacing with microprocessor systems. The data output
buffers can be forced to a high impedance state for use in
expanded memory arrays.
The HM-6508/883 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data
retention supply voltage and supply current are guaranteed
over temperature.
Pinout
HM1-6508/883
(CERDIP)
TOP VIEW
E
1
A0
2
A1
3
A2
4
A3
5
A4
6
Q
7
GND
8
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
D Data Input
16
VCC
15
D
14
W
13
A9
12
A8
11
A7
10
A6
9
A5
Q Data Output
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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| Copyright © Intersil Corporation 1999
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File Number 2985.1
Functional Diagram
HM-6508/883
A5
A6
A7
A8
A9
LATCHED
ADDRESS
REGISTER
D
W
E
A
5
A
5
GATED
ROW
DECODER
A
32 x 32
32
MATRIX
GATED COLUMN
DECODER
AND DATA I/O
55
A A
LATCHED ADDRESS
REGISTER
32
NOTES:
1. All lines positive logic - active high.
2. Three-state buffers: A high → output active.
3. Address latches and gated decoders: Latch on falling edge of E and gate on falling edge of E.
Q
A
A4A3A2A1A0
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HM-6508/883
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
Typical Derating Factor. . . . . . . . . . .1.5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . .VCC -2.0V to VCC
Input Rise and Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
TABLE 1. HM-6508/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
(NOTE 1)
PARAMETER SYMBOL
CONDITIONS
Thermal Resistance (Typical, Note 1) θ
CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
JA
θ
JC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1925 Gates
LIMITS
GROUP A
SUBGROUPS TEMPERATURE
UNITSMIN MAX
Output Low Voltage VOL VCC = 4.5V,
IOL = 3.2mA
Output High Voltage VOH VCC = 4.5V,
IOH = -0.4mA
Input Leakage Current II VCC = 5.5V,
VI = GND or VCC
Output Leakage Current IOZ VCC = 5.5V,
VO = GND or VCC
Data Retention Supply Current ICCDR VCC = 2.0V,
E = VCC,
IO = 0mA,
VI = VCC or GND
HM-6508/883 -10µA
Operating Supply Current ICCOP VCC = 5.5V,
(Note 2),
E = 1MHz,
IO = 0mA,
Standby Supply Current ICCSB VCC = 5.0V,
IO = 0mA,
VI = VCC or GND
NOTES:
1. All voltages referenced to device GND.
2. Typical derating 1.5mA/MHz increase in ICCOP.
1, 2, 3 -55oC ≤ TA≤ +125oC - 0.4 V
1, 2, 3 -55oC ≤ TA≤ +125oC 2.4 - V
1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 +1.0 µA
1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 +1.0 µA
1, 2, 3 -55oC ≤ TA≤ +125oC
-5µAHM-6508B/883
1, 2, 3 -55oC ≤ TA≤ +125oC- 4 mA
1, 2, 3 -55oC ≤ TA≤ +125oC- 10 µA
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