Intersil Corporation HM-6504-883 Datasheet
HM-6504/883
March 1997
Features
• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Low Power Standby. . . . . . . . . . . . . . . . . . . 125µW Max
• Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible Input/Output
• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Pin Package for High Density
• On-Chip Address Register
• Gated Inputs - No Pull Up or Pull Down Resistors
Required
Ordering Information
4096 x 1 CMOS RAM
Description
The HM-6504/883 is a 4096 x 1 static CMOS RAM
fabricated using self-aligned silicon gate technology. The
device utilizes synchronous circuitry to achieve high performance and low power operation.
On-chip latches are provided for addresses, data input and
data output allowing efficient interfacing with microprocessor
systems. The data output can be forced to a high impedance
state for use in expanded memory arrays.
Gated inputs allow lower operating current and also eliminate the need for pull up or pull down resistors. The
HM-6504/883 is a fully static RAM and may be maintained in
any state for an indefinite period of time.
Data retention supply voltage and supply current are guaranteed over temperature.
Pinout
PACKAGE TEMPERA TURE RANGE 200ns 300ns PKG. NO
CERDIP -55oC to +125oC HM1-6504B/883 HM1-6504/883 F18.3
HM-6504/883 (CERDIP)
TOP VIEW
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
Q
8
W
9
GND
PIN DESCRIPTION
A Address Input
E Chip Enable
W Write Enable
D Data Input
Q Data Output
18
VCC
17
A6
16
A7
15
A8
14
A9
13
A10
12
A11
11
D
10
E
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
6-134
File Number 2993.1
Functional Diagram
HM-6504/883
LSB
A8
A7
A6
A0
A1
A2
D
W
E
LATCHED
ADDRESS
REGISTER
L
D
LATCH
L
L
LATCH
A
A
6
6
QD
GATED
DECODER
D
LATCH
Q
ROW
G
L
64
Q
A
LSB A11 A5 A4 A3 A9 A10
NOTES:
1. All lines active high-positive logic.
2. Three-state Buffers: A high → output active.
3. Control and Data Latches: L low → Q = D and Q latches on rising edge of L.
4. Address Latches: Latch on falling edge of E.
5. Gated Decoders: Gate on rising edge of G.
64 x 64
MATRIX
G
GATED COLUMN
DECODER AND
DATA I/O
6
A
LATCHED
L
ADDRESS
REGISTER
64
Q
LATCH
L
Q
A
D
6
A
6-135
HM-6504/883
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range. . . . . . . . . . . . . . . .-55oC to +125oC
TABLE 1. HM-6504/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
(NOTE 1)
PARAMETER SYMBOL
CONDITIONS
Thermal Resistance θ
CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . .+175oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . .+300oC
JA
θ
JC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6910 Gates
Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +0.8V
Input High Voltage. . . . . . . . . . . . . . . . . . . VCC -2.0V to VCC +0.3V
LIMITS
GROUP A
SUBGROUPS TEMPERATURE
UNITSMIN MAX
Output Low Voltage VOL VCC = 4.5V,
IOL = 2mA
Output High Voltage VOH VCC = 4.5V,
IOH = -1.0mA
Input Leakage Current II VCC = 5.5V,
VI = GND or VCC
Output Leakage Current IOZ VCC = 5.5V,
VO = GND or VCC
Data Retention Supply Current ICCDR VCC = 2.0V,
E = VCC,
IO = 0mA
Operating Supply Current ICCOP VCC = 5.5V,
(Note 2),
E = 1MHz,
IO = 0mA
Standby Supply Current ICCSB VCC = 5.0V,
E = VCC -0.3V,
IO = 0mA
NOTES:
1. All voltage referenced to device GND.
2. Typical derating 1.5mA/MHz increase in ICCOP.
1, 2, 3 -55oC ≤ TA≤ +125oC - 0.4 V
1, 2, 3 -55oC ≤ TA≤ +125oC 2.4 - V
1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 +1.0 µA
1, 2, 3 -55oC ≤ TA≤ +125oC -1.0 +1.0 µA
1, 2, 3 -55oC ≤ TA≤ +125oC
-25µA
1, 2, 3 -55oC ≤ TA≤ +125oC- 7 mA
1, 2, 3 -55oC ≤ TA≤ +125oC- 50 µA
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