Intersil Corporation HIP9011 Datasheet

HIP9011

Data Sheet November 1998 File Number

Engine Knock Signal Processor

The HIP9011 is used to provide a method of detecting premature detonation often referred to as “Knock or Ping” in internal combustion engines.

The IC is shown in the Simplified Block Diagram. The chip can select between one of two sensors, if needed for accurate monitoring orfor “V” typeengines. Internal control via the SPI bus is fast enough to switch sensors between each firing cycle. A programmable bandpass filter processes the signal from either of the sensor inputs. The bandpass filter can be selected to optimize the extraction the engine knock or ping signals from the engine background noise. Further single processing is obtained by full wave rectification of the filtered signal and applying it to an integrator whose output voltage level is proportional to the knock signal amplitude. The chip is under microprocessor control via a SPI interface bus.

Ordering Information

TEMP.

PART NUMBER

HIP9011AB -40 to 125

RANGE (oC) PACKAGE

20 Ld SOIC

PKG.

NO.

M20.3

4367.1

Features

• Two Sensor Inputs

• Microprocessor Programmable

• Accurate and Stable Filter Elements

• Digitally Programmable Gain

• Digitally Programmable Time Constants

• Digitally Programmable Filter Characteristics

• On-Chip Crystal Oscillator

• Programmable Frequency Divider

• External Clock Frequencies up to 24MHz

- 4, 5, 6, 8, 10, 12, 16, 20, and 24MHz

• Operating Temperature Range -40

C to 125oC

Applications

• Engine Knock Detector Processor

• Analog Signal Processing Where Controllable Filter Characteristics are Required

Simpliﬁed Block Diagram

CH0FB CH0IN

CH0NI

CH1FB CH1IN CH1NI

SWITCHES

3RD ORDER

CHANNEL SELECT

ANTIALIASING FILTER

VMID

PROGRAMMABLE

GAIN

STAGE

- 0.111

64 STEPS

POWER SUPPLY

AND

BIAS CIRCUITS

VDD GND

PROGRAMMABLE

BANDPASS

FILTER

-20kHz

64 STEPS

ACTIVE

FULL WAVE

RECTIFIER

TO SWITCHED

CAPACITOR NETWORKS

REGISTERS

AND

STATE MACHINE

TEST

PROGRAMMABLE

INTEGRATOR

- 600µs

32 STEPS

PROGRAMMABLE

DIVIDER

SPI

INTERFACE

OUTPUT

DRIVER

AND

SAMPLE

AND HOLD

CLOCK

INTOUT

OSCIN

OSCOUT

INT/

HOLD

SCK

4-1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

HIP9011

Pinout

HIP9011

(SOIC)

TOP VIEW

GND

VMID

INTOUT

INT/

HOLD

OSCIN

OSCOUT

NC NC

1 2 3 4 5 6 7 8 9

20 19 18 17 16 15 14 13 12 11

CH0NI CH0IN CH0FB CH1FB CH1IN CH1NI TEST SCK SI SO

Pin Descriptions

NUMBER DESIGNATION DESCRIPTION

2 GND This pin is tied to ground. 3V

MID

4 INTOUT Buffered output of the integrator. Output signal is held by an internal Sample and Hold circuit when INT/

5, 6 NC These pins are not internally connected. Do Not Use.

7 INT/HOLD Selects whether the chip is in the Integrate Mode (Input High) or in the Hold Mode (Input Low). This pin has an

CS A low input on this pin enables the chip to communicate over the SPI bus. This pin has an internal pull-up.

9 OSCIN Input to inverter used for the oscillator circuit. A 4MHz crystal or ceramic resonator is connected between this pin and

10 OSCOUT Output of the inverter used for the oscillator. See pin 9 above. 11 SO Output of the chip SPI data bus. This is a three-state output that is controlled via the SPI bus. The output is

12 SI Input of the chip SPI data bus. Data length is eight bits. This pin has an internal pull-up. 13 SCK Input from the SPI clock. Normally low, the data is transferred to the chip internal circuitry on the falling clock

TEST A low on this pin places the chip in the diagnostic mode. For normal operation this pin is tied high or left open.

15 CH1NI Non-inverting input of Channel one. 16 CH1IN Inverting input to channel one ampliﬁer. A resistor is tied from this summing input to the transducer. A second

17 CH1FB Output of the channel one ampliﬁer. This pin is used to apply feedback. 18 CH0FB Output of the channel zero ampliﬁer. This pin is used to apply feedback. 19 CH0IN Inverting input to channel zero ampliﬁer. Remainder same as channel one ampliﬁer except feedback is applied

20 CH0NI Non-inverting input of Channel 0. Remainder the same as pin 16, except feedbac k is applied from terminal 18.

Five volt power input.

This pin is connected to the internal mid-supply generator and is brought out for bypassing bya 0.022µF capacitor.

low.

internal pull down.

pin 10. To bias the inverter, a 1.0MΩ to 10MΩ resistor is usually connected between this pin and pin 10.

placed in the high impedance state by setting

CS high when the chip is not selected. This high impedance state can also be programmed by setting the LSB of the prescaler word to 1. This will take precedence over CS. A 0 enables the active state. The Diagnostic Mode overrides these conditions.

edge. This pin has an internal pull up.

This pin has an internal pull up.

resistor is tied between this pin and pin 17, CH1FB to establish the gain of the ampliﬁer.

from pin 18.

HOLD is

4-2

HIP9011

Absolute Maximum Ratings

DC Logic Supply, VDD. . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V

Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V

Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Max

Thermal Information

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Maximum Pow er Dissipation, P

For TA = -40oC to 70oC . . . . . . . . . . . . . . . . . . . . . . .400mW Max

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC

For TA = 70oC to 125oC, Derate Linearly at . . . . . . . . . . 6mW/oC

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range, T

. . . . -65oC to 150oC

STG

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

At a Distance 1/16 ±1/32 inch, (1.59 ±0.79mm) from Case for

10s Max. (SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Speciﬁcations V

= 5V ±5%, GND = 0V, Clock Frequency 4MHz ±0.1%, TA = -40oC to 125oC,

Unless Otherwise Speciﬁed

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

DC ELECTRICAL SPECIFICATIONS

Quiescent Supply Current I Midpoint Voltage, Pin 3 V Midpoint Voltage, Pin 3 V Low Input V oltage , Pins INT/

HOLD,CS, SI, SCK V High Input Voltage , Pins INT/HOLD, CS, SI, SCK V Hysteresis voltage, Pins INT/HOLD, CS, SI, SCK V

DD MID MID

IL IH

HYST

Internal Pull-Up Current ISourceCS,SI,

TEST

SCK,

Internal Pull-Down Current I Sink,

HOLD

INT/ Low Level Output, Pin SO V High Level Output, Pin SO V Three-State Leakage Pin SO I Low Level Output, Pin 10, OSCOUT V High Level Output, Pin 10, OSCOUT V

VDD = 5.25V, GND = 0V - 5.0 8.0 mA VDD = 5.0V, IL = 2mA Source 2.3 2.45 2.55 V VDD = 5.0V, IL = 0mA 2.4 2.5 2.6 V

- - 30 % of V

70 - - % of V

0.85 - - V

VDD = 5.0V, Measured at GND - 50 - µA

VDD = 5.0V, Measured at V

SOURCE

SINK

= 1.6mA, VDD = 5.0V 0.01 - 0.30 V

= 200µA, VDD = 5.0V 4.8 4.9 5.0 V

- -50 - µA

Measured at GND; VDD = 5.0V - - ±10 µA I

SOURCE

SINK

= 500µA; VDD= 5.0V - - 1.5 V

= -500µA; VDD= 5.0V 4.4 - - V

DD DD

SPI BUS INTERFACE AC Parametrics CS Falling to SCLK Rising t CS Rising to SCLK Falling t SCLK Low t SCLK High t SCLK Falling to CS Rising t Data High Setup Time t Data Low Setup Time t Data High Hold Time t Data Low Hold Time t Min Time Between 2 Programmed Words t CS Rising to INT/Hold Rising t

CCH CCL PWL

PWH

SCCH

SUH

SUL

HH HL

CSH

CIH

10 - - ns 80 - - ns 60 - - ns 60 - - ns 60 - - ns 20 - - ns 20 - - ns 10 - - ns 10 - - ns

200 - - ns

8-- µs

4-3

HIP9011

Electrical Speciﬁcations V

= 5V ±5%, GND = 0V, Clock Frequency 4MHz ±0.1%, TA = -40oC to 125oC,

Unless Otherwise Speciﬁed (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

INPUT AMPLIFIERS

CH0 and CH1 High Output Voltage V CH0 and CH1 Low Output Voltage V Voltage Gain A

OUT

HI I

LO I

= 100µA, VDD = 5.0V 4.7 4.9 - V

SINK SOURCE

Input R = 47.5K, Feedback

= 100µA; VDD = 5.0V - 15 200 mV

+18 +20 +21 dB

R = 475kΩ

ANTIALIASING FILTER

Response 1kHz to 20kHz, Referenced to 1kHz BW Test Mode - -0.5 - dB Attenuation at 180kHz, Referenced

ATTEN Test Mode -10 -15 - dB

to 1kHz

PROGRAMMABLE FILTERS

Peak to Peak Voltage Output V

OUT

Run Mode 3.5 4.0 - V

P-P

Filters Q (Note 2) Q Run Mode - 2.5 - Q

PROGRAMMABLE GAIN AMPLIFIERS

Percent Amplifier Gain Deviation %G Run Mode - ±1- %

INTEGRATOR

Integrator Reset Voltage V

RESET

Pin 4 Voltage at Start of

75 125 175 mV Integration Cycle; VDD = 5.0V

Integrator Droop after 500µsV

DROOP

Hold Mode, Pin 7 = 0V,

- ±3 ±50 mV VDD= 5.0V Pin 4 set to 20% to 80% of V

DIFFERENTIAL CONVERTER

Differential to Single Ended Converter Offset

DIFV

By Design - 0.1 - mV

Voltage Change In Converter Output DIFOUT Run Mode, 500µA Sinking Load

- ±1 ±10 mV to No Load Condition

SYSTEM GAIN DEVIATION

Gain Deviation from “Ideal Equation” Correlation Factor + 5.0% (Note 3)

OUT

RESET

Run Mode, maximum signal output from Input Amplifier <2.25V

, Equation Output X

P-P

0.95 + Device Reset Voltage; For Total V

OUT

≤ 4.7V

-8%,

±100mV

Equa-

tion

X 0.95

- V

RE-

SET

8%,

±100mV

NOTES:

2. Q = fo/BW, where: fo = Center Frequency, BW = 3dB Bandwidth

3. Ideal Equation: INTOUT (Volts) = [V Where: VIN = input signal amplitude (V

GIN =External Input Gain; GIN = RF/R

* GIN * GPR * G

)

P-P

* 1/π * (N/tC(ms) *fQ(kHz)) * G

BPF

DSE

] + V

RESET

GPR =Programmed Gain

=Gain of Bandpass Filter (2 for Ideal Case at Center)

BPF

=Integration Time; t

INT

= N/f

0.318 =1/π

N =Number of Cycles of Input Signal

fQ =Frequency of Input Signal

RF =Feedback Resistor Value

RIN =Signal Input Resistor Value

tC =Programmed Time Constant

=Gain of DSE Converter (2 for Ideal Case)

DSE

=Integrator Reset Voltage = 0.125V, Typ

RESET

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