Intersil Corporation HIP9010 Datasheet
HIP9010
Data Sheet November 1998 File Number
Engine Knock Signal Processor
The HIP9010 is used to provide a method of detecting
premature detonation or “Knock” in automotive engines.
A block diagram of this IC is shown in Figure 1. The chip
alternately selects one of the two sensors mounted on the
engine block. Two programmable bandpass filters process
the signal from both sensors, and divides the signal into two
channels. When the engine is not knocking, programmable
gain adjust stages are set to ensure that both the reference
channel and the knock channel contain similar energies.
This technique ensures that the detection system is
comparatively immuneto changes in the engine background
noise level. When the engine is knocking, the energy in the
knock channel increases.
Ordering Information
TEMP.
PART NUMBER
HIP9010AB -40 to 125 20 Ld SOIC (W) M20.3
RANGE (oC) PACKAGE
PKG.
NO.
3601.4
Features
• Two Sensor Inputs
• Microprocessor Programmable
• Accurate and Stable Filter Elements
• Digitally Programmable Gain
• Digitally Programmable Time Constants
• Digitally Programmable Filter Characteristics
• On-Chip Clock
o
• Operating Temperature Range -40
C to 125oC
Applications
• Engine Knock Detector Processor
• Analog Signal Processing where Controllable Filter
Characteristics are Required
Pinout
HIP9010
(SOIC)
TOP VIEW
GND
V
INOUT
HOLD
INT/
OSCIN
OSCOUT
V
DD
MID
NC
NC
CS
1
2
3
4
5
6
7
8
9
10
S0IN
20
S0FB
19
S1FB
18
S1IN
17
NC
16
NC
15
TEST
14
SCK
13
12
MOSI
11
MISO
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
Simplified Block Diagram
4-2
(19) S0FB
(20) S0IN
(18) S1FB
(17) S1IN
(3) V
-
+
-
+
POWER SUPPLY
BIAS CIRCUITS
(1) V
MID
CHANNEL SELECT
SWITCHES
AND
(2) GND
DD
ANTIALIASING
3RD ORDER
FILTER
REFERENCE FREQUENCY CHANNEL
PROGRAMMABLE
BANDPASS
FILTER
1-20kHz
64 STEPS
PROGRAMMABLE
BANDPASS
FILTER
1-20kHz
64 STEPS
KNOCK FREQUENCY CHANNEL
PROGRAMMABLE
GAIN
STAGE
1-0.133
64 STEPS
PROGRAMMABLE
STAGE
GAIN
1-0.133
64 STEPS
ACTIVE
FULL WAVE
RECTIFIER
ACTIVE
FULL WAVE
RECTIFIER
PROGRAMMABLE
INTEGRATOR
40-600µs
32 STEPS
TO SWITCHED
CAPACITOR
NETWORKS
REGISTERS
AND
STATE MACHINE
(14) TEST
DIFFERENTIAL
TO
SINGLE-ENDED
CONVERTER
AND OUTPUT
DRIVER
CLOCK
SPI
INTERSPACE
INOUT (4)
OSCIN (9)
OSCOUT (10)
SCK (13)
CS (8)
MOSI (12)
MISO (11)
INT/
HOLD (7)
HIP9010
FIGURE 1.
HIP9010
Absolute Maximum Ratings Thermal Information
DC Logic Supply, VDD. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V (Max)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Thermal Resistance (Typical, Note 1) θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Maximum Storage Temperature Range, T
. . . . -65oC to 150oC
STG
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Lead Temperature (Soldering) . . . . . . . . . . . . . . . 300oC
At distance 1/16in ± 1/32in (1.59mm ± 0.79mm) from case
for 10s (Max) (SOIC - Lead Tips Only)
Electrical Specifications V
= 5V, ±5%, GND = 0V, Clock Frequency 4MHz, ±0.5%, TA = -40oC to 125oC,
DD
Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
DC ELECTRICAL CHARACTERISTICS
Quiescent Supply Current I
Midpoint Voltage, Pin 3 V
Midpoint Voltage, Pin 3 V
Input Leakage, Pin 14 IL
Internal Pull-Up Resistance, Pin 14 R
Leakage of Pins 7, 8, 12 and 13 I
Low Input Voltage, Pins 7, 8, 12 and 13 V
High Input Voltage, Pins 7, 8, 12 and 13 V
Low Level Output, Pin 11 V
Leakage Pin 11 I
Low Level Output, Pin 10 V
High Level Output, Pin 10 V
DD
MID
MID
TEST
TEST
OL
OL
OH
VDD= 5.25V, GND = 0V 3 7.5 12 mA
VDD = 5.0V, IL = 2mA Source 2.3 2.45 2.55 V
VDD = 5.0V, IL = 0mA 2.4 2.5 2.6 V
Measured at VDD = 5.0V - - 3 µA
VDD = 5.0V, I Measure = 15µA 30 100 200 KΩ
Measured at GND and VDD = 5V - - ± 3 µA
L
IL
IH
I
SOURCE
Measured at GND and VDD = 5V - - ±10 µA
L
I
SOURCE
I
SINK
= 4mA 0.01 - 0.30 V
= 500µA, VDD = 5V - - 1.5 V
= -500µA, VDD = 5V 4.4 - - V
- - 30 % of V
70 - - % of V
INPUT AMPLIFIERS
S0FB and S1FB High Output Voltage V
S0FB and S1FB Low Output V oltage V
S0FB and S1FB Closed Loop A
HI 100µA I
OUT
LO 100µA I
OUT
CL
, VDD = 5V 4.7 4.9 - V
SINK
SOURCE
, VDD = 5V - 15 200 mV
Input Resistor = 1MΩ,
-25 -26 -27 dB
Feedback Resistor = 49.9kΩ
S0FB and S1FB Closed Loop A
CL
Input Resistor = 47.5kΩ,
18 20 21 dB
Feedback Resistor = 475kΩ
ANTIALIASING FILTER
Response 1kHz to 20kHz,
Referenced to 1kHz
Attenuation at 180kHz
Referenced to 1kHz
BW Test Mode, 70mV
S1FB, Output Pin 4
ATEN Test Mode, 70mV
S1FB, Output Pin 4
Input to S0FB or
RMS
Input to S0FB or
RMS
--2-dB
-10 -15 - dB
PROGRAMMABLE FILTERS
Peak to Peak Voltage Output V
OUTP-P
Run Mode 3.5 4.0 - V
Filters Q (Note 2) Q Run Mode - 2.5 - Q
PROGRAMMABLE GAIN AMPLIFIERS
Percent Amplifier Gain Deviation
%G Run Mode - ±1-%
Per Table 2
DD
DD
P-P
4-3
HIP9010
Electrical Specifications V
= 5V, ±5%, GND = 0V, Clock Frequency 4MHz, ±0.5%, TA = -40oC to 125oC,
DD
Unless Otherwise Specified (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
INTEGRATOR
Integrator Offset Voltage INTGVIOBy Design - 0.1 - mV
Integrator Reset Voltage V
RESET
Pin 4 Voltage at Initiation of
430 500 570 mV
Integration Cycle. VDD= 5V
Integrator Droop after 500µsV
DROOP
Hold Mode, Pin 7 = 0V, VDD= 5V,
Pin 4 set to 20% to 80% of V
DD
- ±3 ±50 mV
OUTPUT AND SAMPLE AND HOLD
Differential to Single Ended
DIFV
By Design - 0.1 - mV
IO
Converter Offset Voltage
Change in Converter Output DIFOUT Run Mode, 500µA, Sinking to No Load - ±1 ±3mV
SYSTEM GAIN DEVIATION
Gain Deviation from “Ideal Equation”
Correlation, Factor - 5.0%
V
OUT
V
RESET
-
Run Mode, maximum signal output
from Input Amplifier <2.25V
Equation Output x 0.95 + Device
Reset Voltage. For Total V
P-P
OUT
,
≤ 4.7V
-8%,
±100mV
Equation
x 0.95
-V
RESET
8%,
±100mV
V
NOTE:
2. Q = fO/BW, Where: fO = Center Frequency, BW = 3dB bandwidth.
Ideal Equation
INTOUT volts()Input signal (V
--------- -
)
× GK1.273
PP–
R
IN
---------------------------------------------------
××
TC (ms) fQ(kHz)×
R
F
When the two filters are set to the same frequency and the input signal is present for the periods TIN, then:
R
F
INTOUT volts()Input signal (V
G
and GK = Programed Gain of Reference and Knock channels.
R
PP–
)
--------- -
× 1.273
R
IN
T
---------
TC
IN
G
TIN = Time input signal is present In ms.
TC = Programmed integrator time constant ms.
N = Number of cycles of input signal.
fQ = Frequency of input signal. Assumes both filters are programmed to the same frequency.
V
= Integrator Reset Voltage.
RESET
1.273 = 4/π
RF = Feedback resistor value.
RIN = Signal input resistor value.
For example, assume 300mV
the Reference channel is programmed to a Gain of 0.188. The Knock channel is then automatically set to a gain of one. The input signal is continuous for the total integration time, T
INTOUT volts()0.3V (V
input with the time constant programmed to 300µs and the Integration time is 1.2ms. The RF/RINratio is one and
P-P
.
IN
PP–
) 1.273
× V
1.2ms
-----------------------
0.300ms
1.000 0.188–()××
–()×
KGR
N
V
+=
GR1.273
– V
RESET
RESET
1.24V 0.500V 1.74V=+=+=
---------------------------------------------------
××
TC (ms) fQ(kHz)×
N
+=
RESET
4-4
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