Intersil Corporation HIP7030A2 Datasheet

ADVANCE INFORMATION

August 1996

HIP7030A2

J1850 8-Bit 68HC05 Microcontroller

Features

• Fully Supports VPW Specifications of SAE J1850
Standard for Class B Data Communications Network
Interface

• On-Chip Memory

• 176 Bytes of RAM

• 2110 Bytes of User ROM

• 13 Bidirectional I/O Lines

• 16-Bit Timer with Capture and Compare Registers

• Serial Peripheral Interface (SPI) System

• Watchdog Timer and Slow Clock Detect

• 10MHz Operating Frequency (5.0MHz Internal Bus
Frequency) at 5V

• Built-In-Test Bootstrap Mode with 242 Bytes of ROM

• Two Channel Analog Comparator

• On-Chip Oscillator Amplifier

• 8-Bit CPU Architecture

• Power-Saving STOP, WAIT and Data Retention Modes

o

• Full -40

• Single 3.0V to 6.0V Supply

• 28 Lead Dual-In-Line and Small Outline Plastic Pack­ages

C to 125oC Operating Range

Software Features

• Standard 68HC05 Instruction Set

• True Bit Manipulation

• Addressing Modes Include Indexed Addressing

- Memory Mapped I/O

Ordering Information

TEMP.

PART NUMBER

HIP7030A2P -40 to 125 28 Lead Plastic

HIP7030A2M -40 to 125 28 Lead Plastic

RANGE (oC) PACKAGE

DIP

SOIC (W)

PKG.

NO.

M28.3

E28.6

Description

The HIP7030A2 HCMOS Microcomputer is a member of the
CDP68HC05 family of low-cost single-chip microcomputers.
The integrated hardware functions provide the system
designer with a complete set of building blocks for
implementing a “Class B” multiplexed communications net­work interface, which fully conforms to the VPW Multiplexed
Wiring protocol specified in SAE Recommended Practice
J1850. This 8-bit microcomputer unit (MCU) contains an on­chip oscillator, CPU, 176 bytes of RAM, 2110 bytes of user
ROM, 13 I/O lines, a J1850 Variable Pulse Width Symbol
Encoder/Decoder (VPW SENDEC) system, a Serial Periph­eral Interface (SPI) system, a two channel analog Compara­tor, a Watchdog Timer, a Slow Clock Detect, and a 16-bit
Timer. The static HCMOS design allows operation at input
frequencies up to 10MHz (5MHz internal clock).

Table of Contents

Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Electrical & Timing Specifications. . . . . . . . . . . . . . . . . . . . . 3

Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Integrated Hardware I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Built-In Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Programmable Timer

Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . 27

J1850 VPW Messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Symbol Encoder Decoder

Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

COP System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Effects of STOP and WAIT Modes . . . . . . . . . . . . . . . . . . . . 41

Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Package Outline Dimensions . . . . . . . . . . . . . . . . . . . . 55 - 56

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

I/O, Control, Status and Data Register Definitions. . . . . . . 52

Ordering

Information Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Ordering Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

1

File Number 3646.2

Block Diagram

TCMP

1

TCAP

15

PA0

14

PA1

13

PA2

12

PA3

11

PA4

10

PA5

9

PA6

PORT A I/O LINES

PD2, V2
PD3, V3

PD4, VR

PORT D I/O LINES

PA7

PD0
PD1

TCAP

8

21
20
19
18

17

VSS22
VDD7

2

TIMER SYSTEM

PORT

A

REG

PORT D

REG

+

-

+

-

PORT D

SFR
REG

DAT A

DIR

REG

PORT D

DIR

REG

HIP7030A2

INTERNAL

PROCESSOR

CLOCK

ACCUMULATOR

8

INDEX

REGISTER

8

CONDITION CODE

5

REGISTER

STACK

6

POINTER

PROGRAM

COUNTER HIGH

5

PROGRAM

8

COUNTER LOW

2110 x 8

ROM

242 x 8

BUILT-IN-TEST

ROM

OSCIN OSCOUT

2324

OSCILLATOR

AND

÷ 2

A

X

CC

S

PCH

PCL

176 x 8

STATIC RAM

16

OSCB

CPU

CONTROL

CPU

ALU

WATCHDOG AND

SLOW CLOCK DETECT

5

RESET

6

IRQ

SYMBOL INT

VPW SYMBOL

ENCODER /

DECODER AND

ARBITRATION

SPI

SYSTEM

INTERNAL PROCESSOR

CLOCK

4
3

25
26
27
28

VPW OUT
VPW IN

SCK
MOSI
MISO
SS

Pinout

TCAP

TCMP

VPW IN

VPW OUT

RESET

IRQ

V

DD

PA7
PA6
PA5
PA4
PA3
PA2
PA1

1
2
3
4
5
6
7
8

9
10
11
12
13
14

HIP7030A2

(PDIP, SOIC)

TOP VIEW

28

SS
MISO

27
26

MOSI

25

SCK
OSCIN

24
23

OSCOUT
V

22

PD0

21
20

PD1
PD2, V2

19

PD3, V3

18
17

PD4, VREF

16

OSCB
PA0

15

SS

2

HIP7030A2

Absolute Maximum Ratings Thermal Information

Supply Voltage (VDD). . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V

Input or Output Voltage

Pins with VDD Diode. . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V

Pins without VDD Diode . . . . . . . . . . . . . . . . . . . . . -0.3V to +10V

Current Drain Per Pin, I (Excluding VDD and VSS) . . . . . . . . 25mA

Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . +265oC

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

Gate Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9000 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +3.0V to +5.5V

Operating Temperature Range. . . . . . . . . . . . . . . . .-40oC to 125oC

Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V

Thermal Resistance (Typical) θ

JA

Plastic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .60oC/W

Plastic SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . 75oC/W

Maximum Package Power Dissipation at +125oC

DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415mW

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325mW

Operating Temperature Range (TA) . . . . . . . . . . . .-40oC to +125oC

Storage Temperature Range (T

). . . . . . . . . . . .-65oC to +150oC

STG

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC

Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . ..(0.8•VDD) to V

DD

Input Rise and Fall Time

CMOS Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100ns Max.

CMOS Schmitt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .Unlimited

DC Electrical Specifications V

= 5VDC±10%, VSS = 0VDC, TA = -40oC to +125oC Unless Otherwise Specified

DD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

No Load Output Voltage V

Output High Voltage: PA0-7, PD0-4, VPWOUT,
TCMP

Output High Voltage: OSCOUT V
Output High Voltage: MISO, MOSI, SCK, OSCB V
Output Low Voltage: OSCOUT V
Output Low Voltage: MISO, MOSI, SCK, OSCB V
Input High Voltage: PA0-7, PD0-4, MISO, MOSI,

SS, SCK
Input High Voltage: RESET, IRQ, TCAP,

VPWIN, OSCIN
Input Low Voltage: PA0-7, PD0-4, MISO, MOSI,

SS, SCK
Input Low Voltage: RESET,IRQ, TCAP,VPWIN,

OSCIN
Input Hysteresis Voltage: RESET, IRQ, TCAP,

VPWIN, OSCIN
Supply Current

RUN I
WAIT (Note 2) I
STOP (Notes 2, 3) I

I/O Ports Hi-Z Leakage Current: PA0-7, PD0-4,
MISO, MOSI, SCK

Input Current: RESET, IRQ, TCAP,
OSCIN, VPWIN, SS

OL

V

OH

V

OH

OH
OH

OL

OL

V

IH

V

IH

V

V

V

HYS

RUN
WAIT
STOP

I

IL

I

IN

I

< ±10µA - - 0.1 V

LOAD

VDD-0.1 - - V

I

= -0.8mA VDD-0.8 VDD-0.4 - V

LOAD

I

= -0.08mA VDD-0.8 VDD-0.4 - V

LOAD

I

= -1.6mA VDD-0.8 VDD-0.4 - V

LOAD

I

= 0.17mA - 0.2 0.4 V

LOAD

I

= 1.6mA - 0.2 0.4 V

LOAD

IL

IL

f

= 10MHz Exter-

OSC

nal Square Wave

0.7•V

DD

0.8•V

DD

V

SS

V

SS

0.1•V

DD

- 8 18 mA

- 3.2 10 mA

-VDDV

-VDDV

- 0.3•V

- 0.2•V

1.0 0.5•V

TA = 25oC-250µA
TA = -40oC to 125oC - 10 250 µA

-10 ±0.01 +10 µA

-1 .001 +1 µA

DD

DD

DD

V

V

V

3

HIP7030A2

DC Electrical Specifications V

= 5VDC±10%, VSS = 0VDC, TA = -40oC to +125oC Unless Otherwise Specified (Continued)

DD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Capacitance: (Note 4) C

Powerdown Input Voltage: RESET, IRQ,

V

OUT

C

IN

INPD

VDD = 0 -0.3 - 7 V

- - 12 pF

--8pF

VPWIN, OSCIN
Comparator:

Input Voltage: V2, V3, V

REF

V

IN

VSS-0.2 - V

DD

V

+0.02

Input Current: V2, V3, V

REF

Offset Voltage V
Response t

I

IN

OFF

R

-1 - +1 µA

-20-mV

-2-µs

NOTES:

1. This device contains circuitry to protect the inputs against damage due to high static voltages of electric fields; howe ver, it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For
proper operation it is recommended that VIN and V

be constrained to the range VSS<(VIN or V

OUT

)<VDD. Reliability of operation is

OUT

enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either VSS or VDD).

2. WAIT, STOP IDD: All ports configured as inputs, VIL = 0.2V and VIH = VDD - 0.2V.

3. STOP IDD measured with OSCIN = VSS, no feedback resistor connected.

4. Includes Ports used as Input/Output Pins, Ports used as Input only Pins; Ports used as Output only Pins.

Control Timing V

= 5VDC±10%, VSS = 0VDC, TA = -40oC to 125oC Unless Otherwise Specified

DD

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Frequency Of Operation

Crystal Option f
External Clock Option f

OSC
OSC

Internal Operating Frequency

Crystal (f

External Clock (f
Cycle Time t
Crystal Oscillator Start-up Time for AT-cut Crystal t
Stop Recovery Start-up Time (AT-cut Crystal

+2) f

OSC

+2) f

OSC

OP
OP

CYC

OXOV

t

ILCH

Oscillator)
RESET Pulse Width t

RL

Timer

Resolution (Note 1) t

Input Capture Pulse Width tTH, t

Input Capture Pulse Period tTL, t
Interrupt Pulse Width Low (Edge-Triggered) t
OSC1 Pulse Width tOH, t
Slow Clock Detect Frequency Range f

RES

TL
TL

ILIH

OL

SLOW

NOTES:

1. Since a 2-bit prescaler in the timer must count four internal cycles (t
resolution.

2. The minimum period t
24 t

.

CYC

should not be less than the number of cycle times it takes to execute the capture interrupt service routine plus

TLTL

1 - 10 MHz
1 - 10 MHz

0.5 - 5 MHz

0.5 - 5 MHz

200 - - ns

- - 100 ms

- - 100 ms

1.5 - - t

4--t

50 - - ns

(Note 2) - - t

50 - - ns
35 - - ns
20 50 200 KHz

), this is the limiting minimum factor in determining the timer

CYC

CYC

CYC

CYC

4

HIP7030A2

Serial Peripheral Interface (SPI) Timing (See Figure 3) V

= 5VDC±10%, VSS = 0VDC, TA = -40oC to 125oC

DD

Unless Otherwise Specified

NUMBER PARAMETER SYMBOL MIN MAX UNITS

Operating Frequency

Master f

OP(M)

0.03 0.5 f

OP

(Note 3)

Slave f

OP(S)

DC 5 MHz

1 Cycle Time

Master t
Slave t

CYC(M)
CYC(S)

2- t

CYC

200 - ns

2 Enable Lead Time

Master t
Slave t

LEAD(M)
LEAD(S)

(Note 1) - -

50 - ns

3 Enable Lag Time

Master t
Slave t

LAG(M)
LAG(S)

(Note 1) - -

50 - ns

4 Clock (SCK) High Time

Master t
Slave t

W(SCKH)M
W(SCKH)S

200 - ns

50 - ns

5 Clock (SCK) Low Time

Master t
Slave t

W(SCKL)M

W(SCKL)S

200 - ns

50 - ns

6 Data Setup Time (Inputs)

Master t
Slave t

SU(M)

SU(S)

50 - ns
50 - ns

7 Data Hold Time (Inputs)

Master t
Slave t

H(M)

H(S)

50 - ns
50 - ns

8 Access Time (Time to Data Active from High Impedance State)

Slave t

A

0 120 ns

9 Disable Time (Hold Time to High Impedance State)

Slave t

DIS

- 200 ns

10 Data Valid Time

Master (Before Capture Edge) t
Slave (After Enable Edge) (Note 2) t

V(M)

V(S)

0.25 - t

- 150 ns

CYC(M)

11 Data Hold Time (Outputs)

Master (After Capture Edge) t
Slave (After Enable Edge) t

HO(M)
HO(S)

0.25 - t

CYC(M)

0-ns

12 Rise Time (VDD = 20% to 70%, CL = 100pF)

SPI Outputs (SCK, MOSI, MISO) t
SPI Inputs (SCK, MOSI, MISO, SS) t

R(M)

R(S)

-50ns

-2µs

13 Fall Time (VDD = 20% to 70%, CL = 100pF)

SPI Outputs (SCK, MOSI, MISO) t
SPI Inputs (SCK, MOSI,MISO, SS) t

F(M)
F(S)

-50ns

-2µs

NOTES:

1. Signal Production depends on software.

2. Assumes 200pF load on all SPI pins.

3. Note that the units this specification uses is fOP (internal operating frequency), not MHz! In the master mode the SPI bus is capable of
running at one-half of the devices’s internal operating frequency, therefore, 2.5MHz maximum.

5

Control Timing Diagrams

OSC1

(NOTE 1)

t

t

RL

ILIH

RESET

IRQ

HIP7030A2

t

ILCH

INTERNAL

CLOCK

INTERNAL

ADDRESS

BUS

NOTE:

1. Represents the internal gating of the OSC1 pin.

FIGURE 1. STOP RECOVERY TIMING DIAGRAM

EXTERNAL

(TCAP PIN 1)

FIGURE 2.

Serial Peripheral Interface (SPI) Timing Diagrams

t

TLTL

4064 t

t

TH

CYC

1FFE

RESET OR INTERRUPT
VECTOR FETCH

t

TL

SS (INPUT)

SCK (OUTPUT)

MISO (INPUT)

MOSI (OUTPUT)

HELD HIGH ON MASTER

(1)

(6)

(4)

D7I D6I D0I

(7)

D7O D6O D0O

(11)(10)

(5)

FIGURE 3A. SPI MASTER TIMING CPOL = 0, CPHA = 1

6

(12)(13)

HIP7030A2

Serial Peripheral Interface (SPI) Timing Diagrams

HELD HIGH ON MASTER

SS (INPUT)

SCK (OUTPUT)

MISO (INPUT)

MOSI (OUTPUT)

SS (INPUT)

SCK (OUTPUT)

(4)

D7I D6I D0I

(6)

(7)

D7O D6O D0O

(11)(10)

FIGURE 3B. SPI MASTER TIMING CPOL = 1, CPHA = 1

HELD HIGH ON MASTER

(1)

(5)

(1)

(Continued)

(12)(13)

(12)(13)

MISO (INPUT)

MOSI (OUTPUT)

SS (INPUT)

SCK (OUTPUT)

MISO (INPUT)

MOSI (OUTPUT)

(6)

(4)

D7I D6I D0I

(7)

D7O D6O D0O

(11)(10)

(5)

FIGURE 3C. SPI MASTER TIMING CPOL = 0, CPHA = 0

HELD HIGH ON MASTER

(1)

(6)

(5)

D7I D6I D0I

(7)

D7O D6O D0O

(11)(10)

(4)

(12)(13)

NOTE:

1. Measurement points are VOL, VOH, VIL and V

FIGURE 3D. SPI MASTER TIMING CPOL = 1, CPHA = 0

IH.

7

HIP7030A2

Serial Peripheral Interface (SPI) Timing Diagrams

SS (INPUT)

SCK (INPUT)

MISO (OUTPUT)

MOSI (INPUT)

SS (INPUT)

SCK (INPUT)

HIGH
Z

(4)(2)

LAST

TRANSMITTED

(8)

BIT

FIGURE 3E. SPI SLAVE TIMING CPOL = 0, CPHA = 1

LAST
BIT
TRANSMITTED

(1)

(13)

(5)

D7O D6O D0O

D7I D6I D0I

(7)(6)

(1)(5)(2)

(4)

(Continued)

(12)

(3)

(9)(11)(10)

(3)

(13)(12)

MISO (OUTPUT)

MOSI (INPUT)

NOTE:

1. Measurement points are V

SS

(INPUT)

SCK

(INPUT)

MISO

(OUTPUT)

MOSI

(INPUT)

(8)

, VOH, VIL and VIH.

OL

FIGURE 3F. SPI SLAVE TIMING CPOL = 1, CPHA = 1

(2)

(8)

D7O D6O D0O

D7I D6I D0I

(7)(6)

(1)

(13)

(4)

D7O D6O D0O

D7I D6I D0I

(10)

(5)

(11)

(12)

(9)(11)(10)

(3)

(9)

(6)

(7)

FIGURE 3G. SPI SLAVE TIMING CPOL = 0, CPHA = 0

8

HIP7030A2

Serial Peripheral Interface (SPI) Timing Diagrams

SS

(INPUT)

(2)

SCK

(INPUT)

MISO

(OUTPUT)

(8)

MOSI

(INPUT)

(6)

NOTE:

1. Measurement points are VOL, VOH, VIL and V

FIGURE 3H. SPI SLAVE TIMING CPOL = 1, CPHA = 0

(5)

D7O

(10)

D7I

(7)

IH.

(1)

(12) (13) (3)

(4)

D6O D0O

D6I

(Continued)

(11)

(9)

D0I

Functional Pin Description

This section provides a description of each of the 28 pins of
the HIP7030A2 MCU.

V

and VSS (Power)

DD

Power is supplied to the MCU using these two pins. V
connected to the positive supply and V

is connected to

SS

the negative supply.

IRQ (Maskable Interrupt Request - Input)

IRQ pin is negative edge-sensitive triggering. A high to

The
low transition on the

IRQ pin will produce an interrupt.

In the event of an interrupt request, the MCU always com­pletes the current instruction before it responds to the
request. An internal mask can be used to inhibit the MCU
from responding to IRQ interrupts.

An IRQ interrupt is generated if the
at least one t

. The occurrence of the low going pulse is

ILIH

IRQ pin is pulled low for

registered in a flip-flop and the IRQ interrupt will be recog­nized even if the

IRQ pin has returned to a high state before

the interrupt can be serviced.
Once the edge-sensitive flip-flop is cleared, (it is automati-

cally cleared at the start of the interrupt ser vice routine) the
interrupt request is removed until the

IRQ pin returns to a

high level and once again goes low.
See

INTERRUPTS

for more details concerning IRQ inter-

rupts.

DD

is

RESET (Master Reset - Input)

The HIP7030A2 contains an integrated Power-On Reset
(POR) circuit and the

RESET input is therefore not required
for start-up. It can be used to reset the MCU internal state
and provides for an orderly re-start of the software after ini­tial power-up. Refer to
POR and

RESET.

Resets

for a detailed description of

TCAP (Timer Capture - Input)

The TCAP input controls the input capture feature for the on­chip programmable timer system. The TCAP input is also
used as the strobe signal to the Port D strobed outputs.
Refer to

put Mode

Input Capture Register

and

for additional information.

PD0, PD1 Strobed Out-

TCMP (Timer Compare - Output)

The TCMP pin provides an output for the output compare
feature of the on-chip timer system. Refer to

pare Register

for additional information.

Output Com-

OSCIN (Oscillator Input - Input),
OSCOUT (Oscillator Output - Output),
OSCB (Oscillator Buffered Output - Output)

OSCIN is the input and OSCOUT is the output of an
inverter/amplifier which can be used to build either a quartz
crystal or ceramic resonator based clock oscillator. Alterna­tively, the OSCIN input can be driven from any external clock
source which satisfies the CMOS Schmitt trigger input level
requirements of the OSCIN pin. See

Electrical Specifications

for input level specification.

9

HIP7030A2

OSCB is a squared, buffered version of the OSCIN signal,
available for driving one external CMOS load.

The fundamental internal clock is derived by a divide-by-two
of the external oscillator frequency (f
clocks are also derived from the external frequency. These
clocks include the input to the 16-bit Timer, the Serial Clock
(SCK), and the VPW Symbol Encoder/Decoder (SENDEC).

Quartz Crystal

The circuit shown in Figure 4A is recommended when using
a quartz crystal. The inter nal oscillator is designed to inter­face with an AT -cut parallel resonant quartz crystal in the fre­quency range specified for f

OSC

in
Figure 4B lists the recommended capacitance and feedback
resistance values. Use of an external CMOS oscillator is rec­ommended when crystals outside the specified ranges are
to be used. The crystal and components should be mounted
as close as possible to the OSCIN and OSCOUT pins to
minimize output distortion and start-up stabilization time.

Ceramic Resonator

A ceramic resonator may be used in place of the crystal in
cost sensitive applications. The circuit in Figure 4A is recom­mended when using a ceramic resonator. Figure 4C lists the
recommended capacitance and feedback resistance values.
The manufacturer of the particular ceramic resonator being
considered should be consulted for specific information.

External Clock

). All other internal

OSC

Electrical Specifications

10MHz UNITS

(Typical) 5.5 Ω

R

S

C

0

C

1

C

IN

C

OUT

R

P

Q 500 -

.

NOTES:

1. When no power is applied to the HIP7030A2, the OSCIN,IRQ,
RESET, and VPWIN pins can have up to 9VDC applied with no
side effects.

2. When power is applied to the HIP7030A2, it is recommended that
all unused inputs, except Port A and Port D I/O lines configured
as outputs, be tied to an appropriate logic level (i.e., either V
or VSS).

FIGURE 4C. CERAMIC RESONATOR PARAMETERS

35 pF

5pF
22 pF
22 pF

1-5 MΩ

C

L

R

1

S

DD

If an external clock is used, it should be applied to the
OSCIN input with the OSCOUT output not connected, as
shown in Figure 4E. The t

OXOV

or t

specifications do

ILCH

not apply when using an external clock input. The equivalent
specification of the external clock source should be used in
lieu of t

FIGURE 4A. CRYSTAL/RESONATOR CIRCUIT CONNECTIONS

RS (Max) 400 75 50 30 Ω
C

0

C

1

C

IN

C

OUT

R

P

Q 303030 30 K

or t

OXOV

FIGURE 4B. QUARTZ CRYSTAL PARAMETERS

.

ILCH

MCU

OSCIN OSCOUT

R

P

C

IN

2MHz 4MHz 8MHz 10MHz UNITS

575 5pF

0.008 0.012 0.015 0.018 µF
15-40 15-30 12-30 12-30 pF
15-30 15-25 12-25 12-25 pF

1-10 1-10 1-10 1-10 MΩ

C

OUT

C

0

FIGURE 4D. CRYSTAL/RESONATOR EQUIVALENT CIRCUIT

MCU

OSCIN OSCOUT

24 23

UNCONNECTED

FIGURE 4E. EXTERNAL CLOCK SOURCE CONNECTIONS

EXTERNAL CLOCK

PA0-PA7 (Port A - Input/Output)

These eight I/O lines comprise Port A. The mode (i.e., input
or output) of each pin is software programmable. All Port A
I/Os are configured as inputs during a POR, COP, or exter­nal reset. Refer to

Port A

under

Port A and D I/O Lines

for a

detailed description of programming the Port A I/O lines.

PD0-PD4 (Port D - Input/Output)

These five I/O lines comprise Port D. As with PA0-PA7, the
mode (i.e., input or output) of each pin is software programma­ble. In addition, a Special Function Register (SFRD) allows
configuring PD0 and PD1 as “strobed” outputs, and/or PD2,
PD3, and PD4 as inputs to an on-chip analog comparator.

10

HIP7030A2

All Port D I/Os are configured as inputs during a POR, COP,
or external reset. Refer to

Lines

under

Port A and D I/O Lines

PD0-PD4 Special Function I/O

for a detailed description

of programming the Port D I/O lines.

VPWOUT (Variable Pulse Width Out - Output),
VPWIN (Variable Pulse Width In - Input)

These two lines are used to interface to the J1850 bus trans­ceiver .

VPWOUT is the pulse width modulated output of the SEN­DEC encoder block.

VPWIN is the inverted input to the SENDEC decoder block.

VPW Symbol Encoder/Decoder (SENDEC)

See

for a

detailed description of the J1850 interface pins.

MISO (Master-in/Slave-out - Input/Output),
MOSI (Master-out/Slave-in - Input/Output),
SCK (Serial Clock - Input/Output),
SS (Slave Select - Input)

These four lines constitute the Serial Peripheral Interface
(SPI) communications port. The MCU can be configured as
a SPI “master” or as a SPI “slave”. In master mode MOSI
and SCK function as outputs and MISO functions as an
input. In slave mode MOSI and SCK are inputs and MISO is
an output.

SS is always an input.

Serial data words are transmitted and received over the
MISO/MOSI lines synchronously with the SCK clock stream.
The word size is fixed at 8-bits. Single buffering is used
which results in an inherent inter-byte delay. The master
device always provides the synchronizing clock.

A low on the

SS line causes the MCU to immediately
assume the role of slave, regardless of it’s current mode.
This allows multi-master systems to be constructed with
appropriate arbitration protocols.

See the detailed discussion of the SPI interface under

Peripheral Interface (SPI)

.

Serial

Integrated Hardware I/O Functions

PORT A

Each of the Parallel Port pins of Port A may be individually
programmed as an input or an output under software control.
The direction of each pin is determined by the state of the
corresponding bit in the Port A Data Direction Register
(DDRA, location $04).

V

DD

PORT DATA

PORT DRR

INTERNAL LOGIC

P

PAD

N

DAT A

DIR REG

BIT

LATCHED

OUTPUT

DATA BIT

INTERNAL CONNECTIONS

FIGURE 5B. PORT A FUNCTIONAL BLOCK DIAGRAM

76543210

DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0

PORT A DATA DIRECTION REGISTER (DDRA, LOCATION $04)

INPUT REG BIT

OUTPUT

INPUT I/O

I/O

PIN

Any Port A pin is configured as an output if its corresponding
DDR bit is set to a logic one. A pin is configured as an input if
its corresponding DDR bit is cleared to a logic zero. Any
reset will clear all DDR bits, which configures all Port A and
D pins as inputs. The data direction register is capable of
being written to or read by the processor. Refer to Figure 5
and Table 1.

76543210

A7 A6 A5 A4 A3 A2 A1 A0

PORT A DATA REGISTER (PORTA, LOCATION $00)

Port A is an 8-bit wide read-write data register. Regardless
of the state of the DDRA bits, all Port A data latches are
modified with each write to Port A. When Port A is read, the
value read for bits progr ammed as outputs , is the contents of
the data latch, not the pin. The value read for bits pro­grammed as inputs is the value on the pin.

TABLE 1. PORT A TRUTH TABLE

(NOTE 1)

R/W DDR I/O PIN FUNCTION

W 0 The I/O pin is in input mode.

Data is written into the output data latch

W 1 Data is written into the output data latch

and simultaneously output to the I/O pin.
R 0 The state of the I/O pin is read.
R 1 The I/O pin is in output mode.

The output data latch is read.

NOTE:

1. R/W is an internal signal which equals R when reading the Port
Data Register and equals W when writing the Port Data Register.

PD0-PD4 SPECIAL FUNCTION I/O LINES

These five lines comprise Port D. The five lines can be indi­vidually programmed to provide input or output capabilities
similar to the eight Port A lines. Additionally, each of the lines

FIGURE 5A. PORT A I/O PAD CIRCUITRY

11

HIP7030A2

can be programmed to provide special capabilities, beyond
the standard digital input and output functions. The PD0­PD4 I/O lines are controlled via three read/write registers.

76543210
0 0 0 DD4 DD3 DD2 DD1 DD0

PORT D DATA DIRECTION REGISTER (DDRD, LOCATION $07)

DDRD contains five data direction bits, DD0-DD4, which
control whether the associated I/O line behaves as an Input
or as an Output. Setting a data direction bit causes the
related I/O line to be configured as an output, while clearing
the bit causes the line to be configured as an input. When
configured as an output, the I/O line is actively driven by the
HIP7030A2. When configured as an input, the I/O line
appears as a high impedance input and should be driven by
external circuitry.

DDRD bits D0-D4 are cleared by RESET.

7 6 5 43210

CMP3 CMP2 0 D4 D3 D2 D1 D0

PORT D DATA REGISTER (PORTD, LOCATION $03)

PortD is an 8-bit wide register with 5 read/write data bits and
2 read-only bits. When writing to PortD, bits 5-7 are ignored.
All other bits (D0-D4) are stored in latches until they are
explicitly modified with a subsequent write (or read-modify­write) instruction. The utilization of bits D0-D4 is dependent
on the value in the associated DDRD bit. If a line is pro­grammed as an input, the value read in PortD (D0-D4) is the
logic level present on the external I/O line. If a line is pro­grammed as an output, the value read in PortD (D0-D4) is
the value last written to the same bit in PortD and that value
is forced onto the corresponding I/O line. The PortD CMP2
and CMP3 read-only input bits indicate the results of the last
analog comparisons (see

tor Inputs

for details on CMP2 and CMP3). PortD bit 5 is

PD2, PD3, PD4 Analog Compara-

always read as a 0.
PortD is not affected by RESET.

76 5 432 1 0
0 0 CMPE 0 0 0 STE1 STE0

PORT D SPECIAL FUNCTION REGISTER (SFRD, LOCATION $08)

SFRD is an 8-bit wide register with 3 read/write control bits.
The Strobe Enable 0 and 1-bits (STE0 and STE1) and used
to configure PD0 and PD1 as strobed outputs. STE0 and
STE1 only affect PD0 and PD1 when they are programmed
as outputs by setting the corresponding bits in DDRD. See

PD0, PD1 Strobed Outputs

for a detailed explanation. The
Comparator Enable bit (CMPE) controls the HIP7030A2’s
auto-zeroing, analog comparator (see

log Comparator Inputs

for details on CMPE). SFRD bits 2, 3,

PD2, PD3, PD4 Ana-

4, 6 and 7 are always read as a 0.
SFRD bit CMPE, is cleared by RESET. All other SFRD bits

are unaffected by RESET.

PD0, PD1 Strobed Output Mode

(DD0/DD1) is set, setting the STE0/1-bit configures the
PD0/1 output in strobed mode. Clearing the STE0/1-bit
causes the PD0/1 output to function identically to a PortA
line in output mode. If the DDRD direction bit is clear, the
associated line functions as an input and the state of the
STE bit has no effect. When programmed as strobed out­puts, data written to Port D Data Register bits 0 and 1 will
appear on the external PD0 and PD1 pins synchronously
with a low to high transition on the TCAP pin. This same
transition on TCAP can be programmed to generate an inter­rupt to the processor. See

Programmable Timer

for details
on using the interrupt capabilities of the TCAP pin. The
strobed output mode of PD0 and PD1, coupled with the
interrupt capability of TCAP, provides a mechanism for syn­chronously passing two bits of data between the HIP7030A2
and an external, asynchronous device.

SFRD

STE0/1

DAT A

DIR REG

BIT

LATCHED

OUTPUT

DATA BIT

TCAP

INTERNAL CONNECTIONS

INPUT REG BIT

FIGURE 6. STROBED OUTPUT BLOCK DIAGRAM (PD0, PD)

STROBE ENABLE

OUTPUT ENABLE

STROBED

OUTPUT

FLIP-FLOP

OUTPUT

A/B

BX

MUX

A

INPUT I/O

I/O
PIN

STE0 and STE1 are not affected by RESET.

TABLE 2. PORT D STROBED OUTPUTS TRUTH TABLE

(NOTE 1)

R/W DDR STE I/O PIN FUNCTION

W 0 X The I/O pin is in input mode.

Data is written into the output data latch.

W 1 0 Data is written into the output data latch

and simultaneously output to the I/O pin.

W 1 1 Data is written into the output data latch

and transferred to the I/O pin on the

next TCAP low to high transition.
R 0 X The state of the I/O pin is read.
R 1 0 The I/O pin is in standard output mode.

The output data latch is read.
R 1 1 The I/O pin is in strobed output mode.

The output data latch is read.

NOTE:

1. R/W is an internal signal which equals R when reading the Port
Data Register and equals W when writing the Port Data Register.

12

HIP7030A2

PD2, PD3, PD4 Analog Comparator Input Mode

When the CMPE bit is low in SFRD PD2, PD3, and PD4
behave as standard bidirectional I/O pins. Each of these
three pins can be programmed as an input pin by setting the
associated DDR bit low. Setting the DDR bit high configures
the pin as an output. When CMPE is set high the three pins
are connected to the appropriate comparator inputs and the
contents of the DDRD doesn’t affect comparator operation.
While it is possible to perform comparisons of the pins when
they are in the output mode (DDR bits are set high) the com­parator result of comparing two equal digital values is not
predictable. The comparator is intended for comparing ana­log input values, in which case the DDR bits must be set low
to configure the pins as inputs. When CMPE is high, all of
the associated PortD digital inputs (bits D4, D3, and D2 of
PortD) are forced to 0, to conserve power.

V

DD

DATA BIT

DRR BIT

DATA BIT

DRR BIT

INTERNAL LOGIC

P

V2/V3

N

V

DD

P

N

VR

1. Auto Zero

2. Compare V2, write results to CMP2

3. Auto Zero

4. Compare V3, write results to CMP3

The hardware sequencer is enabled via the CMPE bit. Once
enabled the compare cycling is performed continuously at a
1MHz step rate until CMPE is set low. A complete cycle
takes 4µs. It follows that, at any given time, the results read
in CMP2 or CMP3 of the PortD Data Register can be, at
most, 4µs old.

The auto-zero operation involves charging a pair of bias
capacitors. The charging time depends on the source imped­ance of the analog inputs, the relative voltages of V2 and V3,
and the slew rate of all three input voltages. Incomplete
charging of the capacitors will affect the accuracy of the
comparator. The comparator is intended to perform favor ab ly
with input impedances up to 10kΩ and moderate slew rates.

J1850 Bus Interface

The VPW Symbol Encoder/Decoder (SENDEC) block pro­vides the design with all the features needed to send and
receive properly timed messages on a J1850 Class B Multi­plexed Bus. Refer to

DEC)

for detailed documentation on the use of the SENDEC.

VPW Symbol Encoder/Decoder (SEN-

16-Bit Timer

The integrated 16-bit Timer includes both capture and com­pare features. External events can be timed, pulses gener­ated, and periodic interrupts programmed. A sophisticated
set of control and status registers allows interrupt or polled
operation. For a detailed guide to the operation of the Timer
refer to

Programmable Timer

.

FIGURE 7. ANALOG INPUT I/O PINS

The circuitry of the clocked comparator consists of a differ­ential amplifier with requisite current sources, auto-zero stor­age elements, and multiplexing switches. It is convenient to
view it as a conventional differential comparator to which
PD4 is connected as a “reference” at the negative input and
PD2 and PD3 are connected via a multiplexer at the positive
input. The comparator is enabled be setting the CMPE bit
(bit 5) of SFRD and disabled by clearing CMPE. To conserve
power the comparator should be disabled when not in use.
RESET clears the CMPE bit. The three analog inputs func­tion properly with inputs from -0.3V to V

DD

+0.3V.

In order to use the comparator, PD4 and either (or both) PD2
or(and) PD3 should be selected as inputs via the DD2, DD3,
and DD4 bits in DDRD. The results of the last comparison
are available each time the PortD register is read. The CMP2
bit of PortD is set if PD2 was greater than PD4 during the
last comparison and cleared otherwise. Similarly, the CMP3
bit of PortD is set if PD3 was greater than PD4 during the
last comparison and cleared otherwise. CMP2 and CMP3
are not affected by RESET.

The HIP7030A2 includes a hardware sequencer to control
the auto-zero function and input multiplexer of the compara­tor. Each complete compare cycle consists of a series of:

Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) is a synchronous serial
interface with separate input, output, and clock lines. The
SPI uses the MISO (serial data input/output), MOSI (serial
data output/input), SCK (serial clock), and SS (slave select)
pins. Refer to

Serial Peripheral Interface

for a detailed dis-

cussion of the SPI system.

Memory Organization

The HIP7030A2 MCU is capable of addressing 8192 bytes
of memory and I/O registers with its program counter. The
MCU has implemented 2520 bytes of these locations as
shown in Figure 8. The first 256 bytes of memory (page
zero) include: 24 bytes of I/O features such as data ports,
the port DDRs, Timer, serial peripheral interface (SPI), and
J1850 VPW Registers; 48 bytes of user ROM, and 176 bytes
of RAM. The next 2048 bytes complete the user ROM. The
Built-In-Test ROM (228 bytes) and Built-In-Test vectors (14
bytes) are contained in memory locations $1F00 through
$1FF1. The 14 highest address bytes contain the user
defined reset and the interrupt vectors. Eight bytes of the
lowest 32 memory locations are unused and the 176 bytes of
user RAM include up to 64 bytes for the stack. Since most
programs use only a small part of the allocated stack loca­tions for interrupts and/or subroutine stacking purposes, the
unused bytes are usable for program data storage.

13

HIP7030A2

CPU Registers

The CPU contains five registers, as shown in the program­ming model of Figure 9. The interrupt stacking order is
shown in Figure 10.

Accumulator (A)

The accumulator is an 8-bit general purpose register used to
hold operands, results of the arithmetic calculations, and
data manipulations.

Index Register (X)

The X register is an 8-bit register which is used during the
indexed modes of addressing. It provides an 8-bit value
which is used to create an effective address. The index reg­ister is also used for data manipulations with the read-mod­ify-write type of instructions and as a temporary storage
register when not performing addressing operations.

Program Counter (PC)

The program counter is a 13-bit register that contains the
address of the next instruction to be executed b y the processor .

Stack Pointer (SP)

The stack pointer is a 13-bit register containing the address
of the next free locations on the pushdown/popup stack.
When accessing memory, the most significant bits are per­manently configured to 0000011. These bits are appended
to the six least significant register bits to produce an address
within the range of $00FF to $00C0. The stack area of RAM
is used to store the return address on subroutine calls and
the machine state during interrupts. During external or
power-on reset, and during a reset stack pointer (RSP)
instruction, the stack pointer is set to its upper limit ($00FF).
Nested interrupt and/or subroutines may use up to 64 (deci­mal) locations. When the 64 locations are exceeded, the
stack pointer wraps around and points to its upper limit
($00FF), thus, losing the previously stored information. A
subroutine call occupies two RAM bytes on the stack, while
an interrupt uses five RAM bytes.

Since the Stack Pointer decrements during pushes, the PCL
is stacked first, followed by PCH, etc. Pulling from the stack
is in the reverse order.

Condition Code Register (CC)

The condition code register is a 5-bit register which indicates
the results of the instruction just executed as well as the
state of the processor. These bits can be individually tested
by a program and specified action taken as a result of their
state. Each bit is explained in the following paragraphs.

Half Carry Bit (H)

The H bit is set to a one when a carry occurs between bits 3
and 4 of the ALU during an ADD or ADC instruction. The H
bit is useful in binary coded decimal subroutines.

Interrupt Mask Bit (I)

When the I-bit is set, all interrupts are disabled. Clearing this
bit enables the interrupts. If an external interrupt occurs
while the I-bit is set, the interrupt is latched and processed

after the I-bit is next cleared; therefore, no interrupts are lost
because of the I-bit being set. An internal interrupt can be
lost if it is cleared while the I-bit is set (refer to Programmable
Timer, Serial Communications Interface, and Serial Periph­eral Interface Sections for more information).

Negative (N)

When set, this bit indicates that the result of the last arith­metic, logical, or data manipulation is negative (bit 7 in the
result is a logic one).

Zero (Z)

When set, this bit indicates that the result of the last arith­metic, logical, or data manipulation is zero.

Carry/Borrow (C)

Indicates that a carry or borrow out of the arithmetic logic
unit (ALU) occurred during the last arithmetic operation. This
bit is also affected during bit test and branch instructions,
shifts, and rotates.

Built-In-Test (BIT)

The BIT test routines utilize the SPI interface of the
HIP7030A2 to provide an efficient method to test devices,
both at the component and board level. The BIT routines are
invoked by resetting the HIP7030A2 while applying 9V
(through a 4.7kΩ resistor) to the IRQ pin and 5VDC to the
TCAP pin. After reset, the HIP7030A2 will begin executing
the BIT code stored at locations $1F00-$1FF1. The COP
system remains active during BIT. When the BIT program
begins, the SPI is configured in the master mode. SPI trans­fers are therefore controlled by the HIP7030A2. The tester
paces the transfers by driving the
SPI transfer. When the transfer is complete, the tester raises
IRQ (to 5-9VDC) to signal successful transfer and to prepare
for the next transfer. A convenient means of driving the
pin is to connect it to 9V
drive it with an open-collector/collector device such as the
collector of an NPN device with its emitter grounded.

Following reset, the HIP7030A2 waits for a command to be
received from the tester by monitoring the
SPIF flag in the SSR.
throughout the BIT procedure. If
the BIT routine will immediately branch to location $5D and
begin executing the program stored there.

There are five BIT functions which are accessible via the
SPI. Each is selected by sending the associated command
number to the HIP7030A2. Following completion of each
command (except Command $00), the HIP7030A2 waits for
another command. Commands outside of the range $00-$04
will be ignored.

Download (Command $00):

Download takes 175 bytes from the SPDR and writes them
to RAM beginning at $50 and ending and $FE. After receiv­ing the 175th byte, the program begins executing at location
$5D. The 13 locations $50-$5C are used as a link table to

through a 4.7kΩ resistor and to

DC

SS should normally be held high

IRQ line low to initiate a

IRQ line and the

SS is low following reset,

DC

IRQ

14

HIP7030A2

allow testing of the interrupt functions. The link locations are:
SPI Interrupt $50-51; Timer Interrupt $52-53; IRQ Interrupt
$54-55; SED Interrupt $56-57; COP Interrupt $58-59; SWI
Interrupt $5A-5C. If any entries in the link table are not
required for the downloaded program, they may be used for
variables or subroutines. Interrupts are disabled when exe-

$0000 0000 0000

$001f

$0020

$004F

$0050

$00BF
$00C0

$00FF

$0100

$08FF

$0900

$1EFF

$1F00

$1FE1
$1FE2

$1FF1
$1FF2

$1FFF

I/O

32 BYTES

USER

ROM

48 BYTES

RAM

176 BYTES

STACK

64 BYTES

USER

ROM

2048 BYTES

UNUSED

5632 BYTES

BUILT-IN-TEST

BUILT-IN-TEST

VECTORS

USER
VECTORS
14 BYTES

0031
0032

0079
0080

0191
0192

0255
0256

2303
2304

7935
7936

8177
8178

8191

256 BYTES

PORTS
1 BYTE

UNUSED
2 BYTES

PORTS

2 BYTES
UNUSED

2 BYTES

PORTS

2 BYTES
UNUSED

1 BYTE

SERIAL PERIPHERAL

INTERFACE

3 BYTES
UNUSED

2 BYTES

SENDEC INTERFACE

3 BYTES

TIMER

10 BYTES

UNUSED

1 BYTE

WATCHDOG

2 BYTES
UNUSED

1 BYTE

cution begins. If interrupts are enabled via a CLI instruction,
handling of all interrupts which are generated (including the
NEW interrupt) is required.

Location $5D is always the start location.

0031

PORT A DATA REGISTER

UNUSED
UNUSED

PORT D DATA REGISTER

PORT A DATA DIRECTION REGISTER

UNUSED
UNUSED

PORT D DATA DIRECTION REGISTER

PORT D SPECIAL FUNCTION REGISTER

UNUSED

SERIAL PERIPHERAL CONTROL REGISTER

SERIAL PERIPHERAL STATUS REGISTER

SERIAL PERIPHERAL DATA I/O REGISTER

UNUSED
UNUSED

SENDEC CONTROL REGISTER

SENDEC STATUS REGISTER

SENDEC DATA REGISTER

TIMER CONTROL REGISTER

TIMER STATUS REGISTER

INPUT CAPTURE HIGH REGISTER

INPUT CAPTURE LOW REGISTER

OUTPUT COMPARE HIGH REGISTER

OUTPUT COMPARE LOW REGISTER

COUNTER HIGH REGISTER

COUNTER LOW REGISTER
ALTERNATE COUNTER HIGH REGISTER
ALTERNATE COUNTER LOW REGISTER

UNUSED

WATCHDOG RESET REGISTER

WATCHDOG STATUS REGISTER

UNUSED

$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0A
$0B
$0C
$0D
$0E
$0F
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
$1E
$1F

FIGURE 8. MEMORY MAP OF THE HIP7030A2

15

HIP7030A2

07

A

X

PC

7

1100000

FIGURE 9. CPU REGISTER SET

7

RETURN

11

1

000

PROGRAM COUNTER LOW

INCREASING

MEMORY

ADDRESS

FIGURE 10. STACKING ORDER DURING INTERRUPTS

SP

4

CONDITION CODE REG

ACCUMULATOR (A)

INDEX REGISTER (X)

PROGRAM COUNTER HIGH

ACCUMULATOR

07

INDEX REGISTER

012

PROGRAM COUNTER

012

STACK POINTER

0

CZNIH

CONDITION CODE REG

CARRY/BORROW
ZERO
NEGATIVE
INTERRUPT MASK
HALF CARRY

DECREASING

0

MEMORY

ADDRESS

INTERRUPT

return data is a three character ASCII sequence which
uniquely identifies each customer’s mask ROM pattern.

Resets

The MCU has three reset modes: an active low external
reset pin (
puter Operating Properly (COP) reset function.

RESET Pin

The
orderly software start-up procedure. When using the exter­nal reset mode, the
of one and one half t
nal Schmitt Trigger as part of its input to improve noise
immunity.

Power-On Reset

The power-on reset occurs when a positive transition is
detected on V
power turn-on conditions and should not be used to detect
any drops in the power supply voltage. There is no provision
for a power-down reset. The po wer-on circuitry provides f or a
4064 t
active to allow for stabilization (see Figure 11). If the external
RESET pin is low at the end of the 4064 t
processor remains in the reset condition until
high. Table 3 shows the actions of the two resets on internal
circuits, but not necessarily in order of occurrence (X indi­cates that the condition occurs for the particular reset).

RESET), a power-on reset function, and a Com-

RESET input pin is used to reset the MCU to provide an

RESET pin must stay low for a minimum

. The RESET pin contains an inter-

CYC

. The power-on reset is used strictly for

DD

delay from the time that the oscillator becomes

CYC

time out, the

CYC

RESET goes

ROM Dump (Command $01):

ROM Dump reads the entire ROM contents and transfers
them one byte at a time via the SPI register. The entire ROM
must be read from start to end. Locations $20-$4F, $100­$8FF, and $1F00-$1FFF are read in lowest to highest
address sequence. Following the complete ROM contents, a
two byte checksum is transferred.

Read Page 0 (Command $02):

Allows reading of any page 0 byte (i.e., $00-$FF). The com­mand ($02) is sent, followed by the address, followed by the
data transfer. The data sent is ignored, while the return data
is the contents of the specified address. The three byte
sequence must be repeated for each transfer.

Write Page 0 (Command $03):

Allows writing of any non-ROM, P age 0 b yte (i.e., $00-$1F or
$50-$FF). The command ($03) is sent, followed by the
address, followed by the data transfer. The data is written to
the location, while the return data is the contents of the
specified address. The three byte sequence must be
repeated for each transfer. The procedure will work for ROM
locations identically to all other locations, except the write
will be supressed.

Read Mask ID (Command $04):

Transfers the three character custom mask ID assigned to
each customer pattern. The command ($04) is sent, followed
by three data transfers The data sent is ignored, while the

COP Reset

The COP reset is generated by either of two events: 1) the
Watchdog Timer reaches its maximum value prior to being
cleared, or 2) the Slow Clock Detect circuitry doesn’t detect
a transition on the OSCIN pin during a period of approxi­mately 2µs. The COP reset is identical to an external
RESET pin reset, except the Program Counter is loaded with
the address at $1FFA-$1FFB instead of the address at
$1FFE-$1FFF and the Watchdog Flag (bit 0) is set in the
Watchdog Status Register (WSR, location $1E). COP
Resets are discussed under Interrupts.

Interrupts

Systems often require that normal processing be interrupted
so that some external event may be serviced. The
HIP7030A2 may be interrupted by one of six different meth­ods: either one of four maskable hardware interrupts (
SPI, SENDEC, or Timer), one non-maskable Watch­dog/Slow Clock Detect interrupt, and one non-maskable
software interrupt (SWI). Interrupts such as Timer, SPI, and
SENDEC have several flags which will cause the interrupt.
Generally, interrupt flags are located in read-only status reg­ister, whereas, their equivalent enable bits are located in
associated control registers. The interrupt flags and enable
bits are never contained in the same register. If the enable
bit is a logic zero it blocks the interrupt from occurring but
does not inhibit the flag from being set. Reset clears all
enable bits to preclude interrupts during the reset procedure.

IRQ,

16

HIP7030A2

The general sequence for clearing an interrupt is a software
sequence of first accessing the status register while the
interrupt flag is set, followed by a read or write of an associ­ated register. When any of these interrupts occur, and if the
enable bit is a logic one, normal processing is suspended at
the end of the current instruction execution. Interrupts cause
the processor registers to be saved on the stack (see Figure

12) and the interrupt mask (I-bit) set to prevent additional
interrupts. The appropriate interrupt vector then points to the
starting address of the interrupt service routine (refer to
Table 4 for vector location). Upon completion of the interrupt
service routine, the RTI instruction (which is normally a part
of the service routine) causes the register contents to be

Hardware Controlled Interrupt Sequence

The following three functions (RESET, STOP, and WAIT) are
not in the strictest sense an interrupt; however, they are
acted upon in a similar manner. Flowcharts for hardware
interrupts are shown in Figure 13, and for STOP and WAIT
are provided in Figure 14. A discussion is provided below.

(a) RESET - A low input on the

RESET input pin causes the
program to vector to its starting address which is specified
by the contents of memory locations $1FFE and $1FFF. The
I bit in the condition code register is also set. Much of the
MCU is configured to a known state during this type of reset
as previously described in RESETS paragraph.

recovered from the stack followed by a return to normal pro­cessing. The stack order is shown in Figure 12.

NOTE: The interrupt mask bit (I-bit) will be cleared if and only
if the corresponding bit stored in the stack is zero. A discus­sion of interrupts, plus a table listing vector addresses for all
interrupts including RESET, in the MCU is provided in Table 4.

TABLE 3. RESET PIN, COP, AND POR ACTIONS ON INTERNAL CIRCUITRY

RESET PIN/

CONDITION

Timer Prescaler Reset to Zero State X X
Timer Counter Configure to $FFFC X X
Timer Output Compare (TCMP) Bit Reset to Zero X X
All Timer Interrupt Enable Bits Cleared (ICIE, OCIE, and TOIE) to Disable Timer Interrupts X X
Timer Output Level (OLVL) Bit is Cleared X X
Port A and Port D Data Direction Registers (DDRA and DDRD) Cleared to Zero, Placing

all Port Pins in Input Mode
Port D Special Function Register Bit CMPE is Cleared Disabling Comparator X X
Set Stack Pointer (SP) to $00FF X X
Force Internal Address to RESET Vector ($1FFE) X X
Set I-Bit in Condition Code Register (CC) to 1; Disabling all Maskable Interrupts X X
Clear STOP Latch XX
Clear WAIT Latch XX
Reset Oscillator Stabilization Delay to 4064 (Note 1) X
Clear External Interrupt (Irq) Flip-flop X X
VPWOUT Set Low (Passive State) X X
Slow Clock Detect Circuitry Reset (Note 1) X
Watchdog Timer Reset to Zero State X X
Watchdog Flag (WDF) Cleared/Set in Watchdog Status Register (WSR) (Note 2) (Note 2)
Watchdog Timer Interrupt Latch Cleared X X
Serial Peripheral Interface (SPI) Control Bits SPIE, MSTR, SPIF, WCOL, and MODF

Cleared; Disabling SPI Interrupts and Setting to Slave Mode

NOTES:

1. Only if MCU is in STOP state; if NDEL is set in the SENDEC Control Register a delay of 128 is used for RESET/COP.

2. WDF is cleared by POR and is set by a Watchdog Reset. RESET has no effect on WDF.

COP RESET

XX

XX

POWER-ON

RESET

17