Intersil Corporation HIP7030A0 Datasheet

HIP7030A0

PRELIMINARY

April 1994

Features

• HIP7030A2 Microcontroller Emulation

- All HIP7030A2 Hardware and Software Features

- Timing and Performance Equivalent to HIP7030A2

• On-Chip Memory

- 176 Bytes of RAM - No ROM

• Full 8K Byte Address Space Available Externally

• Non-Multiplexed External Address and Data Lines

- I/O Memory Interface Matches Industry Standard
EPROM/EEPROMS for True Emulation with Two
Chips

• FS Line Identifies Fetch Cycles for Breakpoint Logic

o

C to +125oC Operating Range

• -40

• Single 3.0V to 6.0V Supply

• Available in 68 Lead PLCC Packages

J1850 8-Bit 68HC05 Microcontroller

Emulator Version

Description

The HIP7030A0 Emulator is functionally equivalent to the
HIP7030A2 microcontroller with the addition of external data
bus, address bus, and control signals which provide off chip
address capability. It is designed to permit prototype and
pre-production development of systems for mask pro­grammed applications. The HIP7030A0 is also intended for
construction of development systems for the HIP7030A2.

Ordering Information

TEMPERATURE

PART NUMBER

HIP7030A0M -40oC to +125oC 68 Lead Plastic LCC

RANGE PACKAGE

Pinout

NC
NC

WE

DS

ALC

PD4
PD3
PD2
PD1
PD0

NC
NC

V

SCOUT

OSCIN

SCK

MOSI

HIP7030A0 (PLCC)

TOP VIEW

CE

FSRDA0A1A2A3A4A5A6A7A8A9A10

NC

NC

123456789

6867666564636261

10
11
12
13
14
15
16
17
18
19
20
21
22

SS

23
24
25
26

27282930313233

NCNCNCNCNC

SS

MISO

TCAP

TCMP

VPWIN

VPWOUT

IRQ

RESET

A11

A12

60

NC

59

DB0

58

DB1

57

DB2

56

DB3

55

DB4

54

DB5

53

DB6

52

DB7

51

OSCB

50

PA0

49

PA1

48

PA2

47

PA3

46

PA4

45

PA5

44

43424140393837363534

DD

NC

PA6

PA7

V

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
407-727-9207

| Copyright © Intersil Corporation 1999

9-40

File Number

3645

Block Diagram

HIP7030A0

34

TCAP

49

PA0

48

PA1

47

PA2

46

PA3

45

PA4

44

PA5

43

PA6

PORT A I/O LINES

PD2, V2
PD3, V3

PD4, VR

PORT D I/O LINES

PA7

PD0
PD1

TCAP

DS

WE

CE

FS

RD

ALC

42

19
18
17
16

15

13
12

14

TCMP OSCIN OSCOUT

35

TIMER SYSTEM

9
6

5

PORT D

REG
+

-

+

-

BUS

CONTROL

VSS22
VDD7

PORT

A

REG

PORT D

SFR

REG

DATA

DIR

REG

PORT D

DIR

REG

58575655545352

DB0

DB1

DB2

DB3

INTERNAL

PROCESSOR

CLOCK

ACCUMULATOR

8

INDEX

REGISTER

8

CONDITION CODE

5

REGISTER

STACK

6

POINTER

PROGRAM

COUNTER HIGH

5

PROGRAM

8

COUNTER LOW

51

DB4

DB5

DB6

OSCILLATOR

AND

A

X

CC

S

PCH

PCL

STATIC RAM

49484746454443

A0A1A2A3A4A5A6

DB7

÷ 2

ADDRESS DRIVEBUS DRIVE

176 x 8

2324

50

CPU

CONTROL

CPU

ALU

42

A7

OSCB

INTERNAL PROCESSOR CLOCK

WATCHDOG AND

SLOW CLOCK DETECT

4948474645

A8

38
39

SYMBOL INT

VPW SYMBOL

ENCODER /

DECODER

ARBITRATION

A9

A10

A11

RESET
IRQ

AND

SPI

SYSTEM

A12

37
36

32
26
25
33

VPWOUT
VPWIN

SCK
MOSI
MISO
SS

9-41

Specifications HIP7030A0

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V

Input Voltage, VIN (Note 1). . . . . . . . . . . . . (VSS-0.3) to (VDD+0.3)V

Self-Check Mode (IRQ Pin Only), VIN . . (VSS-0.3) to 2•(VDD+0.3)V

Current Drain Per Pin (Excluding VDD and VSS) . . . . . . . . . . 25mA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Resistance θ

JA

Plastic LCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .55oC/W

Maximum Package Power Dissipation, PDat 125oC . . . . . . 450mW

Operating Temperature Range . . . . . . . . . . . . . . . -40oC to +125oC

Storage Temperature Range, T

. . . . . . . . . . . -65oC to +150oC

STG

Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +265oC

Control Timing V

= 5VDC±10%, VSS = 0VDC, TA = -40oC to +125oC Unless Otherwise Specified.

DD

PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNITS

FREQUENCY OF OPERATION

Crystal Option f

OSC

1 - 10 MHz

External Clock Option 1 - 10 MHz

INTERNAL OPERATING FREQUENCY

Crystal (f

External Clock (f

Cycle Time t

DC Electrical Specifications V

+ 2) f

OSC

+ 2) 0.5 - 5 MHz

OSC

OP

CYC

= 5VDC±10%, VSS = 0VDC, TA = -40oC to +125oC Unless Otherwise Specified.

DD

0.5 - 5 MHz

200 - - ns

PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNITS

I

Output Voltage V

Output High Voltage:

OL

V

OH

V

OH

< 10mA - - 0.1 V

LOAD

I

> -10mA VDD -0.1 - - V

LOAD

I

= 0.8mA VDD -0.8 - - V

LOAD

A0-A12, DB0-DB7, CE, RD, WE, FS
Output Low Voltage:

A0-A12, DB0-DB7, CE, RD, WE, FS
Input High Voltage: DB0-DB7 V
Input Low Voltage: DB0-DB7 V
DB0-7 High Impedance Leakage

V

OH

IH

IL

I

IL

I

= 1.6mA - -

LOAD

- 0.5•V

0.3•V

-10 - +10 µA

DD

V

V

DD

0.4

0.7•V

DD

--V

Current:
Input Current I
Capacitance C

Supply Current: RUN I

IN

OUT

C

RUN

IN

-1 - +1 µA

- - 12 pF

--8pF

- 8 TBD mA

NOTES:

1. This device contains circuitry to protect the inputs against damage due to high static voltages of electric fields; however, i t is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For
proper operation it is recommended that VIN and V

be constrained to the range VSS ≤ (VIN or V

OUT

) ≤ VDD. Reliability of operation is

OUT

enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either VSS or VDD)

2. Characteristics are listed for the signals unique to the Emulator IC. For details on the other signal pins see the HIP7030A2 data sheet.

3. Minimum frequency applies when ALC is low.

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