intersil HIP6521 DATA SHEET

TM

HIP6521

Data Sheet August 2000

PWM and Triple Linear Power Controller

The HIP6521 provides the power control and protection for
four output voltages in high-performance microprocessor
and computer applications. The IC integrates a voltage­mode PWMcontroller and three linear controllers, as well as
monitoring and protection functions into a 16-lead SOIC
package. The PWM controller is intended to regulate the
microprocessor memory core voltage with a synchronous­rectified buck converter. The linear controllers are intended
to regulate the computer system’s AGP 1.5V bus power,the

2.5V clock power, and the 1.8V power for the North/South
Bridge core voltage and/or cache memory circuits. Both the
switching regulator and linear voltage references provide
±2% of static regulation over line, load, and temperature
ranges. All outputs are user-adjustable by means of an
external resistor divider. All linear controllers employ bipolar
NPNs for the pass transistors.

The HIP6521 monitors all the output voltages. The PWM
controller’s adjustable overcurrent function monitors the
output current by using the voltage drop across the upper
MOSFET’s r

. The linear regulator outputs are

DS(ON)

monitored via the FB pins for undervoltage events.

Ordering Information

PKG.

PART NUMBER TEMP. RANGE (oC) PACKAGE

HIP6521CB 0 to 70 16 Ld SOIC M16.15
HIP6521EVAL1 Evaluation Board

NO.

Applications

•

Motherboard Power Regulation for Computers

File Number 4837.1

Features

• Provides 4 Regulated Voltages

- Memory Core, AGP, Clock, and Memory Controller Hub
Power

• ACPI Compatible

• Drives Bipolar Linear Pass Transistors

• Externally Resistor-Adjustable Outputs

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

• Fast PWM Converter Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Ratio

• Excellent Output Voltage Regulation

- All Outputs: ±2% Over Temperature

• Overcurrent Fault Monitors

- Switching Regulator Does Not Require Extra Current
Sensing Element, Uses MOSFET’s r

DS(ON)

• Small Converter Size

- 300kHz Constant Frequency Operation

- Small External Component Count

Related Literature

• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”

Pinout

HIP6521 (SOIC)

TOP VIEW

16
15
14
13
12
11
10

9

FB3
DRIVE3
FB4
DRIVE4
OCSET
VCC
LGATE
PGND

DRIVE2

FB2

FB

COMP

GND

PHASE

BOOT

1
2
3
4
5
6
7
8UGATE

1

1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Block Diagram

VCC

VCC

FB3

OCSET

2

DRIVE3

DRIVE4

FB4

DRIVE2

FB2

EA3

-

+

EA4

+

-

0.8V

INHIBIT/SOFT-START

+

-

EA2

-

+

x 0.70

+

UV3

+

-

UV4

40µA

-

SOFT-

START

AND FAULT

+

-

UV2

LOGIC

+

-

EA1

+

-

COMP1

OCC

+

+

-

-

PWM

POWER-ON

RESET (POR)

HIP6521

BOOT

DRIVE1

UGATE

PHASE

GATE

CONTROL

VCC

GND

OSCILLATOR

FB

COMP

SYNC

DRIVE

LGATE

PGND

Simplified Power System Diagram

HIP6521

+5VSB (+5V

+5V

+3.3V

DUAL

DUAL

)

IN

Typical Application

+5V

SB

+5V

DUAL

L

IN

V

V

OUT3

OUT2

C

IN

Q1

Q3

+

Q4

+

+

LINEAR

CONTROLLER

LINEAR

CONTROLLER

VCC

HIP6521

PWM

CONTROLLER

LINEAR

CONTROLLER

Q2

Q5

+

+

V

OUT4

V

OUT1

V

2.5V

+3.3V

+3.3V

OUT2

DUAL

V

OUT3

1.8V

V

OUT4

1.5V

IN

DRIVE2

Rp2

DRIVE3

Rp3

DRIVE4

FB2

HIP6521

FB3

FB4

GND

C

C

OUT3

OUT4

Q3

OUT2

Rs4

Rs2

Rs3

Rp4

+

C

Q4

+

Q5

+

BOOT

OCSET

UGATE
PHASE

LGATE
PGND

FB

COMP

Q1

Q2

C

CR1

Rp1

BOOT

L

OUT1

C

OUT1

Rs1

V

OUT1

2.5V

+

3

HIP6521

Absolute Maximum Ratings Thermal Information

UGATE, BOOT. . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 15V

VCC, PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +7V

DRIVE, LGATE, all other pins . . . . . . . . GND - 0.3V to VCC + 0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD

Operating Conditions

Supply Voltage on VCC. . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 70oC

Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System

Diagrams, and Typical Application Schematic

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Nominal Supply Current I

CC

POWER-ON RESET

Rising VCC Threshold 4.25 - 4.5 V
Falling VCC Threshold 3.75 - 4.0 V

OSCILLATOR AND SOFT-START

Free Running Frequency F
Ramp Amplitude ∆V
Soft-Start Interval T

OSC

OSC
SS

REFERENCE VOLTAGE

Reference Voltage (All Regulators) V

REF

All Outputs Voltage Regulation -2.0 - +2.0 %
LINEAR REGULATORS (OUT2, OUT3, AND OUT4)
Output Drive Current (All Linears) VCC > 4.5V 100 120 - mA
Undervoltage Level (VFB/V

)V

REF

UV

SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER

DC Gain -80- dB
Gain-Bandwidth Product GBWP 15 - - MHz
Slew Rate SR COMP = 10pF - 6 - V/µs

PWM CONTROLLER GATE DRIVERS

UGATE Source I
UGATE Sink I
LGATE Source I
LGATE Sink I

UGATE
UGATE
LGATE
LGATE

PROTECTION

OCSET Current Source I

OCSET

UGATE, LGATE, DRIVE2, DRIVE3, and
DRIVE4 Open

VCC = 5V, V
V

UGATE-PHASE

VCC = 5V, V
V

LGATE

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

-5- mA

275 300 325 kHz

- 1.5 - V

6.25 6.83 7.40 ms

- 0.800 - V

-70- %

= 2.5V - -1 - A

UGATE

= 2.5V - 1 - A

= 2.5V - -1 - A

LGATE

= 2.5V - 2 - A

34 40 46 µA

P-P

4

HIP6521

Functional Pin Descriptions

VCC (Pin 11)

Provide a well decoupled 5V bias supply for the IC to this
pin. This pin also provides the gate bias charge for the lower
MOSFET controlled by the PWM section of the IC, as well as
the base current drive for the linear regulators’ external
bipolar transistors. The voltage at this pin is monitored for
Power-On Reset (POR) purposes.

GND (Pin 5)

Signal ground for the IC. All voltagelevelsaremeasured with
respect to this pin.

PGND (Pin 9)

This is the power ground connection. Tie the synchronous
PWM converter’s lower MOSFET source to this pin.

BOOT (Pin 7)

Connect a suitable capacitor (0.47µF recommended) from
this pin to PHASE. This bootstrap capacitor supplies UGATE
driver the energy necessary to turn and hold the upper
MOSFET on.

OCSET (Pin 12)

Connect a resistor from this pin to the drain of the upper
PWM MOSFET. This resistor, an internal 40µA current
source (typical), and the upper MOSFET’s on-resistance set
the converter overcurrent trip point. An overcurrent trip
cycles the soft-start function.

The voltage at this pinis monitored for power-on reset (POR)
purposes and pulling this pin below 1.25V with an open
drain/collector device will shutdown the switching controller.

PHASE (Pin 6)

Connect the PHASE pin to the PWM converter’s upper
MOSFET source. This pin is used to monitor the voltage
drop across the upper MOSFET for overcurrent protection.

UGATE (Pin 8)

Connect UGATE pin to thePWM converter’supper MOSFET
gate. This pin provides the gate drive for the upper MOSFET.

LGATE (Pin 10)

Connect LGATE to the PWM converter’s lower MOSFET
gate. This pin provides the gate drive for the lower MOSFET.

COMP and FB (Pins 4, 3)

COMP and FB are the available external pins of the PWM
converter error amplifier. The FB pin is the inverting input of the
error amplifier. Similarly, the COMP pin is the error amplifier
output. These pins are used to compensate the voltage-mode
control feedback loop of the synchronous PWM conv erter .

DRIVE2, 3, 4 (Pins 1, 15, 13)

Connect these pins to the base terminals of external bipolar
NPN transistors. These pins provide the base current drive
for the regulator pass transistors.

FB2, 3, 4 (Pins 2, 16, 14)

Connect the output of the corresponding linear regulators to
these pins through properly sized resistor dividers. The
voltage at these pins is regulated to 0.8V. These pins are
also monitored for undervoltage events.

Quickly pulling and holding any of these pins above 1.25V
(using diode-coupled logic devices) shuts off the respective
regulators. Releasing these pins from the pull-up voltage
initiates a soft-start sequence on the respective regulator.

Description

Operation

The HIP6521 monitors and precisely controls 4 output
voltage levels (Refer to Block and Simplified Power System
Diagrams, and Typical Application Schematic). It is
designed for microprocessor computer applications with

3.3V, and 5V (5V
supply. The IC has a synchronous PWM controller and
three linear controllers. The PWM controller (PWM) is
designed to regulate the 2.5V memory voltage (V
The PWM controller drives 2 MOSFETs (Q1 and Q2) in a
synchronous-rectified buck converter configuration and
regulates the output voltage to a level programmed by a
resistor divider. The linear controllers are designed to
regulate three more of the computer system’s voltages,
typically the 1.5V AGP bus (V
(V
linear controllers are designed to employ external NPN
bipolar pass transistors.

), and the 1.8V ICH/MCH core voltage (V

OUT2

Initialization

The HIP6521 automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltage. The POR monitors
the bias voltage at the VCC pin. The POR function initiates
soft-start operation after the bias supply voltage exceeds its
POR threshold.

Soft-Start

The POR function initiates the soft-start sequence. The
PWM error amplifier reference input is clamped to a level
proportional to the soft-start voltage.Asthe soft-start voltage
slews up, the PWM comparator generates PHASE pulses of
increasing width that charge the output capacitor(s).
Similarly, all linear regulators’ reference inputs are clamped
to a voltage proportional to the soft-start voltage. The ramp­up of the internal soft-start function provides a controlled
output voltage rise.

Figure 1 shows the soft-start sequence for the typical
application. At T0 the +5V
(closely followed b y the +5V
POR threshold at time T1. On the PWM section, the oscillator’s
triangular waveform is compared to the clamped error amplifier

) bias input from an ATX power

DUAL

), the 2.5V clock voltage

OUT4

bias voltage starts to ramp up

SB

voltage) crossing the 4.5V

DUAL

OUT1

OUT3

).

). All

5

HIP6521

output voltage. As the internal soft-start voltage increases, the
pulse-width on the PHASE pin increases to reach its steady­state duty cycle at time T2. At time T3, the 3.3V input supply
starts ramping up; as a result, V

OUT2

and V

OUT4

start ramping
up on the second attempt (approximately3.25 SS cycles wait),
at time T4. During the interval between T4 and T5, the linear
controller error amplifiers’ references ramp to the final value
bringing all outputs within regulation limits.

+5V

+3.3V

DUAL

DUAL

V

OUT1

+3.3V

(2.5V)

V

OUT3

IN

(1.8V)

V

V

OUT2

OUT4

(2.5V)

(1.5V)

0V

+5V

SB

(1V/DIV)

overcurrent event, resulting in an UV condition. Similarly,
after three soft-start periods, the fourth cycle initiates a
ramp-up of this linear output at time T3. One soft-start period
after T3, the linear output is within regulation limits. UV
glitches less than 1µs (typically) in duration are ignored.

V

(2.5V)

OUT1

V

(1.8V)

OUT3

V

(1.5V)

OUT4

V

(2.5V)

OUT2

(0.5V/DIV.)

0V

UV MONITORING

SOFT-START

FUNCTION

INACTIVE

T1 T2

T0

FIGURE2. OVERCURRENT/UNDERVOLTAGEPROTECTION

RESPONSE

TIME

ACTIVE

T3

T4

0V

(0.5V/DIV)

T1 T2

T0 T4

FIGURE 1. SOFT-START INTERVAL

T3

TIME

T5

Overcurrent Protection

All outputs are protected against excessive overcurrents.
The PWM controller uses the upper MOSFET’s
on-resistance, r
against shorted output. All linear controllers monitor their
respectiveFB pins for undervoltage eventsto protect against
excessive currents.

A sustained overload (undervoltage on linears or overcurrent
on the PWM) on any output results in an independent
shutdown of the respective output, followed by subsequent
individual re-start attemptsperformed at an intervalequivalent
to 3 soft-start intervals. Figure 2 describes the protection
feature. At time T0, an overcurrent event sensed across the
switching regulator’ s upper MOSFET (r
triggers a shutdown of the V
internal soft-start initiates a number ofsoft-start cycles. After a
three-cycle wait, the fourth soft-start initiates a ramp-up
attempt of the failed output, at time T2, bringing the output in
regulation at time T4.

To exemplify an UV event on one of the linears, at time T1,
the clock regulator (V

to monitor the current for protection

DS(ON)

DS(ON)

output. As a result, its

OUT1

) is also subjected to an

OUT2

sensing)

As overcurrent protection is performed on the synchronous
switcher regulator on a cycle-by-cycle basis, OC monitoring
is active as long as the regulator is operational. Since the
overcurrent protection on the linear regulators is performed
through undervoltage monitoring at the feedback pins (FB2,
FB3, and FB4), this feature is activated approximately 25%
into the soft-start interval (see Figure 2).

A resistor (R

) programs the overcurrent trip level for

OCSET

the PWM converter. As shown in Figure 3, the internal
40µA current sink (I
R

OCSET(VSET

) that is referenced to VIN. The DRIVE

) develops a voltage across

OCSET

signal enables the overcurrent comparator (OCC). When
the voltage across the upper MOSFET (V
V

, the overcurrent comparator trips to set the

SET

overcurrent latch. Both V
to V

and a small capacitor across R

IN

SET

and V

DS(ON)

OCSET

) exceeds

DS(ON)

are referenced

helps V

OCSET

track the variations of VIN due to MOSFET switching. The
overcurrent function will trip at a peak inductor current
(I

The OC trip point varies with MOSFET’s r

PEAK)

I

PEAK

=

determined by:

I

--------------------------------------------------- -

×

OCSETROCSET

r

DS ON()

DS(ON)

temperature variations. To avoid overcurrent tripping in the
normal operating load range, determine the R

OCSET

resistor from the equation above with:

6

HIP6521

1. The maximum r

2. The minimum I

3. DetermineI

PEAK

DS(ON)
OCSET

at the highest junction temperature.

from the specification table.

for I

PEAK>IOUT(MAX)

+(∆I)/2, where

∆I is the output inductor ripple current.

OVERCURRENT TRIP:

VDSV

>

× I

iDr

DS ON()

OC

OCC

PWM

+

-

CONTROL

FIGURE 3. OVERCURRENT DETECTION

SET

×>

OCSETROCSET

OCSET

I

OCSET

40µA

DRIVE

GATE

R

OCSET

V

VCC

UGATE

PHASE

V

PHASEVINVDS

V

OCSETVINVSET

SET

+

VIN = +5V

i

D

+

V

DS(ON)

–=

–=

For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.

regulators have to meet the following criteria: their value
while in a parallel connection has to be less than 5kΩ, or
otherwise said, the following relationship has to be met:

RSRP×

----------------------

R

SRP

5kΩ<

+

There may be a second restriction on the size of the
resistors used to set the linear regulators’ output voltage
based on ACPI functionality. Read the ‘ACPI
Implementation’ section under ‘Application Guidelines’ to
see if this additional constraint concerns your application. To
ensure the parallel combination of the feedback resistors
equals a certain chosen value, R

, use the following

FB

equations:

V

OUT

--------------- -

R

R

V

S

P

OUT

×=

R

FB

FB

, where

–

V

RSVFB×

-------------------------------- -=

V

OUTVFB

- the desired output voltage,

VFB - feedback (reference) voltage, 0.8V.

Output Voltage Selection

The output voltage of the PWM converter can be resistor­programmed to any level between V
since the value of R

is affecting the values of the rest of

S1

the compensation components, it is advisable its value is
kept between 2kΩ and 5kΩ.

3.3V

IN

Q4

V

OUT3

R

S3

R

S4

R

P4

V

C

V

OUT4

C

OUT

OUT3

OUT4

+

Q5

+

0.8 1

R



S

--------+

×=



R



P

FIGURE 4. ADJUSTING THE OUTPUT VOLTAGE OF ANY OF

THE FOUR REGULATORS (OUTPUTS 3 AND 4
PICTURED)

All linear regulators’ output voltages are set by means of
external resistor dividers as shown in Figure 4. The two
resistors used to set the voltage on each of the three linear

and 0.8V. However,

IN

DRIVE3

FB3

R

P3

DRIVE4

FB4

HIP6521

Application Guidelines

Soft-Start Interval

The soft-start function controls the output voltages rate of rise
to limit the current surge at start-up. The soft-start function is
integrated on the chip and the soft-start interval is thus fixed.

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. The voltage
spikes can degrade efficiency,radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turn­off transition of the upper PWM MOSFET. Prior to tur n-off,
the upper MOSFET was carrying the full load current.
During the turn-off, current stops flowing in the upper
MOSFET and is picked up by the lower MOSFET or
Schottky diode. Any inductance in the switched current
path generates a large voltage spike during the switching
interval. Careful component selection, tight layout of the
critical components, and short, wide circuit traces minimize
the magnitude of voltage spikes. See the Application Note
AN9908 for evaluation board drawings of the component
placement and printed circuit board.

There are two sets of critical components in a DC-DC
converter using a HIP6521 controller. The switching power
components are the most critical because they switch large
amounts of energy, and as such, they tend to generate

7

HIP6521

equally large amounts of noise. The critical small signal
components are those connected to sensitive nodes or
those supplying critical bypass current.

The power components and the controller IC should be
placed first. Locate the input capacitors, especially the high­frequency ceramic decoupling capacitors,close to the power
switches. Locate the output inductor and output capacitors
between the MOSFETs and the load. Locate the PWM
controller close to the MOSFETs.

L

+5V

V

V

IN

IN

+

Q4

Q3

+12V

C

VCC

DRIVE2

HIP6521

DRIVE3

PGND

GNDVCC

OCSET

UGATE

PHASE

LGATE

DRIVE4

C

IN

OUT2

+

C

OUT2

LOAD

OUT3

+

C

OUT3

LOAD

+3.3V

IN

KEY

ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE

C

OCSET

Q2

Q5

R

OCSET

Q1

L

C

CR1

C

OUT

OUT1

OUT4

V

OUT1

+

V

OUT4

+

LOAD

FIGURE 5. PRINTED CIRCUIT BOARDPOWER PLANES AND

ISLANDS

The critical small signal components include the bypass
capacitor for VCC and the feedback resistors. Locate these
components close to their connecting pins on the control IC.

A multi-layer printed circuit board is recommended. Figure
5 shows the connections of the critical components in the
converter. Note that the capacitors C

and C

IN

OUT

each
represent numerous physical capacitors. Dedicate one
solid layer for a ground plane and make all critical
component ground connections with vias to this layer.
Dedicate another solid layer as a power plane and break
this plane into smaller islands of common voltage levels.
The power plane should support the input power and
output power nodes. Use copper filled polygons on the top
and bottom circuit layers for the PHASE nodes, but do not
unnecessarily oversize these particular islands. Since the
PHASE nodes are subjected to very high dV/dt voltages,
the stray capacitor formed between these islands and the

LOAD

surrounding circuitry will tend to couple switching noise.
Use the remaining printed circuit layers for small signal
wiring. The wiring traces from the control IC to the
MOSFET gate and source should be sized to carry 2A
peak currents.

PWM Controller Feedback Compensation

The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration
for a PWM voltage-mode controller. Apply the methods and
considerations only to the PWM controller.

Figure 6 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V

) is regulated to the Reference voltage level,0.8V. The

OUT

error amplifier (Error Amp) output (V
the oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V
PHASE node. The PWM wave is smoothed by the output
filter (L

∆V

and CO).

O

OSC

-

+

Z

FB

+

COMP

C1

DRIVER1

SYNC

DRIVER

0.8V

C2

R2

Z

IN

OSC

PWM

COMP

V

E/A

ERROR

AMP

DETAILED COMPENSATION COMPONENTS

-

+

HIP6521

0.8V

FIGURE 6. VOLTAGE-MODEBUCK CONVERTER

COMPENSATION DESIGN

The modulator transfer function is the small-signal transfer
function of V

OUT/VE/A

Gain, given by V

. This function is dominated by a DC

IN/VOSC

, and shaped by the output filter,
with a double pole break frequency at F
F

.

ESR

) is compared with

E/A

V

IN

L

O

PHASE

(PARASITIC)

Z

FB

Z

IN

C3

R3

R

S1

FB

R

P1

and a zero at

LC

IN

C

ESR

at the

+

O

V

OUT

V

OUT

8

HIP6521

Modulator Break Frequency Equations

--------------------------------------- -=

2π L

1

××

OCO

F

ESR

F

LC

The compensation network consists of the error amplifier
(internal to the HIP6521) and the impedance networks Z
and ZFB. The goal of the compensation network is to provide
a closed loop transfer function with high 0dB crossing
frequency (f

) and adequate phase margin. Phase margin

0dB

is the difference between the closed loop phase at f
180 degrees. The equations below relate the compensation
network’spoles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 6. Use these guidelines for
locating the poles and zeros of the compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth

2. Place 1

3. Place 2

4. Place 1

5. Place 2

ST

Zero Below Filter’s Double Pole (~75% FLC)

ND

Zero at Filter’s Double Pole

ST

Pole at the ESR Zero

ND

Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

1

-----------------------------------------=

2π ESR C

××

O

IN

and

0dB

Compensation Break Frequency Equations

F

F

Z1

Z2

1

-----------------------------------=

2π R× 2C1×

----------------------------------------------------------=

2π RS1R3+()C3××

1

F

F

P1

P2

-------------------------------------------------------=

2π R

-----------------------------------=

2π R× 3C3×

Figure 7 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high
gain peak dependent on the quality factor (Q) of the output
filter, which is not shown in Figure 6. Using the above
guidelines should yield a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the log-log graph of Figure 10 by
adding the Modulator Gain (in dB) to the Compensation Gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.

The compensation gain uses external impedance networks
Z

and ZINto provide a stable, high bandwidth (BW) overall

FB

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.

1

C1 C2×



----------------------

××

2



C1 C2+

1

P2

F



R2

------------ -

log



R



GAIN

Z1

S1

FLCF

100

80

60

40

20

GAIN (dB)

0

20

-20
MODULATOR

-40

-60

FIGURE 7. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

F

F

Z2

ESR

FREQUENCY (Hz)

F

P1

P2

OPEN LOOP

ERROR AMP GAIN

V



IN

------------

20

log



V



PP

COMPENSATION

GAIN

CLOSED LOOP

GAIN

10M1M100K10K1K10010

ACPI Implementation

The three linear controllers included within the HIP6521 can
independently be shut down, in order to accommodate
Advanced Configuration and Power Interface (ACPI) power
management features.

To shut down any of the linears, one needs to pull and keep
high the respective FB pin above a typical threshold of

1.25V. One way to achieve this task is by using a logic gate
coupled through a small-signal diode. The diode should be
placed as close to the FB pin as possible to minimize stray
capacitance to this pin. Upon turn-off of the pull-up device,
the respective output undergoes a soft-start cycle, bringing
the output within regulation limits. On the regulators
implementing this feature, the parallel combination of the
feedbackresistors has to be sufficiently high to allow ease of
driving from the external device. Considering the other
restriction applying to the upper range of this resistor
combination (see ‘Output Voltage Selection’ paragraph), it is
recommended the values of the feedback resistors on an
ACPI-enabled linear regulator output meet the following
constraint:

RSRP×

----------------------

2kΩ

R

SRP

To turn off the switching regulator, use an open-drain or
open-collector device capable of pulling the OCSET pin (with
the attached R
possibility of OC trips at levels different than predicted, a
C

OCSET

larger than the output capacitance of the pull-down device,
has to be used in parallel with R
Upon turn-off ofthe pull-down device, the switching regulator
undergoes a soft-start cycle.

5kΩ<<

+

OCSET

pull-up) below 1.25V. To minimize the

capacitor with a value of an order of magnitude

(1nF recommended).

OCSET

Important

If the collector voltage to a linear regulator pass transistor
(Q3, Q4, or Q5) is lost, the respective regulator has to be

9

HIP6521

shut down by pulling high its FB pin (i.e., when an input
power rail shuts down as a result of entering a sleep state,
the affected regulator’s FB pin has to be pulled high). This
measure is necessary in order to avoid possible damage to
the HIP6521 as a result of overheating. Overheating can
occur in such situations due to sheer power dissipation
inside the chip’s output linear drivers.

Component Selection Guidelines

Output Capacitor Selection

The output capacitors for each output have unique
requirements. In general, the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converters require an output capacitor
to filter the current ripple. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.

PWM Output Capacitors

Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the
transient current and slow the load rate-of-change seen by
the bulk capacitors. The bulk filter capacitor values are
generally determined by the ESR (effective series
resistance) and voltage rating requirements rather than
actual capacitance requirements.

High frequency decoupling capacitors should be placed as
close to the power pins of the load as physicallypossible.Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.

Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage
and the initial voltage drop following a high slew-rate
transient’s edge. An aluminum electrolytic capacitor’s ESR
value is related to the case size with lower ESR available in
larger case sizes.However,the equivalent series inductance
(ESL) of these capacitors increases with case size and can
reduce the usefulness of the capacitor to high slew-rate
transient loading. Unfortunately, ESL is not a specified
parameter. Work with your capacitor supplier and measure
the capacitor’simpedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case
capacitor.

Linear Output Capacitors

The output capacitors for the linear regulators provide
dynamic load current. The linear controllers use dominant
pole compensation integrated into the error amplifier and are
insensitive to output capacitor selection. Output capacitors
should be selected for transient load regulation.

PWM Output Inductor Selection

The PWM converter requires an output inductor. The output
inductor is selected to meet the output voltage ripple
requirements and sets the converter’s response time to a
load transient. The inductor valuedetermines the converter’s
ripple current and the ripple voltage is a function of the ripple
current. The ripple voltage and current are approximated by
the following equations:

∆I

VINV

–

------------------------------- -

F

S

OUT

L×

V

--------------- -

×=

OUT

V

IN

∆ I∆ ESR×=

V

OUT

Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values increase
the converter’s response time to a load transient.

One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6521 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
interval required to slew the inductor current from an initial
current value to the post-transient current level. During this
interval the difference between the inductor current and the
transient current level must be supplied by the output
capacitor(s). Minimizing the response time can minimize the
output capacitance required.

The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:

LOI

×

TRAN

t

RISE

where: I

------------------------------- -=
–

V

INVOUT

is the transient load current step, t

TRAN

t

FALL

response time to the application of load, and t

LOI

×

------------------------------ -=

V

TRAN

OUT

RISE

FALL

is the

is the
response time to the removal of load. Be sure to check both
of these equations at the minimum and maximum output
levels for the worst case response time.

Input Capacitor Selection

The important parameters for the bulk input capacitors are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 of the summation of the DC load current.

Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors can be

10

HIP6521

placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances.

For a through-hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up.

Transistors Selection/Considerations

The HIP6521 requires 5 external transistors. TwoN-channel
MOSFETs are used in the synchronous-rectified buck
topology of PWM converter. The clock, AGP and MCH/ICH
linear controllers each drive an NPN bipolar transistor as a
pass element. All thesetransistors should be selected based
upon r

DS(ON)

, current gain, saturation voltages, gate/base
supply requirements, and thermal management
considerations.

PWM MOSFET Selection and Considerations

In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors.The power dissipation includes two
loss components; conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty factor (see the equations
below). The conduction losses are the main component of
power dissipation for the lower MOSFETs. Only the upper
MOSFET has significant switching losses, since the lower
device turns on and off into near zero voltage.

The equations below assume linear voltage-current
transitions and do not model power loss due to the reverse­recovery of the lower MOSFET’s body diode. The gate­charge losses are dissipated by the HIP6521 and don't heat
the MOSFETs. However, large gate-charge increases the
switching time, t
switchinglosses. Ensure that bothMOSFETs are within their
maximum junction temperature at high ambient temperature
by calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.

P

UPPER

P

LOWER

I

------------------------------------------------------------

I

-------------------------------------------------------------------------------- -=

which increases the upper MOSFET

SW

2

r

× V

O

2

r

× VINV

O

×

DS ON()

V

IN

DS ON()

V

IN

OUT

–()×

I

OVIN

----------------------------------------------------+=

OUT

× tSW× FS×

2

+5V

HIP6521

-

+

BOOT

VCC

C

BOOT

UGATE
PHASE

VCC

LGATE
PGND

GND

FIGURE 8. MOSFET GATE BIAS

+5V OR LESS

+

Q1

Q2

CR1

NOTE:

V

GS

NOTE:
V

GS

≈ V

≈ V

CC

CC

-0.5V

Rectifier CR1 is a clamp that catches the negative inductor
swing during the dead time between the turn off of the lower
MOSFET and the turn on of the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, providing the body diode
is fast enough to avoid excessive negative voltage swings at
the PHASE pin. The diode's rated reverse breakdown
voltage must be greater than the maximum input voltage.

Linear Controllers Transistor Selection

The main criteria for selection of transistors for the linear
regulators is package selection for efficient removal of heat.
The power dissipated in a linear regulator is:

P

LINEARIOVINVOUT

Select a package and heatsink that maintains the junction
temperature below the rating with a the maximum expected
ambient temperature.

As bipolar NPN transistors have to be used with the linear
controllers, insure the current gain at the given operating
V

is sufficiently large to provide the desired maximum

CE

output load current when the base is fed with the minimum
driver output current.

–()×=

Given the reduced available gate bias voltage (5V) logic­level or sub-logic-level transistors have to be used for both
N-MOSFETs. Caution should be exercised with devices
exhibiting very low V

characteristics, as the low gate

GS(ON)

threshold could be conducive to some shoot-through (due to
the Miller effect), in spite of the counteracting circuitry
present aboard the HIP6521.

11

HIP6521

HIP6521 DC-DC Converter Application Circuit

Figure 9 shows an application circuit of a power supply for a
microprocessor computer system. The power supply provides
the system memory voltage (V
(V

), the clock voltage (V

OUT4

voltage(V

+5V

+3.3V

OUT3

DUAL

GND

+3.3V

V

OUT2

(2.5V)

V

OUT3

(1.8V)

V

OUT4

(1.5V)

) from +5V

IN

C8

330µF

DUAL

Q3

FZT649

+

Q4

2SD1802

+

C13
1000µF

+

DUAL

2SD1802

C16

1000µF

), the AGP bus v oltage

OUT1

), and the chip set core

OUT2

. Fordetailed information on the

L1

1.2µH
3x1200µF

R2

12.7K

R4

9.09K

Q5

R9

7.50K

C1-3

DRIVE2

R3

5.90K

DRIVE3

R5

7.15K

DRIVE4

R10

8.45K

+

FB2

FB3

FB4

1

2

15

16

13

14

VCC

11

U1

HIP6521

5

circuit,includinga Bill-of-Materials and circuit board description,
see Application Note AN9908. Also see Intersil’s web page
(www .intersil.com) o r Intersil Ans w erFAX (321-724-7800)
Document No. 99908 for the latest information.

GND

C4
1µF

12

8
6

10

9

3

4

7

OCSET

BOOT

UGATE

PHASE

LGATE
PGND

FB

COMP

C5

1000pF

R1

12K

C15

22nF

D1

MA732

C7

0.47µF

Q1,2

HUF76129D3S

C14

10pF

R7

45.3K

C6
1µF

R8
698

L2

2.5µH

C9-12

4x1000µF

R6

1.50K

+

V

OUT1

(2.5V)

To FB2

S3

S5

To FB4

To OCSET

FIGURE 9. POWER SUPPLY APPLICATION CIRCUIT FOR A MICROPROCESSOR COMPUTER SYSTEM

12

Small Outline Plastic Packages (SOIC)

HIP6521

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45

o

α

e

B

0.25(0.010) C AM BS

M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.

4. Dimension “E”doesnot includeinterleadflash or protrusions.Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The leadwidth“B”, asmeasured 0.36mm(0.014inch) orgreaterabove
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.

A1

C

0.10(0.004)

M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 ­D 0.3859 0.3937 9.80 10.00 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC ­H 0.2284 0.2440 5.80 6.20 ­h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N16 167

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMIN MAX MIN MAX

-

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

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13

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