Intersil Corporation HIP6502B Datasheet

TM

HIP6502B

Data Sheet May 2000 File Number 4871

Multiple Linear Power Controller with
ACPI Control Interface

The HIP6502B complements either an HIP6020 or an
HIP6021 in ACPI-compliant designs for microprocessor and
computer applications. The IC integrates four linear
controllers/regulators, switching, monitoring and control
functions into a 20-pin SOIC package. One linear controller
generates the 3.3V

/3.3VSBvoltage plane from the ATX

DUAL

supply’s 5VSB output, powering the south bridge and the
PCI slots through an external pass transistor during sleep
states (S3, S4/S5). A second transistor is used to switch in
the ATX 3.3V output for operation during S0 and S1/S2
(active) operating states. Two linear controllers/regulators
supply at choice either or both of the computer system’s

2.5V or 3.3V memory power through external pass
transistors in active states. During sleep states, integrated
pass transistors supply the sleep power. Another controller
powers up the 5V

plane by switching in the ATX 5V

DUAL

output in active states, and the ATX 5VSB in sleep states.
One internal regulator outputs a dedicated, noise-free 2.5V
clock chip supply. The HIP6502B’s operating mode (active
outputs or sleep outputs) is selectable through two digital
control pins,
5V

DUAL

state, the 3.3V

S3 and S5. Enabling sleep state support on the

output is offered through the EN5VDL pin. In active

DUAL

and 3.3V

linear regulators use

MEM

external N-channel pass MOSFETs to connect the outputs
directly to the 3.3V input supplied by an ATX (or equivalent)
power supply, for minimal losses. In sleep state, power
delivery on both outputs is transferred to NPN transistors ­external to the controller on the 3.3V

3.3V

. Active state regulation on the 2.5V

MEM

, internal on the

DUAL

MEM

output is
performed through an external NPN transistor. In sleep
state, conduction on this output is transferred to an internal
pass transistor. The 5V

output is powered through two

DUAL

external MOS transistors. In sleep states, a PMOS (or PNP)
transistor conducts the current from the ATX 5VSB output;
while in active state, current flow is transferred to an NMOS
transistor connected to the ATX 5V output. The operation of
the 5V

output is dictated not only by the status of the

DUAL

S3 and S5 pins, but that of the EN5VDL pin as well. The

3.3V
5VSB voltage is applied to the chip. The 2.5V

/3.3VSB output is active for as long as the ATX

DUAL

CLK

output is
only active during S0 and S1/S2, and uses the 3V3 pin as
input source for its internal pass element.

Ordering Information

Features

• Provides 5 ACPI-Controlled Voltages

-5V

- 3.3V

- 2.5V

- 3.3V

- 2.5V

USB/Keyboard/Mouse (Active/Sleep)

DUAL

/3.3VSB PCI/Auxiliary/LAN (Active/Sleep)

DUAL

RDRAM (Active/Sleep)

MEM

SDRAM (Active/Sleep)

MEM

Clock/Processor Terminations (Active Only)

CLK

• Excellent Output Voltage Regulation

- 3.3V

/3.3VSB Output: ±2.0% Over Temperature;

DUAL

Sleep State Only

- 2.5V
Temperature; Both Operational States (3.3V

MEM

and 3.3V

Output: ±2.0% Over

MEM

MEM

in

Sleep Only)

- 2.5V

Output: ±2.0% Over Temperature

CLK

• Small Size

- Very Low External Component Count

• Dual Memory Voltage Support Via MSEL Pin

- 2.5V for RDRAM Memory

- 3.3V for SDRAM Memory

- Both 2.5V and 3.3V for Flexible Systems

• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown

Applications

•

Motherboard Power Regulation for ACPI-Compliant
Computers

Pinout

HIP6502B

(SOIC)

TOP VIEW

VSEN2

5VSB

VSEN1

3V3DLSB

3V3DL

VCLK

3V3

EN5VDL

S3
S5

1
2
3
4
5
6
7
8
9

10

20
19
18
17
16
15
14

13
12
11

MSEL

DRV2

5V

12V
SS
5VDL

5VDLSB
DLA
FAULT
GND

TEMP.

PART NUMBER

HIP6502BCB 0 to 70 20 Ld SOIC M20.3
HIP6502BEVAL1 Evaluation Board

RANGE (oC) PACKAGE

1

1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000

PKG.

NO.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Block Diagram

12V

2

TO 5VSB

12V MONITOR

EA3

10.8V/9.8V

+

3V3DLSB

EA4

-

+

3V3DL

5V

5V MONITOR

4.5V/4.25V

3V3 MONITOR

2.97V/2.8V

3V3

5VSB

5VSB POR

4.4V/3.2V

5VDLSB

DLA

TEMPERATURE

MONITOR

(TMON)

-

TO UV

VSEN1

FAULT

UV DETECTOR

DETECTOR

MONITOR AND CONTROL

TO

UV DETECTOR

+

1.265V

TO 3V3

EA3

+

HIP6502B

-

VCLK

TO 5V

-

5VDL

3.75V

-

+

UV COMPARATOR

+

-

GND

SS

10µA

S3

S5

EN5VDL

FIGURE 1.

MSEL

TO UV

DETECTOR

DRV2

EA2

-

+

VSEN2

Simplified Power System Diagram

+5V

IN

+12V

IN

+5V

SB

+3.3V

IN

Q6

3.3V

MEM

3.3V
Q2

3.3V

DUAL

FAULT

MSEL

SHUTDOWN

SX

EN5VDL

/3.3V

3.3V

SB

Q3

2

Typical Application

HIP6502B

LINEAR

REGULATOR

LINEAR

CONTROLLER

HIP6502B

FIGURE 2.

LINEAR

CONTROLLER

LINEAR

REGULATOR

CONTROL

LOGIC

Q1

2.5V

V

MEM

2.5V

CLK

2.5V

Q5

Q4

5V

DUAL

5V

+5V

IN

+12V

IN

+5V

SB

+3.3V

IN

V

OUT1

3.3V

3.3V

FAULT

SLP_S3
SLP_S5

EN5VDL

MSEL

SHUTDOWN

MEM

V

OUT3

DUAL

/3.3V

Q2

SB

Q6

C

OUT1

C

Q3

OUT3

VSEN1

5V

3V3DLSB

3V3DL

FAULT

S3
S5

EN5VDL

MSEL

SS

C

SS

12V

3V3

HIP6502B

GND

5VSB

DRV2

VSEN2

C

OUT2

VCLK

5VDLSB
DLA

5VDL

C

OUT4

Q1

C

OUT5

Q5

Q4

V

2.5V

2.5V

V

5V

OUT2

V

OUT4

OUT5

DUAL

MEM

CLK

FIGURE 3.

3

HIP6502B

Absolute Maximum Ratings Thermal Information

Supply Voltage, V

12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V

DLA, DRV2. . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V

All Other Pins. . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 5VSB + 0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 3

Recommended Operating Conditions

Supply Voltage, V

Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V

Digital Inputs, VSX,V

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0oC to 70oC

Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3

VCC SUPPLY CURRENT

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V

5VSB

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

+0.3V

12V

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

. . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

5VSB

EN5VDL

, V

. . . . . . . . . . . . . . . 0 to +5.5V

MSEL

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Nominal Supply Current I
Shutdown Supply Current I

5VSB(OFF)VSS

5VSB

= 0.8V - 14 - mA

-30- mA

POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS

Rising 5VSB POR Threshold - - 4.5 V
5VSB POR Hysteresis - 1.0 - V
Rising 12V Threshold - - 10.8 V
12V Hysteresis - 1.0 - V
Rising 3V3 and 5V Thresholds -90- %
3V3 and 5V Hysteresis -5- %
Soft-Start Current I
Shutdown Voltage Threshold V

3.3V

LINEAR REGULATOR (V

MEM

OUT1

)

SS

SD

-10- µA

- - 0.8 V

Sleep State Regulation - - 2.0 %
VSEN1 Nominal Voltage Level V

VSEN1

MSEL > 1.8V - 3.3 - V
VSEN1 Undervoltage Rising Threshold - 2.739 - V
VSEN1 Undervoltage Hysteresis -99- mV
VSEN1 Output Current I

2.5V

LINEAR REGULATOR (V

MEM

OUT2

)

VSEN1

5VSB = 5V 250 300 - mA

Regulation - - 2.0 %
VSEN2 Nominal Voltage Level V

VSEN2

MSEL < 2.0V - 2.5 - V
VSEN2 Undervoltage Rising Threshold - 2.075 - V
VSEN2 Output Current I

VSEN2

5VSB = 5V 250 300 - mA

4

HIP6502B

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

DRV2 Output Drive Current I

3.3V

/3.3VSB LINEAR REGULATOR (V

DUAL

OUT3

DRV2

)

5VSB = 5V 220 - - mA

Sleep State Regulation - - 2.0 %
3V3DL Nominal Voltage Level V

3V3DL

- 3.3 - V
3V3DL Undervoltage Rising Threshold - 2.739 - V
3V3DL Undervoltage Hysteresis -99- mV
3V3DLSB Output Drive Current I

3V3DLSB

5VSB = 5V 5 10 - mA

DLA Output Impedance -90- Ω

2.5V

LINEAR REGULATOR (V

CLK

OUT4

)

Regulation - - 2.0 %
VCLK Nominal Voltage Level V

VCLK

- 2.5 - V
VCLK Undervoltage Rising Threshold - 2.075 - V
VCLK Undervoltage Hysteresis -75- mV
VCLK Output Current (Note 2) I

5V

SWITCH CONTROLLER (V

DUAL

OUT5

)

VCLK

V

= 3.3V 500 800 - mA

3V3

5VDL Undervoltage Rising Threshold - 4.150 - V
5VDL Undervoltage Hysteresis - 150 - mV
5VDLSB Output Drive Current I

5VDLSB

5VDLSB = 4V, 5VSB = 5V -20 - -40 mA

5VDLSB Pull-Up Impedance to 5VSB - 350 - Ω

TIMING INTERVALS

Active State Assessment Past Input UV

20 25 30 ms

Thresholds (Note 3)
Active-to-Sleep Control Input Delay - 200 - µs

CONTROL I/O (S3, S5, EN5VDL, MSEL, FAULT)

High Level Input Threshold - - 2.2 V
Low Level Input Threshold 0.8 - - V
S3, S5 Internal Pull-up Impedance to 5VSB - 50 - kΩ
FAULT Output Impedance FAULT = high - 100 - Ω

TEMPERATURE MONITOR

Fault-Level Threshold (Note 4) 125 - ­Shutdown-Level Threshold (Note 4) - 155 -

NOTES:

2. At Ambient Temperatures Less Than 50oC.

3. Guaranteed by Correlation.

4. Guaranteed by Design.

o

C

o

C

5