Intersil Corporation HIP6500 Datasheet

HIP6500

Data Sheet December 1999 File Number 4774.1

Multiple Linear Power Controller with
ACPI Control Interface

The HIP6500 complements either an HIP6020 or an HIP6021
in ACPI-compliant designs for microprocessor and computer
applications. The IC integrates two linear controllers and two
regulators, switching, monitoring and control functions into a
20-pin SOIC package. One linear controller generates the

3.3V
powering the PCI slots through an external pass transistor
during sleep states (S3, S4/S5). A second transistor is used to
switch in the ATX 3.3V output f or operation during S0 and
S1/S2 (active) operating states. The second linear controller
supplies the computer system’s 2.5V/3.3V memory power
through an external pass transistor in active states. During S3
state, an integrated pass transistor supplies the 2.5V/3.3V
sleep power . A third controller pow ers up the 5V
switching in the ATX 5V output in activ e states, and the ATX
5VSB in sleep states. The two internal regulators consist of a
low current 3.3V sleep output and a dedicated, noise-free 2.5V
clock chip supply. The HIP6500’s operating mode (active
outputs or sleep outputs) is selectable through two digital
control pins,
activation of different pow er states is off ered through tw o
configuration pins,

3.3V
MOSFET to connect the output directly to the 3.3V input
supplied by an ATX (or equivalent) power supply, for minimal
losses.Insleepstate,power delivery on the 3.3V
transferred to an NPN transistor, also external to the controller.
Active state power deliv ery for the 2.5/3.3V
performed through an external NPN transistor, or an NMOS
switch for the 3.3V setting. In sleep state, conduction on this
output is transferred to an internalpass transistor.The 5V
output is powered through two external MOS transistors. In
sleep states, a PMOS (or PNP) transistor conducts the current
from the ATX 5VSB output; while in active state, current flow is
transferred to an NMOS transistor connected to the ATX 5V
output. Similar to the 3.3V
5V
S5 pins, but that of the EN5VDL pin as well. The 3.3V
internal regulator is active for as long as the ATX 5VSB voltage
is applied to the chip, and derives its output current from the
5VSB pin. The 2.5V
S1/S2, and uses the 3V3 pin as input source for its internal
pass element.

voltage plane from the ATX supply’ s 5VSB output,

DUAL

DUAL

S3 and S5. Further control of the logic governing

EN3VDL and EN5VDL. In active state, the

linear regulator uses an external N-Channel pass

DUAL

DUAL

output is

MEM

output, the operation of the

output is dictated not only by the status of the S3 and

DUAL

DUAL

output is only active during S0 and

CLK

plane by

output is

DUAL

SB

Features

• Provides 5 ACPI-Controlled Voltages

- 5V Active/Sleep (5V

- 3.3V Active/Sleep (3.3V

- 2.5V/3.3V Active/Sleep (2.5V

- 3.3V Always Present (3.3V

- 2.5V Clock (Active Only) (2.5V

DUAL

)

DUAL

SB

)

MEM

)

CLK

)

)

• Excellent Output Voltage Regulation

- 3.3V

Output: ±2.0% Over Temperature; Sleep

DUAL

State Only

- 2.5V/3.3V

Output: ±2.0% Over Temperature; Both

MEM

Operational States (3.3V setting in sleep only)

- 2.5V

and 3.3VSBOutput: ±2.0% Over Temperature

CLK

• Small Size

- Very Low External Component Count

• Selectable Memory Output Voltage Via FAULT/MSEL Pin

- 2.5V for RDRAM Memory

- 3.3V for SDRAM Memory

• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting and Temperature Shutdown

Applications

•

Motherboard Power Regulation for ACPI-Compliant
Computers

Pinout

HIP6500

(SOIC)

TOP VIEW

VSEN2

5VSB

3V3SB

3V3DLSB

3V3DL

VCLK

3V3

EN5VDL

S3
S5

1
2
3
4
5
6
7
8
9

10

20

EN3VDL

19

DRV2

18

5V

17

12V

16

SS
5VDL

15

5VDLSB

14

13

DLA

12

FAULT/MSEL

11

GND

Ordering Information

TEMP.

PART NUMBER

HIP6500CB 0 to 70 20 Ld SOIC M20.3
HIP6500EVAL1 Evaluation Board

RANGE (oC) PACKAGE

1

PKG.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

NO.

1-888-INTERSIL or 321-724-7143

| Copyright © Intersil Corporation 1999

Block Diagram

12V

2

TO 5VSB

12V MONITOR

EA3

10.2V/9.2V

+

3V3DLSB

EA4

-

+

3V3DL

5V

3V3

5VSB

5VSB POR

4.5V/4.0V

5VDLSB

DLA

TEMPERATURE

MONITOR

(TMON)

-

TO

3V3SB

FAULT/MSEL

UV DETECTOR

UV

DETECTOR

MONITOR AND CONTROL

TO

UV DETECTOR

+

1.265V

TO 3V3

EA3

+

HIP6500

-

VCLK

TO 5V

-

5VDL

40µA

3.75V

TO 5VSB

-

+

UV COMPARATOR

+

-

GND

SS

10µA

S3

S5

EN3VDL

FIGURE 1.

EN5VDL

TO

UV DETECTOR

DRV2

EA2

-

+

VSEN2

Simplified Power System Diagram

+5V

IN

+12V

IN

+5V

SB

+3.3V

IN

HIP6500

Q2

3.3V

DUAL

3.3V

FAULT/MSEL

SHUTDOWN

SX

ENXVDL

2

2

Typical Application

+5V

IN

+12V

IN

+5V

SB

+3.3V

IN

Q3

3.3V

3.3V

SB

LINEAR

REGULATOR

LINEAR

CONTROLLER

HIP6500

FIGURE 2.

LINEAR

CONTROLLER

LINEAR

REGULATOR

CONTROL

LOGIC

Q1

V

MEM

2.5V/3.3V
V

CLK

2.5V

Q5

Q4

5V

DUAL

5V

FAULT

SLP_S3
SLP_S5

EN5VDL

EN3VDL

SHUTDOWN

V

OUT1

3.3V

V

3.3V

SB

OUT3

DUAL

Q2

C

OUT1

C

Q3

OUT3

3V3SB

5V

3V3DLSB

3V3DL

FAULT/MSEL

R

SEL

S3
S5

EN5VDL
EN3VDL

SS

C

SS

12V

3V3

HIP6500

GND

5VSB

DRV2

VSEN2

C

OUT2

VCLK

5VDLSB
DLA

5VDL

C

OUT4

Q1

C

OUT5

Q5

2.5/3.3V

2.5V

Q4

V

V

5V

OUT2

V

OUT4

OUT5

DUAL

MEM

CLK

FIGURE 3.

3

HIP6500

Absolute Maximum Ratings Thermal Information

Supply Voltage, V

12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V

DLA, DRV2. . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V

All Other Pins. . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 5VSB + 0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 3

Recommended Operating Conditions

Supply Voltage, V
Digital Inputs, VSX,V

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . .0oC to 70oC

Junction Temperature Range. . . . . . . . . . . . . . . . . . . .0oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3

VCC SUPPLY CURRENT

Nominal Supply Current I
Shutdown Supply Current I

POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS

Rising 5VSB POR Threshold - - 4.5 V
5VSB POR Hysteresis - 0.2 - V
Rising 12V Threshold - - 10.2 V
12V Hysteresis - 1.0 - V
Rising 3V3 and 5V Thresholds -90- %
3V3 and 5V Hysteresis -5- %
Soft-Start Current I
Shutdown Voltage Threshold V

3.3VSB LINEAR REGULATOR (V

Regulation - - 2.0 %
3V3SB Nominal Voltage Level V
3V3SB Undervoltage Rising Threshold - 2.77 - V
3V3SB Undervoltage Hysteresis - 110 - mV
3V3SB Output Current I

2.5/3.3V

Regulation - - 2.0 %
VSEN2 Nominal Voltage Level V
VSEN2 Nominal Voltage Level V
VSEN2 Undervoltage Rising Threshold -83- %
VSEN2 Undervoltage Hysteresis (Note 2) - 3 - %
VSEN2 Output Current I
DRV2 Output Drive Current I
DRV2 Output Impedance R

LINEAR REGULATOR (V

MEM

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V

5VSB

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

+0.3V

12V

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

. . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ± 5%

5VSB

EN5VDL

, V

EN3VDL

. . . . . . . . . . . . 0 to +5.25V

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

-30- mA

-10- µA

- - 0.8 V

- 3.3 - V

OUT1

)

OUT2

)

5VSB

5VSB(OFF)VSS

SS

SD

3V3SB

3V3SB

VSEN2
VSEN2

VSEN2

DRV2

5VSB = 5V 250 300 - mA

R

SEL

R

SEL

5VSB = 5V 250 300 - mA
5VSB = 5V, R

SEL

= 0.8V - 14 - mA

= 1kΩ - 2.5 - V
= 10kΩ - 3.3 - V

= 1kΩ 220 - - mA

SEL

= 10kΩ - 200 - Ω

4

HIP6500

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

3.3V

Sleep State Regulation - - 2.0 %
3V3DL Nominal Voltage Level V
3V3DL Undervoltage Rising Threshold - 2.77 - V
3V3DL Undervoltage Hysteresis - 110 - mV
3V3DLSB Output Drive Current I
DLA Output Impedance -90- Ω

2.5V

Regulation - - 2.0 %
VCLK Nominal Voltage Level V
VCLK Undervoltage Rising Threshold - 2.10 - V
VCLK Undervoltage Hysteresis -80- mV
VCLK Output Current (Note 3) I

5V

5VDL Undervoltage Rising Threshold - 4.22 - V
5VDL Undervoltage Hysteresis - 170 - mV
5VDLSB Output Drive Current I
5VDLSB Pull-up Impedance to 5VSB - 350 - Ω

TIMING INTERVALS

Active State Assessment Past Input UV
Thresholds (Note 4)

Active-to-Sleep Control Input Delay - 200 - µs

CONTROL I/O (S3, S5, EN3VDL, EN5VDL, FAULT/MSEL)

High Level Input Threshold - - 2.2 V
Low Level Input Threshold 0.8 - - V
S3, S5 Internal Pull-Up Impedance to 5VSB - 70 - kΩ
FAULT Output Impedance FAULT = high - 100 - Ω

TEMPERATURE MONITOR

Fault-Level Threshold (Note 5) 140 - ­Shutdown-Level Threshold (Note 5) - 155 -

NOTES:

2. Valid for 3.3V setting only.

3. At ambient temperatures less than 50oC.

4. Guaranteed by correlation.

5. Guaranteed by design.

LINEAR REGULATOR (V

DUAL

LINEAR REGULATOR (V

CLK

SWITCH CONTROLLER (V

DUAL

OUT3

OUT4

OUT5

)

3V3DL

3V3DLSB

5VSB = 5V 5 8.5 - mA

- 3.3 - V

)

VCLK

VCLK

V

= 3.3V 500 800 - mA

3V3

- 2.5 - V

)

5VDLSB

5VDLSB = 4V, 5VSB = 5V -20 - -40 mA

20 25 30 ms

o

C

o

C

5