Intersil Corporation HIP6019 Datasheet

HIP6019

Data Sheet April 1998 File Number

Advanced Dual PWM and Dual Linear
Power Control

The HIP6019 provides the powercontrolandprotectionforfour
output voltages in high-performance microprocessor and
computer applications. The IC integrates two PWM controllers,
a linear regulator and a linear controller as well as the
monitoring and protection functions into a single 28 lead SOIC
package. One PWM controller regulates the microprocessor
core voltage with a synchronous-rectified buck converter,while
thesecondPWMcontrollersupplies the computer’s3.3V power
with a standard buck conv erter. The linear controller regulates
power for the GTL bus and the linear regulator pro vides po wer
for the clock driver circuits.

The HIP6019 includes an Intel-compatible, TTL 5-input digital­to-analog converter (DAC) that adjusts the core PWM output
voltage from 2.1V

1.8V

to 2.05VDC in 0.05V steps. The precision reference

DC

to 3.5VDC in 0.1V increments and from

DC

and voltage-mode control provide ±1% static regulation. The
second PWM controller is user-adjustable for output le v els
between 3.0V and 3.5V with ±2% accuracy. The adjustable
linear regulator uses an internal pass device to provide 2.5V
±2.5%. The adjustable linear controller drives an external N­Channel MOSFET to provide 1.5V ±2.5%.

The HIP6019 monitors all the output voltages. A single P o wer
Good signal is issued when the core is within ±10% of the DAC
setting and the other levels are abov e their under- voltage
levels. Additional b uilt-in o v er-v oltage protection for the core
output uses the lower MOSFET to prev ent output v oltages
above 115% of the D A C setting. The PWM controller’s over­current functions monitor the output current by sensing the
voltage drop across the upper MOSFET’s r

DS(ON)

, eliminating

the need for a current sensing resistor .

Pinout

HIP6019 (SOIC)

TOP VIEW

28
27
26
25
24
23
22
21
20
19
18
17
16
15

V

CC

UGATE1
PHASE1
LGATE1
PGND
OCSET1
VSEN1
FB1
COMP1
FB3
GATE3
GND
VOUT4
VSEN2

UGATE2
PHASE2

VID4
VID3
VID2
VID1
VID0

PGOOD

OCSET2

FB2

COMP2

SS

FAULT/RT

FB4

1
2
3
4
5
6
7
8

9
10
11
12
13
14

4490.2

Features

• Provides 4 Regulated Voltages

- Microprocessor Core, I/O, Clock Chip and GTL Bus

• Drives N-Channel MOSFETs

• Operates from +5V and +12V Inputs

• Simple Single-Loop Control Designs

- Voltage-Mode PWM Control

• Fast Transient Response

- High-Bandwidth Error Amplifiers

- Full 0% to 100% Duty Ratios

• Excellent Output Voltage Regulation

- Core PWM Output: ±1% Over Temperature

- I/O PWM Output: ±2% Over Temperature

- Other Outputs: ±2.5% Over Temperature

• TTL-Compatible 5-Bit Digital-to-Analog Core Output
Voltage Selection

- Wide Range . . . . . . . . . . . . . . . . . . . 1.8V

DC

to 3.5V

- 0.1V Steps . . . . . . . . . . . . . . . . . . . . 2.1VDC to 3.5V

- 0.05V Steps . . . . . . . . . . . . . . . . . . 1.8VDC to 2.05V

• Power-Good Output Voltage Monitor

• Microprocessor Core Voltage Protection Against Shorted
MOSFET

• Over-Voltage and Over-Current Fault Monitors

- Does Not Require Extra Current Sensing Element,

Uses MOSFET’s r

DS(ON)

• Small Converter Size

- Constant Frequency Operation

- 200kHz Free-Running Oscillator; Programmable from

50kHz to 1MHz

Applications

•

Full Motherboard Power Regulation for Computers

• Low-Voltage Distributed Power Supplies

Ordering Information

PART NUMBER TEMP. (oC) PACKAGE PKG. NO.

HIP6019CB 0 to 70 28 Ld SOIC M28.3
HIP6019EVAL1 Evaluation Board

DC
DC
DC

2-252

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

Block Diagram

HIP6019

VCC

OCSET1

VSEN1

OCSET2

POWER-ON

RESET (POR)

200µA

+

110%

LUV

-

PGOOD

+

90%

DRIVE

LOWER

PGND

TTL D/A

VCC

GND

CONVERTER

DACOUT

VID4

VID3

4V

VID2

VID1

VID0

FB1 COMP1

SS

FIGURE 1.

(DAC)

11µA

UGATE1

PHASE1

VCC

DRIVE1

GATE

INHIBIT

-

+

OC1

-

-

+

115%

OV

SOFT-

LOGIC

START

OC

200µA

AND FAULT

+

FAULT

CONTROL

+

-

VCC

PWM1

PWM

-

COMP1

AMP1

ERROR

LGATE1

LINEAR

FB3

UNDER-

VOLTAGE

+

-

0.3V

+

-

+

VSEN2

GATE3

2-253

FAULT / RT

VCC

DRIVE2

GATE2

OC2

-

+

PHASE2

-

INHIBIT

GATE

+

PWM2

CONTROL

PWM

COMP2

-

FB2

COMP2

+

AMP2

ERROR

+

1.26V

-

+

VSEN2

+

2.5V

-

+

-

-

+

0.25A

VOUT4

OC4

FB4

-

-

+

1.26V

+

-

+

OSCILLATOR

4.3V

-

+

Simplified Power System Diagram

+5V

IN

V

OUT2

HIP6019

PWM2

CONTROLLER

HIP6019

PWM1

CONTROLLER

V

OUT1

V

OUT3

V

OUT4

Typical Application

+12V

IN

+5V

IN

V

OUT2

3.0V TO 3.5V

C

L

OUT2

OUT2

C

CR2

LINEAR LINEAR

CONTROLLER REGULATOR

FIGURE 2.

IN

OCSET2

Q3

UGATE2
PHASE2

VCC

OCSET1

PGOOD

UGATE1
PHASE1

LGATE1
PGND

Q1

Q2

CR1

L

OUT1

C

OUT1

POWERGOOD

V

OUT1

1.8V TO 3.5V

V

1.5V

V

OUT4

2.5V

OUT3

C

Q4

OUT3

C

OUT4

2-254

VSEN2

FB2

COMP2

GATE3

FB3

VOUT4

FB4

HIP6019

GND

FIGURE 3.

VSEN1

FB1

COMP1

FAULT / RT

VID0
VID1
VID2
VID3
VID4

SS

C

SS

HIP6019

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V

PGOOD, R T/FA ULT, and GATE Voltage. . . . GND - 0.3V to VCC + 0.3V

Input, Output or I/O Voltage. . . . . . . . . . . . . . . . . . GND -0.3V to 7V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 2

Operating Conditions

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . .0oC to 70oC

Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.

Refer to Figures 1, 2 and 3

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Nominal Supply I

POWER-ON RESET

Rising VCC Threshold V
Falling VCC Threshold V
Rising V

OSCILLATOR

Free Running Frequency RT = OPEN 185 200 215 kHz
Total Variation 6kΩ < RT to GND < 200kΩ -15 - +15 %
Ramp Amplitude ∆V

REFERENCE AND DAC

DAC(VID0-VID4) Input Low Voltage - - 0.8 V
DAC(VID0-VID4) Input High Voltage 2.0 - - V
DACOUT Voltage Accuracy -1.0 - +1.0 %
Reference Voltage

(Pin FB2, FB3, and FB4)

LINEAR REGULATOR

Regulation 10mA < I
Under-Voltage Level FB4
Under-Voltage Hysteresis -6- %
Over-Current Protection 180 230 - mA
Over-Current Protection During Start-Up CSS Voltage < 4V 560 700 - mA

LINEAR CONTROLLER

Regulation VSEN3 = GATE3 -2.5 - 2.5 %
Under-Voltage Level FB3
Under-Voltage Hysteresis -6- %

Threshold - 1.25 - V

OCSET1

CC

OSC

UGATE1, GATE2, GATE3, LGATE1, and
VOUT4 Open

OCSET
OCSET

RT = Open - 1.9 - V

FB4 Rising - 75 87 %

UV

FB3 Rising - 75 87 %

UV

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

SOIC Package (with 3 in2 of copper) . . . . . . . . . . . 50

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

-10- mA

= 4.5V 8.6 - 10.4 V
= 4.5V 8.2 - 10.2 V

1.240 1.265 1.290 V

< 150mA -2.5 - 2.5 %

VOUT4

P-P

2-255

HIP6019

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted.

Refer to Figures 1, 2 and 3 (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

PWM CONTROLLER ERROR AMPLIFIERS

DC Gain -88- dB
Gain-Bandwidth Product GBWP - 15 - MHz
Slew Rate SR COMP = 10pF - 6 - V/µs

PWM CONTROLLER GATE DRIVERS

Drive1 (and 2) Source I
Drive1 (and 2) Sink R
Lower Gate Source I
Lower Gate Sink R

UGATE

UGATEVGATE-PHASE

LGATE

LGATEVGATE

PROTECTION

V

Over-Voltage Trip VSEN1 Rising 112 115 118 %

OUT1

V

Over-Voltage Trip VSEN2 Rising 4.1 4.3 4.5 V

OUT2

VSEN2 Input Resistance -70- kΩ
FAULT Sourcing Current I
OCSET1(and 2) Current Source I
Soft-Start Current I

OVP

OCSETVOCSET

SS

Chip Shutdown Soft-Start Threshold - - 1.0 V

POWER GOOD

V

Upper Threshold VSEN1 Rising 108 - 110 %

OUT1

V

Under-Voltage VSEN1 Rising 92 - 94 %

OUT1

V

Hysteresis Upper/Lower Threshold - 2 - %

OUT1

V

Under-Voltage VSEN2 Rising 2.45 2.55 2.65 V

OUT2

V

Under-Voltage Hysteresis - 100 - mV

OUT2

PGOOD Voltage Low V

PGOODIPGOOD

VCC = 12V, V

UGATE1

(or V

) = 6V - 1 - A

GATE2

= 1V - 1.7 3.5 Ω

VCC = 12V, V

= 1V - 1 - A

LGATE

= 1V - 1.4 3.0 Ω

V

FAULT/RT

= 10.0V 10 14 - mA

= 4.5V

DC

170 200 230 µA

-11- µA

= -4mA - - 0.5 V

Typical Performance Curves

1000

100

RESISTANCE (kΩ)

10

RT PULLUP
TO +12V

RT PULLDOWN TO V

10 100 1000

SWITCHING FREQUENCY (kHz)

FIGURE 4. RT RESISTANCE vs FREQUENCY FIGURE 5. BIAS SUPPLY CURRENT vs FREQUENCY

2-256

SS

140

C

= C

UGATE1

V

= 12V,VIN = 5V

VCC

120

100

80

(mA)

60

CC

I

40

20

100 200 300 400 500 600 700 800 900 1000

= C

UGATE2

SWITCHING FREQUENCY (kHz)

LGATE1

= C

GATE

C

C

C

C

GATE

GATE

GATE

GATE

= 4800pF

= 3600pF

= 1500pF

= 660pF