intersil HIP6004B DATA SHEET

®

HIP6004B

Data Sheet October 2003 FN4567.3

Buck and Synchronous-Rectifier (PWM)
Controller and Output Voltage Monitor

The HIP6004B provides complete control and protection for
a DC-DC converter optimized for high-performance
microprocessor applications. It is designed to drive two
N-Channel MOSFETs in a synchronous-rectified buck
topology. The HIP6004B integrates all of the control, output
adjustment, monitoring and protection functions into a single
package.

The output voltage of the converter is easily adjusted and
precisely regulated. The HIP6004B includes a fully
TTL-compatible 5-input digital-to-analog converter (DAC)
that adjusts the output voltage from 1.3V

0.05V and from 2.1V

to 3.5VDC in 0.1V increments steps.

DC

to 2.05VDC in

DC

The precision reference and voltage-mode regulator hold the
selected output voltage to within ±1% over temperature and
line voltage variations.

The HIP6004B provides simple, single feedback loop,
voltage-mode control with fast transient response. It includes
a 200kHz free-running triangle-wave oscillator that is
adjustable from below 50kHz to over 1MHz. The error
amplifier features a 15MHz gain-bandwidth product and
6V/µs slew rate which enables high converter bandwidth for
fast transient performance. The resulting PWM duty ratio
ranges from 0% to 100%.

The HIP6004B monitors the output voltage with a window
comparator that tracks the DAC output and issues a Power
Good signal when the output is within ±10%. The HIP6004B
protects against over-current and overvoltage conditions by
inhibiting PWM operation. Addi t io n al bu i lt - i n overvoltage
protection triggers an external SCR to crowbar the input
supply. The HIP6004B monitors the current by using the
r

of the upper MOSFET which eliminates the need for

DS(ON)

a current sensing resistor.

Ordering Information

PART NUMBER

HIP6004BCB 0 to 70 20 Ld SOIC M20.3
HIP6004BCV 0 to 70 20 Ld TSSOP M20.173
HIP6004BCR 0 to 70 20 Ld 5x5 QFN L20.5x5

TEMP.

RANGE (oC) PACKAGE

PKG.

DWG. #

Features

• Drives Two N-Channel MOSFETs

• Operates from +5V or +12V Input

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

• Fast Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Ratio

• Excellent Output Voltage Regulation

- ±1% Over Line Voltage and Temperature

• TTL-Compatible 5-Bit Digital-to-Analog Output
Voltage Selection

- Wide Range . . . . . . . . . . . . . . . . . . . 1.3V

DC

to 3.5V

- 0.1V Binary Steps . . . . . . . . . . . . . . 2.1VDC to 3.5V

- 0.05V Binary Steps . . . . . . . . . . . . 1.3VDC to 2.05V

• Power-Good Output Voltage Monitor

• Over-Voltage and Over-Current Fault Monitors

- Does Not Require Extra Current Sensing Element,

Uses MOSFET’s r

DS(ON)

• Small Converter Size

- Constant Frequency Operation

- 200kHz Free-Running Oscillator Programmable from

50kHz to over 1MHz

• QFN Package:

- Compliant to JEDEC PUB95 MO-220

QFN - Quad Flat No Leads - Package Outline

- Near Chip Scale Package footprint, which improves

PCB efficiency and has a thinner profile

Applications

• Power Supply for Pentium®, Pentium Pro, Pentium II,
PowerPC™, K6™, 6X86™ and Alpha™ Microprocessors

•

High-Power 5V to 3.xV DC-DC Regulators

•

Low-Voltage Distributed Power Supplies

DC
DC
DC

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2003. All Rights Reserved.

Pinouts

HIP6004B (SOIC, TSSOP)

TOP VIEW

HIP6004B

HIP6004B (QFN)

TOP VIEW

1

V

SEN

OCSET

SS
VID0
VID1
VID2
VID3
VID4

COMP

FB

2
3
4
5
6
7
8
9

10

Typical Application

PGOOD

SS

OVP

RT

20

OVP

19

V

18

CC

LGATE

17

PGND

16

BOOT

15

UGATE

14

PHASE

13
12

PGOOD
GND

11

+12V

MONITOR AND

PROTECTION

VCC

OCSET
EN
BOOT

SS

20 19 18 17 16

VID0

1

VID1

2

VID2

3

VID3

4

VID4

5

678910

COMP

VIN = +5V OR +12V

OCSET

FB

GND

21

VSEN

GND

RT

PGOOD

OVP

VCC

15

LGATE

14

PGND

13

BOOT

12

UGATE

11

PHASE

VID0
VID1
VID2
VID3
VID4

RT

FB

D/A

OSC

+

-

COMP

HIP6004B

+

-

VSEN

GND

UGATE
PHASE

LGATE
PGND

+V

OUT

2

Block Diagram

V

SEN

OCSET

VID0
VID1
VID2
VID3
VID4

FB

COMP

RT

REFERENCE

TTL D/A

CONVERTER

(DAC)

200µA

DACOUT

110%

90%

115%

HIP6004B

+

-

+

­OVER-

VOLTAGE

+

-

+

-

OVER-

CURRENT

+

-

ERROR

AMP

OSCILLATOR

RESET (POR)

4V

PWM

COMPARATOR

+

-

V

CC

POWER-ON

SOFT-

START

INHIBIT

PWM

PGOOD

10µA

OVP

SS

BOOT
UGATE

PHASE

GATE

CONTROL

LOGIC

LGATE
PGND
GND

3

4

HIP6004B

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

POWER GOOD

Upper Threshold (V
Lower Threshold (V
Hysteresis (V

SEN

/DACOUT) V

SEN

/DACOUT) V

SEN

/DACOUT) Upper and Lower Threshold - 2 - %

PGOOD Voltage Low V

PGOODIPGOOD

Rising 106 - 111 %

SEN

Falling 89 - 94 %

SEN

= -5mA - 0.5 - V

Typical Performance Curves

80

70

1000

RT PULLUP

TO +12V

60

C

= C

UPPER

50

LOWER

= C

GATE

C

GATE

= 3300pF

100

RESISTANCE (kΩ)

10

10 100 1000

SWITCHING FREQUENCY (kHz)

RT PULLDOWN TO V

SS

FIGURE 1. RT RESISTANCE vs FREQUENCY FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY

Functional Pin Descriptions

1

V

SEN

V

SEN

OCSET

(Pin 1)

SS
VID0
VID1
VID2
VID3
VID4

COMP

FB

2
3
4
5
6
7
8
9

10

This pin is connected to the converters output voltage. The
PGOOD and OVP comparator circuits use this signal to
report output voltage status and for overvoltage protection.

OCSET (Pin 2)

Connect a resistor (R
upper MOSFET. R
(I

), and the upper MOSFET on-resistance (r

OCS

OCSET

) from this pin to the drain of the

OCSET

, an internal 200µA current source

20
19
18
17
16
15
14
13
12
11

RT
OVP
VCC
LGATE
PGND
BOOT
UGATE
PHASE
PGOOD
GND

DS(ON)

) set

40

(mA)

CC

I

30

20

10

0

100 200 300 400 500 600 700 800 900 1000

SWITCHING FREQUENCY (kHz)

C

C

GATE

GATE

= 1000pF

= 10pF

the converter over-current (OC) trip point according to the
following equation:

I

PEAK

OCSET

-----------------------------------------------------

=

OCSET

r

DS ON()

I

x R

An over-current trip cycles the soft-start function.

SS (Pin 3)

Connect a capacitor from this pin to ground. This capacitor,
along with an internal 10µA current source, sets the soft­start interval of the converter.

VID0-4 (Pins 4-8)

VID0-4 are the input pins to the 5-bit DAC. The states of
these five pins program the internal voltage reference
(DACOUT). The level of DACOUT sets the converter output
voltage. It also sets the PGOOD and OVP thresholds. Table
1 specifies DACOUT for the all combinations of DAC inputs.

COMP (Pin 9) and FB (Pin 10)

COMP and FB are the available external pins of the error
amplifier. The FB pin is the inverting input of the error
amplifier and the COMP pin is the error amplifier output.
These pins are used to compensate the voltage-control
feedback loop of the converter.

5

GND (Pin 11)

Signal ground for the IC. All voltage levels are measured
with respect to this pin.

PGOOD (Pin 12)

PGOOD is an open collector output used to indicate the
status of the converter output voltage. This pin is pulled low
when the converter output is not within

±10% of the

DACOUT reference voltage. Exception to this behavior is the
‘11111’ VID pin combination which disables the converter; in
this case PGOOD asserts a high level.

PHASE (Pin 13)

Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET
for over-current protection. This pin also provides the return
path for the upper gate drive.

UGATE (Pin 14)

Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET.

BOOT (Pin 15)

This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.

PGND (Pin 16)

This is the power ground connection. Tie the lower MOSFET
source to this pin.

LGATE (Pin 17)

Connect LGATE to the lower MOSFET gate. This pin
provides the gate drive for the lower MOSFET.

VCC (Pin 18)

Provide a 12V bias supply for the chip to this pin.

OVP (Pin 19)

The OVP pin can be used to drive an external SCR in the
event of an overvoltage condition. Output rising 15% more
than the DAC-set voltage triggers a high output on this pin
and disables PWM gate drive circuitry.

Functional Description

Initialization

The HIP6004B automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary. The
Power-On Reset (POR) function continually monitors the input
supply voltages. The POR monitors the bias voltage at the V
pin and the input voltage (V
OCSET is equal to V

IN

) on the OCSET pin. The level on

IN

less a fixed voltage drop (see over­current protection). The POR function initiates soft start
operation after both input supply voltages exceed their POR
thresholds. For operation with a single +12V power source, V
and V
exceed the rising V

are equivalent and the +12V power source must

CC

threshold before POR initiates operation.

CC

Soft Start

The POR function initiates the soft start sequence. An internal
10µA current source charges an external capacitor (C
the SS pin to 4V. Soft start clamps the error amplifier output
(COMP pin) and reference input (+ terminal of error amp) to the
SS pin voltage. Figure 3 shows the soft start interval with
C

= 0.1µF . Initially the clam p on the error a mplifier (CO MP

SS

pin) controls the converter’s output voltage. At t
the SS voltage reaches the valley of the oscillator’s triangle
wave. The oscillator’s triangular waveform is compared to the
ramping error amplifier voltage. This generates PHASE pulses
of increasing width that charge the output capacitor(s). This
interval of increasing pulse width continues to t
output voltage, the clamp on the ref erence input control s the
output voltage. This is the interval between t
At t

the SS voltage exceeds the DACOUT voltage and the

3

output voltage is in regulation. This method provides a rapid
and controlled output voltage rise. The PGOOD signal toggles
‘high’ when the output voltage (V

pin) is within ±5% of

SEN

DACOUT. The 2% hysteresis built into the power good
comparators prevents PGOOD oscillation due to nominal
output voltage ripple.

in Figure 3,

1

. With sufficient

2

and t3 in Figure 3.

2

SS

CC

IN

) on

RT (Pin 20)

This pin provides oscillator switching frequency adjustment.
By placing a resistor (R
200kHz switching frequency is increased according to the
following equation:

5 x 10

Fs 200kHz

≈

---------------------

+

RTkΩ()

Conversely, connecting a pull-up resistor (R
to V

reduces the switching frequency according to the

CC

following equation:

4 x 10

≈

Fs 200kHz

---------------------

–

RTkΩ()

) from this pin to GND, the nominal

T

6

(RT to GND)

) from this pin

T

7

(RT to 12V)

6

HIP6004B

Over-Current Protection

The over-current function protects the converter from a
shorted output by using the upper MOSFET’s on-resistance,
r
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.

The over-current function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R
programs the over-current trip level. An internal 200µA current
sink develops a voltage across R
V
referenced to V
over-current function initiates a soft-start sequence. The soft­start function discharges C
inhibits PWM operation. The soft-start function recharges
C
clamped to the SS voltage. Should an overload occur while
recharging C
while fully charging C
shows this operation with an overload condition. Note that the
inductor current increases to over 15A during the C
charging interval and causes an over-current trip. The
converter dissipates very little power with this method. The
measured input power for the conditions of Figure 4 is 2.5W.

The over-current function will trip at a peak inductor current
(I

I

to monitor the current. This method enhances the

DS(ON)

4V

2V

0V

15A

10A

5A

OUTPUT INDUCTOR SOFT-START

0A

TIME (20ms/DIV)

FIGURE 4. OVER-CURRENT OPERATION

that is referenced to

. When the voltage across the upper MOSFET (also

IN

, and PWM operation resumes with the error amplifier

SS

determined by:

PEAK)

I

-----------------------------------------------------

=

PEAK

) exceeds the voltage across R

IN

, the soft start function inhibits PWM operation

SS

OCSET

r

DS ON()

to 4V to complete its cycle. Figure 4

SS

x R

OCSET

OCSET

OCSET

with a 10µA current sink and

SS

OCSET

SS

)

, the

where I

is the internal OCSET current source (200µA

OCSET

typical). The OC trip point varies mainly due to the
MOSFET’s r
tripping in the normal operating load range, find the R

variations. To avoid over-current

DS(ON)

OCSET

resistor from the equation above with:

1. The maximum r

at the highest junction

DS(ON)

temperature.

2. The minimum I

3. Determine I

PEAK

where ∆I is the output inductor ripple current.

from the specification table.

OCSET

for

I

PEAKIOUT MAX()

,

∆I()2⁄+>

For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.

A small ceramic capacitor should be placed in parallel with
R

to smooth the voltage across R

OCSET

OCSET

in the

presence of switching noise on the input voltage.

Output Voltage Program

The output voltage of a HIP6004B converter is programmed
to discrete levels between 1.8V

and 3.5VDC. The voltage

DC

identification (VID) pins program an internal voltage reference
(DACOUT) with a TTL-compatible 5-bit digital-to-analog
converter (DAC). The level of DACOUT also sets the PGOOD
and OVP thresholds. Table 1 specifies the DACOUT voltage
for the 32 different combinations of connections on the VID
pins. The output voltage should not be adjusted while the
converter is delivering power. Remove input power before
changing the output voltage. Adjusting the output voltage
during operation could toggle the PGOOD signal and exercise
the overvoltage protection.

‘11111’ VID pin combination resulting in a 0V output setting
activates the Power-On Reset function and disables the gate
drives circuitry. For this specific VID combination, though,
PGOOD asserts a high level. This unusual behavior has been
implemented in order to allow for operation in dual­microprocessor systems where AND-ing of the PGOOD signals
from two individual power converters is implemented.

Application Guidelines

Layout Considerations

As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.

7

HIP6004B

TABLE 1. OUTPUT VOLTAGE PROGRAM

PIN NAME

NOMINAL OUTPUT

VOLTAGE DACOUT

01111 1.30 11111 0
01110 1.35 11110 2.1
01101 1.40 11101 2.2
01100 1.45 11100 2.3
01011 1.50 11011 2.4
01010 1.55 11010 2.5
01001 1.60 11001 2.6
01000 1.65 11000 2.7
00111 1.70 10111 2.8
00110 1.75 10110 2.9
00101 1.80 10101 3.0
00100 1.85 10100 3.1
00011 1.90 10011 3.2
00010 1.95 10010 3.3
00001 2.00 10001 3.4
00000 2.05 10000 3.5

NOTE: 0 = connected to GND or V

, 1 = connected to VDD through pull-up resistors.

SS

PIN NAME

NOMINAL OUTPUT

VOLTAGE DACOUTVID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0

V

IN

HIP6004B

UGATE
PHASE

LGATE

PGND

Q

1

Q

2

RETURN

L

O

V

OUT

C

IN

C

D

2

O

LOAD

FIGURE 5. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

Figure 5 shows the critical power components of the converter.
To minimize the voltage overshoot the interconnecting wires
indicated by heavy lines should be part of ground or power
plane in a printed circuit board. The components shown in
Figure 5 should be located as close together as possible.
Please note that the capacitors C

and CO each represent

IN

numerous physical capacitors. Locate the HIP6004B within 3
inches of the MOSFETs, Q

and Q2. The circuit traces for the

1

MOSFETs’ gate and source connections from the HIP6004B
must be sized to handle up to 1A peak current.

Figure 6 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage

current paths on the SS PIN and locate the capacitor, C

SS

close to the SS pin because the internal current source is
only 10µA. Provide local V
GND pins. Locate the capacitor, C

decoupling between VCC and

CC

BOOT

as close as

practical to the BOOT and PHASE pins.

+V

IN

Q

L

1

O

C

Q

2

V

OUT

O

SS

C

SS

HIP6004B

GND

BOOT

C

BOOT

PHASE
V

CC

+12V

C

D

VCC

1

FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

Feedback Compensation

Figure 7 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V

) is regulated to the Reference voltage level. The

OUT

error amplifier (Error Amp) output (V
the oscillator (OSC) triangular wave to provide a pulse­width modulated (PWM) wave with an amplitude of V
the PHASE node.

) is compared with

E/A

IN

at

LOAD

8

6. Check Gain against Error Amplifier’s Open-Loop Gain.

7. Estimate Phase Margin - Repeat if Necessary.

Compensation Break Frequency Equations

Figure 8 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 8. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F
the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 8 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.

The compensation gain uses external impedance networks
Z

and ZIN to provide a stable, high bandwidth (BW)

FB

with the capabilities of

P2

The PWM wave is smoothed by the output filter (LO and CO).
The modulator transfer function is the small-signal transfer
function of V

OUT/VE/A

Gain and the output filter (L
break frequency at F
the modulator is simply the input voltage (V
peak-to-peak oscillator voltage ∆V

. This function is dominated by a DC

and CO), with a double pole

O

and a zero at F

LC

OSC

. The DC Gain of

ESR

) divided by the

IN

.

Modulator Break Frequency Equations

The compensation network consists of the error amplifier
(internal to the HIP6004B) and the impedance networks Z
and Z

. The goal of the compensation network is to provide

FB

a closed loop transfer function with the highest 0dB crossing
frequency (f

) and adequate phase margin. Phase margin

0dB

is the difference between the closed loop phase at f
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
R

, C1, C2, and C3) in Figure 7. Use these guidelines for

3

locating the poles and zeros of the compensation network:

1. Pick Gain (R

2. Place 1

3. Place 2

4. Place 1

ST

ND
ST

) for desired converter bandwidth.

2/R1

Zero Below Filter’s Double Pole (~75% FLC).

Zero at Filter’s Double Pole.

Pole at the ESR Zero.

5. Place 2ND Pole at Half the Switching Frequency.

0dB

and

, R2,

1

IN

9

HIP6004B

Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor value s are genera lly determined by
the ESR (Effective Series Resistance) and voltage rating
requirements rather than actual capacitance requirements.

High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. For example, Intel
recommends that the high frequency decoupling for the
Pentium Pro be composed of at least forty (40) 1µF ceramic
capacitors in the 1206 surface-mount package.

Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and cu rren t are
approximated by the following equations:

DI =

Fs x L

- V

V

IN

Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.

One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
HIP6004B will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.

OUT

V

OUT

x

V

IN

DV

OUT

= DI x ESR

The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:

L x I

=

t

RISE

where: I

TRAN

VIN - V

OUT

is the transient load current step, t

TRAN

t

FALL

response time to the application of load, and t

L x I

V

TRAN

OUT

RISE

FALL

is the

is the

=

response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
DACOUT setting. Be sure to check both of these equations
at the minimum and maximum output levels for the worst
case response time. With a +12V input, and output voltage
level equal to DACOUT, t

is the longest response time.

FALL

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q

turns on. Place the

1

small ceramic capacitors physically close to the MOSFETs
and between the drain of Q

and the source of Q2.

1

The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.

For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX
or equivalent) may be needed. For surface mount designs,
solid tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surge­current at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.

MOSFET Selection/Considerations

The HIP6004B requires 2 N-Channel power MOSFETs. These
should be selected based upon r
requirements, and thermal management requirements.

In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor (see the equations

DS(ON)

, gate supply

10

below). Only the upper MOSFET has switching losses, since
the Schottky rectifier clamps the switching node before the
synchronous rectifier turns on. These equations assume linear
voltage-current transitions and do not adequately model power
loss due the reverse-recovery of the lower MOSFET’s body
diode. The gate-charge losses are dissipated by the HIP6004B
and don't heat the MOSFETs. However, large gate-charge
increases the switching interval, t

which increases the upper

SW

MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.

OUT

1
2

/ VIN,

Io x VIN x tSW x F

S

P
P

Where: D is the duty cycle = V

UPPER

LOWER

= Io2 x r

= Io2 x r

t

is the switch ON time, and

SW

is the switching frequency.

F

S

DS(ON)

DS(ON)

x D +
x (1 - D)

Standard-gate MOSFETs are normally recommended for
use with the HIP6004B. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET’s absolute gate-to­source voltage rating determine whether logic-level
MOSFETs are appropriate.

Figure 9 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from V

. The boot capacitor, C

CC

BOOT

develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V
less the boot diode drop (V

) when the lower MOSFET, Q2

D

CC

turns on. Logic-level MOSFETs can only be used if the
MOSFET’s absolute gate-to-source voltage rating exceeds
the maximum voltage applied to V

+12V

D

BOOT

CC

.

Figure 10 shows the upper gate drive supplied by a direct
connection to V
converter systems where the main input voltage is +5V

. This option should only be used in

CC

DC

or
less. The peak upper gate-to-source voltage is approximately
V

less the input supply. For +5V main power and +12VDC

CC

for the bias, the gate-to-source voltage of Q
level MOSFET is a good choice for Q
MOSFET can be used for Q

if its absolute gate-to-source

2

voltage rating exceeds the maximum voltage applied to V

is 7V. A logic-

1

and a logic-level

1

CC

Schottky Selection

Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency will drop
one or two percent as a result. The diode’s rated reverse
breakdown voltage must be greater than the maximum
input voltage.

.

V

CC

HIP6004B

-

+

BOOT

UGATE
PHASE

LGATE
PGND

GND

C

11

BOOT

+5V OR +12V

Q1

Q2

NOTE:

NOTE:
V

G-S

≈ VCC

HIP6004B

HIP6004B DC-DC Converter Application Circuit

Figure 11 shows an application circuit of a DC-DC Converter
for an Intel Pentium Pro microprocessor. Detailed
information on the circuit, including a complete
Bill-of-Materials and circuit board description, can be found

- 1µHµ

VIN =

+5V

OR

+12V

0.1µF

L

F

1

1

5x 1000µF

0.1µF

SS

V

SEN

RT

VID0
VID1
VID2
VID3
VID4

FB

0.1µF

C

IN

3

1
20
4

5
6
7
8

10

2.2nF

8.2nF

D/A

+12V

PROTECTION

OSC

HIP6004B

+

-

9

20K

MONITOR

V

CC

18

AND

-

+

COMP

2N6394

OVP

19

11

in Application Note AN9672. Although the Application Note
details the HIP6004, the same evaluation platform can be
used to evaluate the HIP6004B.

2x 1µF

2K

D

1

1000pF

1K

0.1µF

Q

1

Q

2

L

2

3µH

D

2

C

9x 1000µF

OUT

+V

O

12
15

14
13

17
16

GND

2

OCSET
PGOOD

BOOT

UGATE
PHASE

LGATE
PGND

1.33K

15

Component Selection Notes:

C

Each 1000µF 6.3W VDC, Sanyo MV-GX or Equivalent.

OUT -

C

Each 330µF 25W VDC, Sanyo MV-GX or Equivalent.

IN -

- Core: Micrometals T50-52B; Each Winding: 10 Turns of 16A WG.

L

2

L

- Core: Micrometals T50-52; Winding: 5 Turns of 18AWG.

1

D

- 1N4148 or Equivalent.

1

- 3A, 40V Schottky, Motorola MBR340 or Equivalent.

D

2

Q

, Q2 - Intersil MOSFET; RFP70N03.

1

FIGURE 11. PENTIUM PRO DC-DC CONVERTER

12

HIP6004B

Small Outline Plastic Packages (SOIC)

N

INDEX
AREA

123

-A­D

e

B

0.25(0.010) C AMB

E

-B-

SEATING PLANE

A

-C-

S

M

0.25(0.010) B

H

α

µ

A1

0.10(0.004)

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In­terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact.

M

L

h x 45

M

o

M20.3 (JEDEC MS-013-AC ISSUE C)

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.014 0.019 0.35 0.49 9
C 0.0091 0.0125 0.23 0.32 ­D 0.4961 0.5118 12.60 13.00 3
E 0.2914 0.2992 7.40 7.60 4

e 0.050 BSC 1.27 BSC -

H 0.394 0.419 10.00 10.65 -

h 0.010 0.029 0.25 0.75 5

C

L 0.016 0.050 0.40 1.27 6

N20 207

o

α

0

o

8

o

0

o

8

NOTESMIN MAX MIN MAX

-

Rev. 1 1/02

13

HIP6004B

Thin Shrink Small Outline Plastic Packages (TSSOP)

N

INDEX
AREA

123

0.05(0.002)

-A­D

e

b

0.10(0.004) C AM BS

E1

-B-

SEATING PLANE

A

-C-

M

0.25(0.010) BM M

E

α

A1

0.10(0.004)

GAUGE

PLANE

0.25

0.010

A2

L

c

NOTES:

1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.

5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen­sion at maximum material condition. Minimum space between protru­sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)

M20.173

20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.047 - 1.20 ­A1 0.002 0.006 0.05 0.15 ­A2 0.031 0.051 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.252 0.260 6.40 6.60 3
E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N20 207

o

α

0

o

8

o

0

o

8

Rev. 1 6/98

NOTESMIN MAX MIN MAX

-

14

HIP6004B

Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data she ets are current before placin g orders. Information furn ished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or othe rwise under any patent or patent righ ts of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

15