Intersil Corporation HIP4081A Datasheet

1

HIP4081A

80V/2.5A Peak, High Frequency

Full Bridge FET Driver

Description

The HIP4081A is a high frequency, medium voltage Full
Bridge N-Channel FET driver IC, available in 20 lead plastic
SOIC and DIP packages. The HIP4081A can drive every
possible switch combination except those which would
cause a shoot-through condition. The HIP4081A can switch
at frequencies up to 1MHz and is well suited to driving Voice
Coil Motors, high-frequency Class D audio amplifiers, and
power supplies.

For example, the HIP4081A can drive medium voltage brush
motors, and two HIP4081As can be used to drive high per­formance stepper motors, since the short minimum “on-time”
can provide fine micro-stepping capability.

Short propagation delays of approximately 55ns maximizes
control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion, resulting
in rapid, precise control of the driven load.

A similar part, the HIP4080A, includes an on-chip input com­parator to create a PWM signal from an external triangle
wave and to facilitate “hysteresis mode” switching.

The Application Note for the HIP4081A is the AN9405.

Ordering Information

PART

NUMBER

TEMP RANGE

(oC) PACKAGE PKG. NO.

HIP4081AIP -40 to 85 20 Ld PDIP E20.3
HIP4081AIB -40 to 85 20 Ld SOIC (W) M20.3

Features

• Independently Drives 4 N-Channel FET in Half Bridge
or Full Bridge Configurations

• Bootstrap Supply Max Voltage to 95V

DC

• Drives 1000pF Load at 1MHz in Free Air at 50oC with
Rise and Fall Times of Typically 10ns

• User-Programmable Dead Time

• On-Chip Charge-Pump and Bootstrap Upper Bias
Supplies

• DIS (Disable) Overrides Input Control

• Input Logic Thresholds Compatible with 5V to 15V
Logic Levels

• Very Low Power Consumption

• Undervoltage Protection

Applications

• Medium/Large Voice Coil Motors

• Full Bridge Power Supplies

• Class D Audio Power Amplifiers

• High Performance Motor Controls

• Noise Cancellation Systems

• Battery Powered Vehicles

• Peripherals

• U.P.S.

November 1996

Pinout

HIP4081A (PDIP, SOIC)

TOP VIEW

11

12

13

14

15

16

17

18

20
19

10

9

8

7

6

5

4

3

2

1

BHB

BHI
DIS
V

SS

BLI
ALI

HDEL

AHI

LDEL

AHB

BHO

BLO
BLS
V

DD

BHS

V

CC

ALS
ALO
AHS
AHO

Application Block Diagram

80V

GND

LOAD

HIP4081A

GND

12V

AHI

ALI

BLI

BHI

BLO

BHS

BHO

ALO
AHS
AHO

File Number 3659.5

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

2

HIP4081A

Functional Block Diagram

(1/2 HIP4081A)

Typical Application

(PWM Mode Switching)

CHARGE

PUMP

V

DD

AHI

DIS

ALI

HDEL

LDEL

V

SS

TURN-ON

DELAY

TURN-ON

DELAY

DRIVER

DRIVER

AHB

AHO

AHS

V

CC

ALO

ALS

C

BF

TO VDD (PIN 16)

C

BS

D

BS

HIGH VOLTAGE BUS ≤ 80V

DC

+12V

DC

LEVEL SHIFT

AND LATCH

14

10

11

12

15

13

16

7

3

6

8

9

4

BIAS

SUPPLY

UNDER-

VOLTAGE

11

12

13

14

15

16

17

18

20
19

10

9

8

7

6

5

4

3

2

1

BHB
BHI
DIS
V

SS

BLI
ALI

HDEL

AHI

LDEL
AHB

BHO

BLO

BLS
V

DD

BHS

V

CC

ALS
ALO
AHS

AHO

80V

12V

+

-

12V

DIS

GND

6V

GND

TO OPTIONAL

CURRENT CONTROLLER

PWM

LOAD

INPUT

HIP4081/HIP4081A

3

HIP4081A

Absolute Maximum Ratings Thermal Information

Supply Voltage, VDD and VCC. . . . . . . . . . . . . . . . . . . . -0.3V to 16V

Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V

Voltage on AHS, BHS. . . . -6.0V (Transient) to 80V (25oC to 125oC)

Voltage on AHS, BHS. . . -6.0V (Transient) to 70V (-55oC to 125oC)

Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient)

Voltage on AHB, BHB. . . . . . . . .V

AHS, BHS

-0.3V to V

AHS, BHS

+V

DD

Voltage on ALO, BLO . . . . . . . . . . . . . V

ALS, BLS

-0.3V to VCC +0.3V

Voltage on AHO, BHO . . . . . . . V

AHS, BHS

-0.3V to V

AHB, BHB

+0.3V

Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA

Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20V/ns

NOTE: All Voltages relative to VSS, unless otherwise specified.

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Storage Temperature Range. . . . . . . . . . . . . . . . . . .-65oC to 150oC

Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . . 125oC

Lead Temperature (Soldering 10s)) . . . . . . . . . . . . . . . . . . . . 300oC

(For SOIC - Lead Tips Only

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Operating Conditions

Supply Voltage, VDD and VCC. . . . . . . . . . . . . . . . . . . +9.5V to +15V

Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V

Voltage on AHB, BHB. . . . . . . . . . V

AHS, BHS

+5V to V

AHS, BHS

+15V

Input Current, HDEL and LDEL. . . . . . . . . . . . . . . . -500µA to -50µA

Operating Ambient Temperature Range . . . . . . . . . . .-40oC to 85oC

Electrical Specifications V

DD

= VCC = V

AHB

= V

BHB

= 12V, VSS = V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

= 100K and

TA = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS

TJ = 25oC

TJS = -40oC

TO 125oC

UNITSMIN TYP MAX MIN MAX

SUPPLY CURRENTS AND CHARGE PUMPS

VDD Quiescent Current I

DD

All inputs = 0V 8.5 10.5 14.5 7.5 14.5 mA

VDD Operating Current I

DDO

Outputs switching f = 500kHz 9.5 12.5 15.5 8.5 15.5 mA

VCC Quiescent Current I

CC

All Inputs = 0V, I

ALO

= I

BLO

= 0 - 0.1 10 - 20 µA

VCC Operating Current I

CCO

f = 500kHz, No Load 1 1.25 2.0 0.8 3 mA

AHB, BHB Quiescent Current ­Qpump Output Current

I

AHB

, I

BHB

All Inputs = 0V, I

AHO

= I

BHO

= 0

VDD = VCC = V

AHB

= V

BHB

= 10V

-50 -30 -11 -60 -10 µA

AHB, BHB Operating Current I

AHBO

, I

BHBO

f = 500kHz, No Load 0.6 1.2 1.5 0.5 1.9 mA

AHS, BHS, AHB, BHB Leakage
Current

I

HLK

V

BHS

= V

AHS

= 80V,

V

AHB

= V

BHB

= 93V

- 0.02 1.0 - 10 µA

AHB-AHS, BHB-BHS Qpump
Output Voltage

V

AHB-VAHS

V

BHB-VBHS

I

AHB

= I

AHB

= 0, No Load 11.5 12.6 14.0 10.5 14.5 V

INPUT PINS: ALI, BLI, AHI, BHI, AND DIS

Low Level Input Voltage V

IL

Full Operating Conditions - - 1.0 - 0.8 V

High Level Input Voltage V

IH

Full Operating Conditions 2.5 - - 2.7 - V
Input Voltage Hysteresis - 35 - - - mV
Low Level Input Current I

IL

VIN = 0V, Full Operating Conditions -130 -100 -75 -135 -65 µA
High Level Input Current I

IH

VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 µA

TURN-ON DELAY PINS: LDEL AND HDEL

LDEL, HDEL Voltage V

HDEL

, V

LDELIHDEL

= I

LDEL

= -100µA 4.9 5.1 5.3 4.8 5.4 V

GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO

Low Level Output Voltage V

OL

I

OUT

= 100mA 0.7 0.85 1.0 0.5 1.1 V

High Level Output Voltage VCC-V

OHIOUT

= -100mA 0.8 0.95 1.1 0.5 1.2 V

Peak Pullup Current IO+V

OUT

= 0V 1.7 2.6 3.8 1.4 4.1 A

Peak Pulldown Current IO-V

OUT

= 12V 1.7 2.4 3.3 1.3 3.6 A

4

HIP4081A

Undervoltage, Rising Threshold UV+ 8.1 8.8 9.4 8.0 9.5 V
Undervoltage, Falling Threshold UV- 7.6 8.3 8.9 7.5 9.0 V
Undervoltage, Hysteresis HYS 0.25 0.4 0.65 0.2 0.7 V

Switching Specifications V

DD

= VCC = V

AHB

= V

BHB

= 12V, VSS = V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

= 10K,

CL = 1000pF.

PARAMETER SYMBOL TEST CONDITIONS

TJ = 25oC

TJS = -40oC

TO 125oC

UNITSMIN TYP MAX MIN MAX

Lower Turn-off Propagation Delay
(ALI-ALO, BLI-BLO)

T

LPHL

- 30 60 - 80 ns

Upper Turn-off Propagation Delay
(AHI-AHO, BHI-BHO)

T

HPHL

- 35 70 - 90 ns

Lower Turn-on Propagation Delay
(ALI-ALO, BLI-BLO)

T

LPLH

R

HDEL

=R

LDEL

= 10K - 45 70 - 90 ns

Upper Turn-on Propagation Delay
(AHI-AHO, BHI-BHO)

T

HPLH

R

HDEL

=R

LDEL

= 10K - 60 90 - 110 ns

Rise Time T

R

- 10 25 - 35 ns

Fall Time T

F

- 10 25 - 35 ns

Turn-on Input Pulse Width T

PWIN-ONRHDEL

=R

LDEL

= 10K 50 - - 50 - ns

Turn-off Input Pulse Width T

PWIN-OFFRHDEL

=R

LDEL

= 10K 40 - - 40 - ns

Turn-on Output Pulse Width T

PWOUT-ONRHDEL

=R

LDEL

= 10K 40 - - 40 - ns

Turn-off Output Pulse Width T

PWOUT-OFFRHDEL

=R

LDEL

= 10K 30 - - 30 - ns

Disable Turn-off Propagation Delay
(DIS - Lower Outputs)

T

DISLOW

- 45 75 - 95 ns

Disable Turn-off Propagation Delay
(DIS - Upper Outputs)

T

DISHIGH

- 55 85 - 105 ns

Disable to Lower Turn-on Propagation Delay
(DIS - ALO and BLO)

T

DLPLH

- 40 70 - 90 ns

Refresh Pulse Width (ALO and BLO) T

REF-PW

240 410 550 200 600 ns

Disable to Upper Enable (DIS - AHO and BHO) T

UEN

- 450 620 - 690 ns

TRUTH TABLE

INPUT OUTPUT

ALI, BLI AHI, BHI U/V DIS ALO, BLO AHO, BHO

XXX100
1X0010
010001
000000
XX1X00

NOTE: X signifies that input can be either a “1” or “0”.

Electrical Specifications V

DD

= VCC = V

AHB

= V

BHB

= 12V, VSS = V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

= 100K and

TA = 25oC, Unless Otherwise Specified (Continued)

PARAMETER SYMBOL TEST CONDITIONS

TJ = 25oC

TJS = -40oC

TO 125oC

UNITSMIN TYP MAX MIN MAX

5

HIP4081A

Pin Descriptions

PIN

NUMBER SYMBOL DESCRIPTION

1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-

strap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

2 BHI B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI

high level input to pre vent half-bridge shoot-through, see T ruth Tab le . DIS (Pin 3) high level input overrides BHI
high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA
pull-up to VDD will hold BHI high, so no connection is required if high-side and low-side outputs are to be con­trolled by the low-side input.

3 DIS DISable input. Logic lev el input that when taken high sets all four outputs lo w . DIS high overrides all other inputs.

When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of

0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold DIS high if this pin is not driven.
4VSSChip negative supply, generally will be ground.
5 BLI B Low-side Input. Logic lev el input that controls BLO driver (Pin 18). If BHI (Pin 2) is driven high or not connected

externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL

(Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels

of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold BLI high if this pin is not driven.
6 ALI A Low-side Input. Logic lev el input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected

externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL

(Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels

of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold ALI high if this pin is not driven.
7 AHI A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI

high level input to pre vent half-bridge shoot-through, see T ruth Tab le . DIS (Pin 3) high level input overrides AHI

high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA

pull-up to VDD will hold AHI high, so no connection is required if high-side and low-side outputs are to be con-

trolled by the low-side input.
8 HDEL High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on de-

lay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guar-

antees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is

approximately 5.1V.
9 LDEL Low-side turn-on DELay . Connect resistor from this pin to VSS to set timing current that defines the turn-on delay

of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees

no shoot-through by delaying the turn-on of the low-side drivers. LDEL ref erence v oltage is appro ximately 5.1V.

10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-

strap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this

pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

11 AHO A High-side Output. Connect to gate of A High-side power MOSFET.
12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of

bootstrap capacitor to this pin.

13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET.
14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET.
15 V

CC

Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap

diodes.

16 V

DD

Positive supply to lo wer gate drivers . Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4).

17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET.
18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET.
19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of

bootstrap capacitor to this pin.

20 BHO B High-side Output. Connect to gate of B High-side power MOSFET.

6

HIP4081A

Timing Diagrams

FIGURE 1. INDEPENDENT MODE

FIGURE 2. BISTATE MODE

FIGURE 3. DISABLE FUNCTION

U/V = DIS = 0

XLI

XHI

XLO

XHO

T

LPHL

T

HPHL

T

HPLH

T

LPLH

T

R

(10% - 90%)

T

F

(10% - 90%)

X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT

U/V = DIS = 0

XLI

XHI = HI OR NOT CONNECTED

XLO

XHO

U/V OR DIS

XLI

XHI

XLO

XHO

T

DLPLH

T

DIS

T

UEN

T

REF-PW

7

HIP4081A

T ypical Performance Curves

VDD = VCC = V

AHB

= V

BHB

= 12V, VSS = V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

=

100K and TA = 25oC, Unless Otherwise Specified

FIGURE 4. QUIESCENT I

DD

SUPPL Y CURRENT vs VDD SUPPL Y

VOLTAGE

FIGURE 5. I

DDO

, NO-LOAD IDD SUPPL Y CURRENT vs

FREQUENCY (kHz)

FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs

FREQUENCY (LOAD = 1000pF)

FIGURE 7. I

CCO

, NO-LOAD ICC SUPPL Y CURRENT vs

FREQUENCY (kHz) TEMPERATURE

FIGURE 8. I

AHB

, I

BHB

, NO-LOAD FLO ATING SUPPLY BIAS

CURRENT vs FREQUENCY

FIGURE 9. ALI, BLI, AHI, BHI LOW LEVEL INPUT CURRENT I

IL

vs TEMPERATURE

6 8 10 12 14

2.0

4.0

6.0

8.0

10.0

12.0

14.0

I

DD

SUPPLY CURRENT (mA)

VDD SUPPLY VOLTAGE (V)

0 100 200 300 400 500 600 700 800 900 1000

8.0

8.5

9.0

9.5

10.0

10.5

11.0

I

DD

SUPPLY CURRENT (mA)

SWITCHING FREQUENCY (kHz)

0 100 200 300 400 500 600 700 800 900 1000

0.0

5.0

10.0

15.0

20.0

25.0

30.0

FLOATING SUPPLY BIAS CURRENT (mA)

SWITCHING FREQUENCY (kHz)

0 100 200 300 400 500 600 700 800 900 1000

0.0

1.0

2.0

3.0

4.0

5.0

I

CC

SUPPLY CURRENT (mA)

SWITCHING FREQUENCY (kHz)

75oC
25oC

125

o

C

-40

o

C

0

o

C

0.5

1

1.5

2

2.5

200 600 800 1000

0 400

FLOATING SUPPLY BIAS CURRENT (mA)

SWITCHING FREQUENCY (kHz)

-50 -25 0 25 50 75 100 125

-120

-110

-100

-90

LOW LEVEL INPUT CURRENT (µA)

JUNCTION TEMPERATURE (oC)

8

HIP4081A

Typical Performance Curves

VDD = VCC = V

AHB

= V

BHB

= 12V, VSS = V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

=

10K and TA = 25oC, Unless Otherwise Specified

FIGURE 10. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP

VOLTAGE vs TEMPERATURE

FIGURE 11. UPPER DISABLE TURN-OFF PROPAGATION

DELAY T

DISHIGH

vs TEMPERATURE

FIGURE 12. DISABLE TO UPPER ENABLE, T

UEN

,

PROPAGATION DELAY vs TEMPERATURE

FIGURE 13. LOWER DISABLE TURN-OFF PR OP A GATION

DELAY T

DISLOW

vs TEMPERATURE

FIGURE 14. T

REF-PW

REFRESH PULSE WIDTH vs

TEMPERA TURE

FIGURE 15. DISABLE TO LO WER ENABLE T

DLPLH

PROPAGATION DELAY vs TEMPERATURE

-40 -20 0 20 40 60 80 100 120

10.0

11.0

12.0

13.0

14.0

15.0

NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V)

JUNCTION TEMPERATURE (oC)

-40 -20 0 20 40 60 80 100 120

30

40

50

60

70

80

PROPAGATION DELAY (ns)

JUNCTION TEMPERATURE (oC)

425

450

475

500

525

-50 -25 0 25 50 75 100 125 150
JUNCTION TEMPERATURE (oC)

PROPAGATION DELAY (ns)

-40 -20 0 20 40 60 80 100 120

30

40

50

60

70

80

PROPAGATION DELAY (ns)

JUNCTION TEMPERATURE (oC)

350

375

400

425

450

-50 -25 0 25 50 75 100 125 150

REFRESH PULSE WIDTH (ns)

JUNCTION TEMPERATURE (oC)

-40 -20 0 20 40 60 80 100 120

20

30

40

50

60

70

80

PROPAGATION DELAY (ns)

JUNCTION TEMPERATURE (oC)

9

HIP4081A

FIGURE 16. UPPER TURN-OFF PROP A GATION DELA Y T

HPHL

vs

TEMPERA TURE

FIGURE 17. UPPER TURN-ON PROPAGATION DELAY T

HPLH

vs

TEMPERA TURE

FIGURE 18. LOWER TURN-OFF PR OPA GATION DELA Y T

LPHL

vs

TEMPERA TURE

FIGURE 19. LOWER TURN-ON PR OPAGATION DELAY T

LPLH

vs

TEMPERA TURE

FIGURE 20. GATE DRIVE FALL TIME TF vs TEMPERATURE FIGURE 21. GATE DRIVE RISE TIME TR vs TEMPERATURE

Typical Performance Curves

VDD = VCC = V

AHB

= V

BHB

= 12V, VSS = V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

=

10K and TA = 25oC, Unless Otherwise Specified (Continued)

-40 -20 0 20 40 60 80 100 120

20

30

40

50

60

70

80

PROPAGATION DELAY (ns)

JUNCTION TEMPERATURE (oC)

-40 -20 0 20 40 60 80 100 120

20

30

40

50

60

70

80

PROPAGATION DELAY (ns)

JUNCTION TEMPERATURE (oC)

-40 -20 0 20 40 60 80 100 120

20

30

40

50

60

70

80

PROPAGATION DELAY (ns)

JUNCTION TEMPERATURE (oC)

-40 -20 0 20 40 60 80 100 120

20

30

40

50

60

70

80

PROPAGATION DELAY (ns)

JUNCTION TEMPERATURE (oC)

-40 -20 0 20 40 60 80 100 120

8.5

9.5

10.5

11.5

12.5

13.5

GATE DRIVE FALL TIME (ns)

JUNCTION TEMPERATURE (oC)

-40 -20 0 20 40 60 80 100 120

8.5

9.5

10.5

11.5

12.5

13.5

TURN-ON RISE TIME (ns)

JUNCTION TEMPERATURE (oC)

10

HIP4081A

Typical Performance Curves

VDD = VCC = V

AHB

= V

BHB

= 12V, VSS = V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

=

100K and TA = 25oC, Unless Otherwise Specified

FIGURE 22. V

LDEL

, V

HDEL

VOLTA GE vs TEMPERATURE FIGURE 23. HIGH LEVEL OUTPUT VOLT A GE VCC - VOH vs BIAS

SUPPLY AND TEMPERATURE AT 100mA

FIGURE 24. LOW LEVEL OUTPUT V OLTAGE VOL vs BIAS

SUPPLY AND TEMPERATURE AT 100mA

FIGURE 25. PEAK PULLDOWN CURRENT IOvs BIAS SUPPLY

VOLTAGE

FIGURE 26. PEAK PULLUP CURRENT IO+ vs BIAS SUPPL Y

VOLTAGE

FIGURE 27. LOW V OLTAGE BIAS CURRENT IDD(LESS

QUIESCENT COMPONENT) vs FREQUENCY AND
GATE LOAD CAPACITANCE

-40 -20 0 20 40 60 80 100 120

4.0

4.5

5.0

5.5

6.0

HDEL, LDEL INPUT VOLTAGE (V)

JUNCTION TEMPERATURE (oC)

10 12 14

0

250

500

750

1000

1250

1500

V

CC

- V

OH

(mV)

BIAS SUPPLY VOLTAGE (V)

75oC

25oC

125

o

C

-40

o

C

0oC

12 14

0

250

500

750

1000

1250

1500

V

OL

(mV)

BIAS SUPPLY VOLTAGE (V)

10

75oC

25oC

125

o

C

-40

o

C

0

o

C

6 7 8 9 10 11 12 13 14 15 16

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

GATE DRIVE SINK CURRENT (A)

VDD, VCC, V

AHB

, V

BHB

(V)

6 7 8 9 10 11 12 13 14 15 16

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

GATE DRIVE SINK CURRENT (A)

VDD, VCC, V

AHB

, V

BHB

(V)

1 10 100 10002 5 20 50 500200

0.1

1

10

100

500

50

5

0.5

200

20

2

0.2

LOW VOLTAGE BIAS CURRENT (mA)

SWITCHING FREQUENCY (kHz)

100pF

1,000pF

10,000pF

3,000pF

11

HIP4081A

FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCYAND BUS VOLTAGE

FIGURE 29. UNDERVOLTAGE LOCKOUT vs TEMPERATURE

FIGURE 30. MINIMUM DEAD-TIME vs DEL RESISTANCE

Typical Performance Curves

VDD = VCC = V

AHB

= V

BHB

= 12V, VSS = V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

=

100K and TA = 25oC, Unless Otherwise Specified (Continued)

10 100 100020 50 200 500

10

100

1000

20

50

200

500

LEVEL-SHIFT CURRENT (µA)

SWITCHING FREQUENCY (kHz)

8.2

8.4

8.6

8.8

9.0

50 25 0 25 50 75 100 125 150

UV+

UV-

TEMPERATURE (oC)

BIAS SUPPLY VOLTAGE, V

DD

(V)

10 50 100 150 200 250

0

30

60

90

120

150

HDEL/LDEL RESISTANCE (kΩ)

DEAD-TIME (ns)

12

HIP4081A

1

2

3

1

2

3

1

2

3

6

5

1

2

3

2

1

12

13

1

2

3

10

11

1

2

3

1
2
3
4
5
6
7
8
9

10 11

12

13

14

15

16

17

18

19

20

L1

R21

Q1

Q3

Q4

R22

L2

R23

C1

C3

JMPR1

R24

R30 R31

C2

R34

C4

CR2

CR1

Q2

JMPR5

JMPR3

JMPR2

JMPR4

R33

C5

C6

CX CY

C8

U1

CW CW

+

B+

IN2 IN1

BO

OUT/BLI

IN-/AHI

COM

IN+/ALI

+12V

+12V

BLS

AO

HEN/BHI

ALS

CD4069UB

CD4069UB

CD4069UB

CD4069UB

HIP4080A/81A

SECTION

CONTROL LOGIC

POWER SECTION

DRIVER SECTION

AHOAHB

AHSLDEL

ALOHDEL

ALSIN-/AHI

V

CC

IN+/ALI

V

DD

OUT/BLI

BLSV

SS

BLODIS

BHSHEN/BHI

BHOBHB

R29

U2

U2

U2

U2

43

89

R32

I

O

O

CD4069UB

CD4069UB

ENABLE IN

U2

U2

NOTES:

1. DEVICE CD4069UB PIN 7 = COM, PIN 14 = +12V.

2. COMPONENTS L1, L2, C1, C2, CX, CY, R30, R31, NOT SUPPLIED.
REFER TO APPLICATION NOTE FOR DESCRIPTION OF INPUT
LOGIC OPERATION TO DETERMINE JUMPER LOCATIONS FOR
JMPR1 - JMPR4.

FIGURE 31. HIP4081A EVALUATION PC BOARD SCHEMATIC

13

HIP4081A

R22

1

Q3

L1

JMPR2

JMPR5

R31

R33

CR2

R23

R24

R27

R28

R26

1

Q4

1

Q2

JMPR3

U1

R21

GND

L2

C3

C4

JMPR4

JMPR1

R30

CR1

U2

R34

R32

I

O

C8

R29

C7

C6

C5

CY

CX

1

Q1

COM

+12V

B+

IN1

IN2

AHO

BHO

ALO

BLO
BLS

BLS

LDEL

HDEL

DIS

ALS

ALS

O

+

+

HIP4080/81

FIGURE 32. HIP4081A EVALUATION BOARD SILKSCREEN

14

HIP4081A

E20.3 (JEDEC MS-001-AD ISSUE D)

20 LEAD DUAL-IN-LINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 ­B1 0.045 0.070 1.55 1.77 8

C 0.008 0.014 0.204 0.355 -

D 0.980 1.060 24.89 26.9 5
D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

e

A

0.300 BSC 7.62 BSC 6

e

B

- 0.430 - 10.92 7

L 0.115 0.150 2.93 3.81 4

N20 209

Rev. 0 12/93

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protru­sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).

6. E and are measured with the leads constrained to be per­pendicular to datum .

7. eB and eC are measured at the lead tips with the leads uncon­strained. eC must be zero or greater.

8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).

C

L

E

e

A

C

e

B

e

C

-B-

E1

INDEX

1 2 3 N/2

N

AREA

SEATING

BASE

PLANE

PLANE

-C-

D1
B1

B

e

D

D1

A

A2

L

A1

-A-

0.010 (0.25) C AMB

S

e

A

-C-

Dual-In-Line Plastic Packages (PDIP)

15

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: [phone]
FAX: [phone]

EUROPE

Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: [phone]
FAX: [phone]

ASIA

Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: [phone]
FAX: [phone]

HIP4081A

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In­terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact.

INDEX
AREA

E

D

N

123

-B-

0.25(0.010) C AMB

S

e

-A-

L

B

M

-C-

A1

A

SEATING PLANE

0.10(0.004)

h x 45

o

C

H

0.25(0.010) B

M

M

α

M20.3 (JEDEC MS-013-AC ISSUE C)

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.4961 0.5118 12.60 13.00 3
E 0.2914 0.2992 7.40 7.60 4

e 0.050 BSC 1.27 BSC -

H 0.394 0.419 10.00 10.65 -

h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6

N20 207

α

0

o

8

o

0

o

8

o

-

Rev. 0 12/93

Small Outline Plastic Packages (SOIC)

HIP4081A