Intersil Corporation HIP4081 Datasheet

November 1996

HIP4081

80V/2.5A Peak, High Frequency

Full Bridge FET Driver

Features

• Independently Drives 4 N-Channel FET in Half Bridge or Full Bridge Conﬁgurations

• Bootstrap Supply Max Voltage to 95V

• Drives 1000pF Load at 1MHz in Free Air at 50oC with Rise and Fall Times of Typically 10ns

• User-Programmable Dead Time

• On-Chip Charge-Pump and Bootstrap Upper Bias Supplies

• DIS (Disable) Overrides Input Control

• Input Logic Thresholds Compatible with 5V to 15V Logic Levels

• Very Low Power Consumption

Applications

• Medium/Large Voice Coil Motors

• Full Bridge Power Supplies

• Class D Audio Power Ampliﬁers

• High Performance Motor Controls

• Noise Cancellation Systems

• Battery Powered Vehicles

• Peripherals

• U.P.S.

Ordering Information

PART

NUMBER

HIP4081IP -40 to 85 20 Lead Plastic DIP E20.3 HIP4081IB -40 to 85 20 Lead Plastic SOIC M20.3

TEMP.

RANGE (oC) PACKAGE

PKG.

NUMBER

Description

The HIP4081 is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 20 lead plastic SOIC and DIP packages. The HIP4081 can drive every possible switch combination except those which would cause a shoot-through condition. The HIP4081 can switch at frequencies up to 1MHz andssssss is well suited to driving Voice Coil Motors, high-frequency Class D audio ampliﬁers, and power supplies.

For example, the HIP4081 can drive medium voltage brush motors, and two HIP4081s can be used to drive high performance stepper motors, since the short minimum “on-time” can provide ﬁne micro-stepping capability.

Short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in rapid, precise control of the driven load.

A similar part, the HIP4080, includes an on-chip input comparator to create a PWM signal from an external triangle wave and to facilitate “hysteresis mode” switching.

See Application Note AN9325 for HIP4081, Intersil AnswerFAX, (407) 724-7800, document #99325. Intersil web home page: http://www.semi.intersil.com

Similar part HIP4081A includes undervoltage circuitr y which does not require the circuitry shown in Figure 30 of this data sheet.

Pinout

HIP4081

(PDIP, SOIC)

TOP VIEW

BHB

BHI

DIS

BLI

ALI

AHI

HDEL

LDEL

AHB

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207

BHO

BHS

BLO

BLS

ALS

ALO

AHS AHO

File Number 3556.7

Application Block Diagram

12V

BHI BLI

HIP4081

BHO BHS BLO

HIP4081

80V

LOAD

ALI AHI

GND

Functional Block Diagram

CHARGE

PUMP

AHI

DIS

ALI

ALO AHS AHO

(1/2 HIP4081)

LEVEL SHIFT

AND LATCH

TURN-ON

DELAY

TURN-ON

DELAY

DRIVER

GND

AHB

AHO

AHS

ALO

ALS

HIGH VOLTAGE BUS ≤ 80V

TO VDD (PIN 16)

+12V

BIAS

SUPPLY

HDEL

LDEL

HIP4081

Typical Application (PWM Mode Switching)

80V

12V

DIS

PWM

INPUT

TO OPTIONAL

CURRENT CONTROLLER

GND

BHB BHI

DIS

BLI

ALI

AHI

HDEL

LDEL

AHB

BHO

BHS BLO

BLS V

ALS ALO AHS

AHO

20 19 18 17 16 15 14 13 12 11

12V

LOAD

GND

HIP4081

Absolute Maximum Ratings Thermal Information (Typical, Note 1)

Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . -0.3V to 16V

Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD +0.3V

Voltage on AHS, BHS. . . . -6.0V (Transient) to 80V (25oC to 125oC)

Voltage on AHS, BHS. . . -6.0V (Transient) to 70V (-55oC to 125oC)

Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient)

Voltage on AHB, BHB. . . . . . . V

AHS, BHS

Voltage on ALO, BLO . . . . . . . . . . . . V

Voltage on AHO, BHO . . . . . .V

AHS, BHS

-0.3V to V

ALS, BLS

-0.3V to V

AHS, BHS

+16V

-0.3V to VCC +0.3V

AHB, BHB

+0.3V

Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA

Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20V/ns

NOTE: All voltages are relative to pin 4, VSS, unless otherwise

speciﬁed.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Operating Conditions

Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . +6V to +15V

Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V

Storage Temperature Range. . . . . . . . . . . . . . . . . . .-65oC to 150oC

Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . . 125oC

Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . . 300oC

(For SOIC - Lead Tips Only)

Thermal Resistance, Junction-Ambient

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85oC/W

DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75oC/W

Voltage on AHB, BHB . . . . . . . . V

AHS, BHS

+5V to V

AHS, BHS

+15V

Input Current, HDEL and LDEL. . . . . . . . . . . . . . . . -500µA to -50µA

Operating Ambient Temperature Range . . . . . . . . . . .-40oC to 85oC

Electrical Speciﬁcations V

= VCC = V

AHB

= V

BHB

= 12V, VSS = V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

= 100K

and TA = 25oC, Unless Otherwise Speciﬁed

TJS = -40oC

TJ = 25oC

PARAMETER SYMBOL TEST CONDITIONS

TO 125oC

UNITSMIN TYP MAX MIN MAX

SUPPLY CURRENTS AND CHARGE PUMPS

VDD Quiescent Current I VDD Operating Current I VCC Quiescent Current I VCC Operating Current I AHB, BHB Quiescent Current -

AHB

Qpump Output Current AHB, BHB Operating Current I

AHBO

AHS, BHS, AHB, BHB Leakage Current I AHB-AHS, BHB-BHS Qpump

Output Voltage

AHB-VAHS

BHB-VBHS

DDO

CCO

, I

HLK

All Inputs = 0V 7 9 11 6 12 mA Outputs Switching f = 500kHz 8 9.5 12 7 13 mA All Inputs = 0V, I

ALO

= I

= 0 - 0.1 10 - 20 µA

BLO

f = 500kHz, No Load 1 1.25 2.0 0.8 3 mA All Inputs = 0V, I

BHB

VDD = VCC = V f = 500kHz, No Load 0.5 0.9 1.3 0.4 1.7 mA

BHBO

= V

AHS

BHS

= I

AHB

= 0, No Load 11.5 12.6 14.0 10.5 14.5 V

AHB

= V

AHO

AHB

= I

= V

= 0

BHO

= 10V

BHB

= V

= 95V - 0.02 1.0 - 10 µA

BHB

-50 -30 -15 -60 -10 µA

INPUT PINS: ALI, BLI, AHI, BHI, AND DIS

Low Level Input Voltage V High Level Input Voltage V

Full Operating Conditions - - 1.0 - 0.8 V

Full Operating Conditions 2.5 - - 2.7 - V Input Voltage Hysteresis -35---mV Low Level Input Current I High Level Input Current I

IL IH

VIN = 0V, Full Operating Conditions -130 -100 -75 -135 -65 µA

VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 µA TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage V

HDEL,VLDELIHDEL

= I

= -100µA 4.9 5.1 5.3 4.8 5.4 V

LDEL

GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO

Low Level Output Voltage V

High Level Output Voltage VCC-V

OUT

OHIOUT

= 100mA 0.7 0.85 1.0 0.5 1.1 V = -100mA 0.8 .95 1.1 0.5 1.2 V

HIP4081

Electrical Speciﬁcations V

= VCC = V

AHB

= V

BHB

= 12V, VSS = V

and TA = 25oC, Unless Otherwise Speciﬁed (Continued)

PARAMETER SYMBOL TEST CONDITIONS

Peak Pullup Current IO+V Peak Pulldown Current IO-V

Switching Speciﬁcations V

= VCC = V

AHB

= V

OUT OUT

BHB

CL = 1000pF

PARAMETER SYMBOL TEST CONDITIONS

Lower Turn-off Propagation Delay

LPHL

(ALI-ALO, BLI-BLO) Upper Turn-off Propagation Delay

HPHL

(AHI-AHO, BHI-BHO) Lower Turn-on Propagation Delay

LPLH

(ALI-ALO, BLI-BLO) Upper Turn-on Propagation Delay

HPLH

(AHI-AHO, BHI-BHO) Rise Time T Fall Time T Turn-on Input Pulse Width T Turn-off Input Pulse Width T Disable Turn-off Propagation Delay

R F

PWIN-ON

PWIN-OFF

DISLOW

(DIS - Lower Outputs) Disable Turn-off Propagation Delay

DISHIGH

(DIS - Upper Outputs) Disable to Lower Turn-on Propagation Delay

DLPLH

(DIS - ALO and BLO) Refresh Pulse Width (ALO and BLO) T Disable to Upper Enable (DIS - AHO and BHO) T

REF-PW

HEN

= V

ALS

BLS

AHS

BHS

= 0V, R

HDEL

= R

LDEL

= 100K

TJS = -40oC

TJ = 25oC

TO 125oC

UNITSMIN TYP MAX MIN MAX

= 0V 1.7 2.6 3.8 1.4 4.1 A = 12V 1.7 2.4 3.3 1.3 3.6 A

= 12V, VSS = V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

= 10K,

TJS = 40oC

TJ = +25oC

TO 125oC

UNITSMIN TYP MAX MIN MAX

- 30 60 - 80 ns

- 35 70 - 90 ns

- 45 70 - 90 ns

- 60 90 - 110 ns

- 10 25 - 35 ns

- 10 25 - 35 ns 50 - - 50 - ns 40 - - 40 - ns

- 45 75 - 95 ns

- 55 85 - 105 ns

- 35 70 - 90 ns

160 260 380 140 420 ns

- 335 500 - 550 ns

INPUT OUTPUT

ALI, BLI AHI, BHI DIS ALO, BLO AHO, BHO

XX1 0 0 1X0 1 0 010 0 1 000 0 0

NOTE: X signiﬁes that input can be either a “1” or “0”.

TRUTH TABLE

HIP4081

Pin Descriptions

NUMBER SYMBOL DESCRIPTION

1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-

strap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

2 BHI B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI

high level input to pre vent half-bridge shoot-through, see T ruth Table. DIS (Pin 3) high level input overrides BHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold BHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input.

3 DIS Disable input. Logic level input that when tak en high sets all f our outputs low . DIS high o verrides all other inputs.

When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of

0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold DIS high if this pin is not driven. 4VSSChip negative supply, generally will be ground. 5 BLI B Low-side Input. Logic level input that controls BLO driver (Pin 18). If BHI (Pin 2) is driven high or not connected

externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL

(Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels

of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold BLI high if this pin is not driven. 6 ALI A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected

externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL

(Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels

of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold ALI high if this pin is not driven. 7 AHI A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI

high level input to pre vent half-bridge shoot-through, see T ruth Table. DIS (Pin 3) high level input overrides AHI

high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA

pull-up to VDD will hold AHI high, so no connection is required if high-side and low-side outputs are to be con-

trolled by the low-side input. 8 HDEL High-side turn-on DELay . Connect resistor from this pin to VSS to set timing current that deﬁnes the turn-on de-

lay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guar-

antees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is

approximately 5.1V. 9 LDEL Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that deﬁnes the turn-on delay

of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees

no shoot-through by delaying the turn-on of the low-side drivers. LDEL ref erence v oltage is appro ximately 5.1V.

10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-

strap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this

pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

11 AHO A High-side Output. Connect to gate of A High-side power MOSFET. 12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of

bootstrap capacitor to this pin.

13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET. 14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET. 15 V

16 V 17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET. 18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET. 19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of

20 BHO B High-side Output. Connect to gate of B High-side power MOSFET.

Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap

diodes.

Positive supply to lo wer gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4).

bootstrap capacitor to this pin.

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