INTERSIL HIP 4080 AIPZ Datasheet [it]

®

HIP4080A

Data Sheet FN3658.5

80V/2.5A Peak, High Frequency Full Bridge
FET Driver

The HIP4080A is a high frequency, medium voltage Full
Bridge N-Channel FET driver IC, available in 20 lead plastic
SOIC and DIP packages. The HIP4080A includes an input
comparator, used to facilitate the “hysteresis” and PWM
modes of operation. Its HEN (high enable) lead can force
current to freewheel in the bottom two external power
MOSFETs, maintaining the upper power MOSFETs off.
Since it can switch at frequencies up to 1MHz, the HIP4080A
is well suited for driving Voice Coil Motors, switching power
amplifiers and power supplies.

HIP4080A can also drive medium voltage brush motors, and
two HIP4080As can be used to drive high performance
stepper motors, since the short minimum “on-time” can
provide fine micro-stepping capability.

Short propagation delays of approximately 55ns maximizes
control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion, resulting
in precise control of the driven load.

The similar HIP4081A IC allows independent control of all 4
FETs in an Full Bridge configuration.

The Application Note for the HIP4080A is AN9404.

Ordering Information

PART

NUMBER

HIP4080AIP -40
HIP4080AIB -40

TEMPERATURE

RANGE PACKAGE

o

C to +85oC 20 Lead Plastic DIP

o

C to +85oC 20 Lead Plastic SOIC (W)

February 2003

Features

• Drives N-Channel FET Full Bridge Including High Side
Chop Capability

• Bootstrap Supply Max Voltage to 95VDC

o

• Drives 1000pF Load at 1MHz in Free Air at +50

C with

Rise and Fall Times of Typically 10ns

• User-Programmable Dead Time

• Charge-Pump and Bootstrap Maintain Upper Bias
Supplies

• DIS (Disable) Pin Pulls Gates Low

• Input Logic Thresholds Compatible with 5V to 15V Logic
Levels

• V ery Low Power Consumption

• Undervoltage Protection

Applications

• Medium/Large Voice Coil Motors

• Full Bridge Power Supplies

• Switching Power Amplifiers

• High Performance Motor Controls

• Noise Cancellation Systems

• Battery Powered Vehicles

• Peripherals

•U.P.S.

Pinout

HIP4080A

(PDIP, SOIC)

TOP VIEW

1

BHB
HEN

2

DIS

3

V

4

SS

OUT

5

IN+

6

IN-

7

HDEL

8

LDEL

9

AHB

10

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2003. All Rights Reserved

20

BHO
BHS

19

BLO

18

BLS

17

V

16

DD

V

15

CC

ALS

14

ALO

13

AHS

12

AHO

11

Application Block Diagram

HEN
DIS

HIP4080A

12V

BHO
BHS
BLO

HIP4080A

80V

LOAD

IN+
IN-

ALO
AHS
AHO

GND

Functional Block Diagram (1/2 HIP4080A)

V

DD

HEN

DIS

OUT

IN+

IN

UNDER-

VOLTAGE

16

2

3

5

6

+

_

-

7

CHARGE

PUMP

LEVEL SHIFT

AND LATCH

TURN-ON

DELAY

TURN-ON

DELAY

DRIVER

DRIVER

GND

10

11

12

15

13

14

AHB

AHO

AHS

V

CC

ALO

ALS

HIGH VOLTAGE BUS ≤ 80VDC

C

BS

D

BS

TO VDD (PIN 16)

+12VDC

BIAS

C

BF

SUPPLY

HDEL

LDEL

V

SS

8

9

4

2

HIP4080A

Typical Application (Hysteresis Mode Switching)

80V

6V

IN

12V

DIS

GND

1

BHB

2

HEN

3

DIS

4

V

SS

OUT

5

IN+

6

IN-

7

HDEL

8

LDEL

9

AHB

10

BHO

BHS
BLO

BLS
V
V
ALS

HIP4080A/HIP4080

ALO
AHS

AHO

DD
CC

20
19
18
17
16
15
14
13
12
11

12V

LOAD

-

+

6V

GND

3

HIP4080A

HIP4080A

Absolute Maximum Ratings Thermal Information

Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . .-0.3V to 16V

Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V

Voltage on AHS, BHS. . . . -6.0V (Transient) to 80V (25

Voltage on AHS, BHS. . . .-6.0V (Transient) to 70V (-55

+0.3V

DD

o

C to 125oC)

o

C to 125oC)

Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient)

Voltage on AHB, BHB. . . . . . . . . V

Voltage on ALO, BLO. . . . . . . . . . . . . .V

Voltage on AHO, BHO . . . . . . . .V

AHS, BHS

AHS, BHS

ALS, BLS

-0.3V to V

-0.3V to V

AHS, BHS

-0.3V to VCC +0.3V

AHB, BHB

+V

DD

+0.3V

Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA

Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns

NOTE: All Voltages relative to V

, unless otherwise specified.

SS

Thermal Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . θ

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +85oC/W

DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +75

Maximum Power Dissipation at +85

o

C

o

C/W

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470mW

DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530mW

Storage Temperature Range. . . . . . . . . . . . . . . . . . -65

o

C to +150oC

Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . +125

Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300

(For SOIC - Lead Tips Only)

JA

o

C

o

C

Operating Conditions

Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . +9.5V to +15V

Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V

Voltage on AHB, BHB. . . . . . . . . . V

Input Current, HDEL and LDEL . . . . . . . . . . . . . . . .-500µA to -50µA

Operating Ambient Temperature Range . . . . . . . . . -40

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditio ns above those indicated in the operat ional sections of this specification is not implied.

AHS, BHS

+5V to V

AHS, BHS

o

C to +85oC

+15V

Electrical Specifications V

PARAMETERS SYMBOL TEST CONDITIONS

= VCC = V

DD

= +25oC, Unless Otherwise Specified

T

A

AHB

= V

BHB

= 12V, VSS = V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

T

= +25oC

J

HDEL

= R

= 100K, and

LDEL

= - 40oC

T

J

TO +125

o

C

UNITSMIN TYP MAX MIN MAX

SUPPLY CURRENTS AND CHARGE PUMPS

Quiescent Current I

V

DD

Operating Current I

V

DD

Quiescent Current I

V

CC

Operating Current I

V

CC

AHB, BHB Quiescent Current ­Qpump Output Current

AHB, BHB Operating Current I

I

AHB

AHBO

AHS, BHS, AHB, BHB Leakage Current I

AHB-AHS, BHB-BHS Qpump
Output Voltage

V

AHB

V

BHB

DD

DDO

CC

CCO

, I

, I

HLK

- V

- V

IN- = 2.5V, Other Inputs = 0V 8 11 14 7 14 mA
Outputs switching f = 500kHz, No Load 9 12 15 8 15 mA
IN- = 2.5V, Other Inputs = 0V,

I

= I

BLO

= 0

ALO

- 25 80 - 100 µA

f = 500kHz, No Load 1 1.25 2.0 0.8 3 mA
IN- = 2.5V, Other Inpu ts = 0V, I

BHB

I

= 0, VDD = V

BHO

f = 500kHz, No Load 0.62 1.2 1.5 0.5 1.9 mA

BHBO

V

= V

BHS

V

= V

AHB

I

AHB

= I

AHB

AHS
BHS

CC =VAHB

= 80V,

AHS

= 93V

BHB

= 0, No Load 11.5 12.6 14.0 10.5 14.5 V

= V

AHO

BHB

=

= 10V

-50 -25 -11 -60 -10 µA

- 0.02 1.0 - 10 µA

INPUT COMPARATOR PINS: IN+, IN-, OUT

Offset Voltage V

OS

Input Bias Current I
Input Offset Current I

OS

Input Common Mode Voltage Range CMVR 1 - V

Over Common Mode Voltage Range -10 0 +10 -15 +15 mV

IB

00.52 0 4 µA

-1 0 +1-2+2µA
1V

DD

-1.5

DD

-1.5
Voltage Gain AVOL 10 25 - 10 - V/mV
OUT High Level Output Voltage V

OUT Low Level Output Voltage V
Low Level Output Current I
High Level Output Current I

OH

OL

OL

OH

IN+ > IN-, IOH = -250µAV

-0.4
IN+ < IN-, IOL = +250µA - -0.4-0.5V
V

= 6V 6.5 14 19 6 20 mA

OUT

V

= 6V -17 -10 -3 -20 -2.5 mA

OUT

--V

DD

DD

- 0.5

-V

V

4

HIP4080A

Electrical Specifications V

PARAMETERS SYMBOL TEST CONDITIONS

= VCC = V

DD

= +25oC, Unless Otherwise Specified (Continued)

T

A

AHB

= V

BHB

= 12V, VSS = V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

T

= +25oC

J

HDEL

= R

= 100K, and

LDEL

= - 40oC

T

J

TO +125

o

C

UNITSMIN TYP MAX MIN MAX

INPUT PINS: DIS

Low Level Input Voltage V
High Level Input Voltage V

Full Operating Conditions - - 1.0 - 0.8 V

IL

Full Operating Conditions 2.5 - - 2.7 - V

IH

Input Voltage Hysteresis -35- - -mV
Low Level Input Current I
High Level Input Current I

IL

IH

VIN = 0V, Full Operating Conditions -130 -100 -75 -135 -65 µA
VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 µA

INPUT PINS: HEN
Low Level Input Voltage V
High Level Input Voltage V

Full Operating Conditions - - 1.0 - 0.8 V

IL

Full Operating Conditions 2.5 - - 2.7 - V

IH

Input Voltage Hysteresis -35- - -mV
Low Level Input Current I
High Level Input Current I

IL

IH

VIN = 0V, Full Operating Conditions -260 -200 -150 -270 -130 µA
VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 µA

TURN-ON DELAY PINS: LDEL AND HDEL

LDEL, HDEL Voltage V

HDEL,

VI

HDEL

= I

= -100µA 4.9 5.1 5.3 4.8 5.4 V

LDEL

GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO

I

Low Level Output Voltage V
High Level Output Voltage V

CC

Peak Pullup Current I
Peak Pulldown Current I

OL

- VOHI
+V

O

-V

O

= 100mA 0.7 0.85 1.0 0.5 1.1 V

OUT

= -100mA 0.8 0.95 1.1 0.5 1.2 V

OUT

= 0V 1.7 2.6 3.8 1.4 4.1 A

OUT

= 12V 1.7 2.4 3.3 1.3 3.6 A

OUT

Under Voltage, Rising Threshold UV+ 8.1 8.8 9.4 8.0 9.5 V
Under Voltage, Falling Threshold UV- 7.6 8.3 8.9 7.5 9.0 V
Under Voltage, Hysteresis HYS 0.25 0.4 0.65 0.2 0.7 V

Switching Specifications V

= VCC = V

DD

= 1000pF, and TA = +25oC, Unless Otherwise Specified

C

L

AHB

= V

BHB

= 12V, VSS = V

PARAMETERS SYMBOL TEST CONDITIONS

Lower Turn-off Propagation Delay (IN+/IN- to ALO/BLO) T
Upper Turn-off Propagation Delay (IN+/IN- to AHO/ BHO) T
Lower Turn-on Propagation Delay (IN+/IN- to ALO/BLO) T
Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO) T
Rise Time T
Fall Time T
Turn-on Input Pulse Width T
Turn-off Input Pulse Width T
Disable Turn-off Propagation Delay

PWIN-OFF

T

(DIS - Lower Outputs)

5

LPHL

HPHL

LPLH

HPLH

R

F

PWIN-ON

DISLOW

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

T

= +25oC

T

J

TO +125

- 40 70 - 90 ns

-5080-110ns

- 40 70 - 90 ns

- 70 110 - 140 ns

- 10 25 - 35 ns

- 10 25 - 35 ns
50 - - 50 - ns
40 - - 40 - ns

- 45 75 - 95 ns

= 10K,

= - 40oC

J

o

C

UNITSMIN TYP MAX MIN MAX

HIP4080A

Switching Specifications V

= VCC = V

DD

= 1000pF, and TA = +25oC, Unless Otherwise Specified (Continued)

C

L

AHB

= V

BHB

= 12V, VSS = V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

T

= +25oC

T

J

TO +125

PARAMETERS SYMBOL TEST CONDITIONS

Disable Turn-off Propagation Delay
(DIS - Upper Outputs)

Disable to Lower Turn-on Propagation Delay

T

DISHIGH

T

DLPLH

-5585-105ns

- 45 70 - 90 ns

(DIS - ALO and BLO)
Refresh Pulse Width (ALO and BLO) T
Disable to Upper Enable (DIS - AHO and BHO) T
HEN-AHO, BHO Turn-off, Propagation Delay T
HEN-AHO, BHO Turn-on, Propagation Delay T

REF-PW

UEN

HEN-PHLRHDEL

HEN-PLHRHDEL

= R
= R

= 10K - 40 70 - 90 ns

LDEL

= 10K - 60 90 - 110 ns

LDEL

240 380 500 200 600 ns

- 480 630 - 750 ns

TRUTH TABLE

INPUT OUTPUT

IN+ > IN- HEN U/V DIS ALO AHO BLO BHO

X XX10000
0 0001000
1 1000110
0 1001001
1 0000010
X X1X0000

= 10K,

= - 40oC

J

o

C

UNITSMIN TYP MAX MIN MAX

6

HIP4080A

Pin Descriptions

PIN

NUMBER SYMBOL DESCRIPTION

1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap

2 HEN High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers

3 DIS DISable input. Logic level input that when taken high sets all four outputs low . DIS high o verrides all other inputs. When

4V
5 OUT OUTput of the input control comparator. This output can be used for feedback and hysteresis.
6 IN+ Noninverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level outputs

7 IN- Inverting input of control comparator. See IN+ (Pin 6) description.
8 HDEL High-side turn-on DELay. Connect resistor from this pin to V

9 LDEL Low-side turn-on DELay. Connect resistor from this pin to V

10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap

11 AHO A High-side Output. Connect to gate of A High-side power MOSFET.
12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negativ e side of bootstrap

13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET.
14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET.
15 V
16 V
17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET.

18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET.

19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negativ e side of bootstrap

20 BHO B High-side Output. Connect to gate of B High-side power MOSFET.

diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to
maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

(Pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can
be driven by signal levels of 0V to 15V (no greater than V

DD

).

DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no
greater than V

Chip negative supply, generally will be ground.

SS

DD

).

and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level outputs and BLO
and AHO are low level outputs. DIS (Pin 3) high lev el will o verride IN+/IN- control for all outputs. HEN (Pin 2) low le v el
will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode, dead time in a half bridge leg
is controlled by HDEL and LDEL (Pins 8 and 9).

to set timing current that defines the turn-on delay of

SS

both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no
shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V.

to set timing current that defines the turn-on delay of

both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no

SS

shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.

diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to
maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

capacitor to this pin.

Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes.

CC

Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4).

DD

capacitor to this pin.

7

Timing Diagrams

U/V = DIS

HEN

IN+ > IN-

ALO

AHO

BLO

BHO

0
1

T

T

HPHL

LPHL

HIP4080A

T

DT

T

LPLH

T

HPLH

T

DT

FIGURE 1. BISTATE MODE

T

R

(10% - 90%)

T

F

(90% - 10%)

U/V = DIS

HEN

IN+ > IN-

ALO

AHO

BLO

BHO

U/V or DIS

HEN

IN+ > IN-

ALO

T

HEN-PHL

T

HEN-PLH

0

FIGURE 2. HIGH SIDE CHOP MODE

T

DLPLH

T

REF-PW

T

DIS

AHO

BLO

BHO

T

UEN

FIGURE 3. DISABLE FUNCTION

8

HIP4080A

Typical Performance Curves V

14.0

12.0

10.0

8.0

6.0

SUPPLY CURRENT (mA)

DD

I

4.0

2.0
8 10 12 14

VDD SUPPLY VOLTAGE (V)

FIGURE 4. QUIESCENT I

SUPPLY VOLTAGE

20.0

15.0

10.0

SUPPLY CURRENT vs VDD

DD

= VCC = V

DD

100K, and T

= V

AHB

= +25oC, Unless Otherwise Specified

A

= 12V, VSS = V

BHB

12.5

12.0

11.5

11.0

SUPPLY CURRENT (mA)

DD

I

10.5

13

10

FIGURE 5. I

5.0

4.0

3.0

2.0

= V

ALS

200 400 600 800 1000

NO-LOAD IDD SUPPLY CURRENT vs FRE-

DDO

QUENCY (kHz)

= V

= V

BLS

AHS

SWITCHING FREQUENCY (kHz)

+125

+75oC
+25oC

0

-40

= 0V, R

BHS

o

C

o

C

o

C

HDEL

= R

LDEL

=

5.0

FLOATING SUPPLY BIAS CURRENT (mA)

0.0
0 100 200 300 400 500 600 700 800 900 1000

SWITCHING FREQUENCY (kHz)

FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs

FREQUENCY (LOAD = 1000pF)

2.5

2

1.5

1

0.5

FLOATING SUPPLY BIAS CURRENT (mA)

0400

FIGURE 8. I

200

SWITCHING FREQUENCY (kHz)

, I

AHB

NO-LOAD FLOATING SUPPLY BIAS

BHB

600 800 1000

CURRENT vs FREQUENCY

SUPPLY CURRENT (mA)

CC

1.0

I

0.0
0 100 200 300 400 500 600 700 800 900 1000

SWITCHING FREQUENCY (kHz)

FIGURE 7. I

1.0

0.5

COMPARATOR INPUT CURRENT (µA)

-40 -20 0 20 40 60 80 100 120

FIGURE 9. COMPARATOR INPUT CURRENT I

, NO-LOAD ICC SUPPLY CURRENT vs FRE-

CCO

QUENCY (kHz) TEMPERATURE

JUNCTION TEMPERATURE (oC)

TURE AT V

CM

= 5 V

L

vs TEMPERA-

9

HIP4080A

Typical Performance Curves V

-90

-100

-110

LOW LEVEL INPUT CURRENT (µA)

-120

-50 -25 0 25 50 75 100 125
JUNCTION TEMPERATURE (oC)

= VCC = V

DD

100K, and T

AHB

= +25oC, Unless Otherwise Specified (Continued)

A

FIGURE 10. DIS LOW LEV EL INPUT CURRENT IIL vs TEMPERA-

TURE

15.0

14.0

= V

= 12V, VSS = V

BHB

-180

-190

-200

-210

-220

LOW LEVEL INPUT CURRENT (µA)

-230

-40 -20 0 20 40 60 80 100 120

= V

= V

ALS

BLS

JUNCTION TEMPERATURE (oC)

AHS

= V

FIGURE 11. HEN LOW LEVEL INPUT CURRENT I

ATURE

80

70

BHS

= 0V, R

= R

HDEL

IL

LDEL

vs TEMPER-

=

13.0

12.0

11.0

10.0

-40 -20 0 20 40 60 80 100 120

NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V)

JUNCTION TEMPERATURE (oC)

FIGURE 12. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP

VOLTAGE vs TEMPERATURE

525

500

475

450

PROPAGATION DELAY (ns)

60

50

40

PROPAGATION DELAY (ns)

30

-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (oC)

FIGURE 13. UPPER DISABLE TURN-OFF PROPAGATION

80

DELAY T

70

60

50

PROPAGATION DELAY (ns)

40

vs TEMPERATURE

DISHIGH

425

-50 -25 0 25 50 75 100 125 150
JUNCTION TEMPERATURE (oC)

FIGURE 14. DISABLE TO UPPER ENABLE T

UEN

DELAY vs TEMPERATURE

10

PROP A GA TION

30

-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (oC)

FIGURE 15. LOWER DISABLE TURN-OFF PROPA GATION

DELAY T

vs TEMPERATURE

DISLOW

HIP4080A

Typical Performance Curves V

DD

10K, and T

450

425

400

375

REFRESH PULSE WIDTH (ns)

350

-50 -25 0 25 50 75 100 125 150
JUNCTION TEMPERATURE (oC)

FIGURE 16. T

REFRESH PULSE WIDTH vs TEMPERA-

REF-PW

TURE

90.0

80.0

= VCC = V

= V

AHB

= +25oC, Unless Otherwise Specified

A

= 12V, VSS = V

BHB

80

70

60

50

40

PROPAGATION DELAY (ns)

30

20

-40 -20 0 20 40 60 80 100 120

FIGURE 17. DISABLE TO LOWER ENABLE TDLPLH PROPAGA-

90.0

80.0

= V

= V

= V

ALS

BLS

AHS

JUNCTION TEMPERATURE (oC)

BHS

= 0V, R

TION DELAY vs TEMPERATURE

HDEL

= R

LDEL

=

70.0

60.0

50.0

PROPAGATION DELAY (ns)

40.0

-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (oC)

FIGURE 18. UPPER TURN-OFF PROPAGATION DELAY T

vs TEMPERATURE

90.0

80.0

70.0

60.0

50.0

PROPAGATION DELAY (ns)

40.0

HPHL

70.0

60.0

50.0

PROPAGATION DELAY (ns)

40.0

-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (oC)

FIGURE 19. UPPER TURN-ON PROPAGATION DELAY THPLH

vs TEMPERATURE

90.0

80.0

70.0

60.0

50.0

PROPAGATION DELAY (ns)

40.0

-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (oC)

FIGURE 20. LOWER TURN-OFF PROPAGATION DELAY T

vs TEMPERATURE

11

LPHL

-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (oC)

FIGURE 21. LOWER TURN-ON PROPAGATION DELAY T

TEMPERATURE

LPLH

vs

HIP4080A

Typical Performance Curves V

13.5

12.5

11.5

10.5

GATE DRIVE FALL TIME (ns)

9.5

8.5

-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (oC)

FIGURE 22. GATE DRIVE FALL TIME T

6.0

5.5

5.0

4.5

HDEL, LDEL INPUT VOLTAGE (V)

4.0

-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (oC)

vs TEMPERATURE

F

= VCC = V

DD

100K, and T

= V

AHB

= +25oC, Unless Otherwise Specified

A

= 12V, VSS = V

BHB

13.5

12.5

11.5

10.5

TURN-ON RISE TIME (ns)

9.5

8.5

-40 -20 0 20 40 60 80 100 120

ALS

= V

FIGURE 23. GATE DRIVE RISE TIME T

1500

1250

1000

(mV)

OH

750

- V

CC

V

500

250

0

10 12 14

-40
0

+25oC
+75oC

+125

= V

= V

BLS

AHS

JUNCTION TEMPERATURE (oC)

o

C

o

C

o

C

BIAS SUPPLY VOLTAGE (V)

= 0V, R

BHS

vs TEMPERATURE

R

HDEL

= R

LDEL

=

, V

FIGURE 24. V

1500

1250

1000

750

(mV)

OL

V

500

250

+125

0

10

-40
0

+25oC
+75oC

LDEL

o

C

o

C

o

C

VOLTAGE vs TEMPERATURE

HDEL

12 14

BIAS SUPPLY VOLTAGE (V)

FIGURE 26. LOW LEVEL OUTPUT VOLTAGE V

SUPPLY AND TEMPERATURE AT 100µA

12

vs BIAS

OL

FIGURE 25. HIGH LEVEL OUTPUT VOLTAGE, V

SUPPLY AND TEMPERATURE AT 100µA

3.5

3.0

2.5

2.0

1.5

1.0

GATE DRIVE SINK CURRENT (A)

0.5

0.0
6 7 8 9 10 11 12 13 14 15 16

VCC, VDD, V

FIGURE 27. PEAK PULLDOWN CURRENT I

AHG

, V

BHB

(V)

O-

VOLTAGE

- VOH vs BIAS

CC

BIAS SUPPLY

HIP4080A

Typical Performance Curves V

3.5

3.0

2.5

2.0

1.5

1.0

GATE DRIVE SINK CURRENT (A)

0.5

0.0
6 7 8 9 10 11 12 13 14 15 16

VCC, VDD, V

ABH

, V

BHB

= VCC = V

DD

100K, and T

(V)

AHB

= +25oC, Unless Otherwise Specified (Continued)

A

FIGURE 28. PEAK PULLUP CURRENT IO+ vs SUPPL Y V OLTA GE

1000

500

200

= V

= 12V, VSS = V

BHB

500

200
100

50

20
10

5

2
1

0.5

LOW VOLTAGE BIAS CURRENT (mA)

0.2

0.1
1 10 100 10002 5 20 50 500200

= V

ALS

10,000

3,000
1,000

100

= V

BLS

AHS

SWITCHING FREQUENCY (kHz)

FIGURE 29. LOW VOLTAGE BIAS CURRENT I

QUIESCENT COMPONENT) vs FREQUENCY AND
GATE LOAD CAPACITANCE

9

(V)

DD

8.8

UV+

= V

BHS

= 0V, R

DD

HDEL

AND I

= R

CC

=

LDEL

(LESS

100

50

20

LEVEL-SHIFT CURRENT (µA)

10

10 100 100020 50 200 500

SWITCHING FREQUENCY (kHz)

FIGURE 30. HIGH VOL TAGE LEVEL-SHIFT CURRENT vs

FREQUENCY AND BUS VOLTAGE

150

120

90

60

DEAD-TIME (ns)

30

8.6

8.4

BIAS SUPPLY VOLTAGE, V

8.2
50 25 0 25 50 75 100 125 150

UV-

TEMPERATURE (

o

C)

FIGURE 31. UNDERVOLTAGE LOCKOUT vs TEMPERATURE

13

0

10 50 100 150 200 250

HDEL/LDEL RESISTANCE (kΩ)

FIGURE 32. MINIMUM DEAD-TIME vs DEL RESISTANCE

14

IN2 IN1

CONTROL LOGIC

SECTION

1

U2

CD4069UB

13

U2

CD4069UB

5

U2

CD4069UB

11

U2

CD4069UB

2

12

6

10

R29

JMPR1

JMPR2

JMPR3

JMPR4

OUT/BLI

IN+/ALI

HEN/BHI

IN-/AHI

+12V

2
CW CW

JMPR5

R33

POWER SECTION

2

+

R34

3

2

1

DRIVER SECTION

C6

HIP4080A/81A

1
2
3
4
5
6
7
8
9

10 11

3

1

U1

SS

OUT/BLI
IN+/ALI

CR1

C3

CR2

C4

20

BHOBHB

19

BHSHEN/BHI

18

BLODIS

17

BLSV
V

DD

V

CC

ALSIN-/AHI
ALOHDEL
AHSLDEL
AHOAHB

+12V

16
15
14
13
12

R21

R22

R23

R24

CX CY

Q1

1

3

1

L1

2

Q2

1

3

R30 R31

C1

1

Q4

Q3

C8

2

3

L2

2

3

C2

B+

AO

BO

HIP4080A

FIGURE 33. HIP4080A EVALUATION PC BOARD SCHEMATIC

C5

ALS

BLS

NOTES:

1. DEVICE CD4069UB PIN 7 = COM. PIN 14 = +12V.

2. COMPONENTS L1, L2, C1, C2, CX, CY, R30, R31, ARE NOT
SUPPLIED. REFER TO APPLICATION NOTE FOR HELP IN
DETERMINING JMPR1 - JMPR4 JUMPER LOCATIONS.

COM

GND

+12V

B+

COM

15

R29

C7
+

R32

IN1

I

O

IN2

ALS

BLS

U2

FIGURE 34. HIP4080A EVALUATION BOARD SILKSCREEN

JMPR5

HDEL

R33

R27

R28

R26

JMPR1
JMPR2
JMPR3
JMPR4

O

LDEL

R34

DIS

C6

+

U1

CR2

CR1

HIP4080/81

C4

C3

BHO

BLO
BLS

ALS
ALO

AHO

C5

R22

R24

R23

R21

CX

R30

C8

Q1

1

Q2

1

Q3

1

L1

Q4

1

L2

C1

AO

C2

BO

HIP4080A

CY

R31

Dual-In-Line Plastic Packages (PDIP)

N

-C-

D1

-C-

E1

-B-

A1

A2

A

L

e

C

S

INDEX

AREA

BASE

PLANE

SEATING

PLANE

12 3 N/2

-A-

D1
B1

B

D

e

0.010 (0.25) C AMB

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or
protrusions. Mold flash or protrusions shall not exceed 0.010
inch (0.25mm).

6. E and are measured with the leads constrained to be

e

A

perpendicular to datum .

7. e

and eC are measured at the lead tips with the leads

B

unconstrained. e

must be zero or greater.

C

8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).

HIP4080A

E

C

L

e

A

C

e

B

E20.3 (JEDEC MS-001-AD ISSUE D)

20 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 ­B1 0.045 0.070 1.55 1.77 8

C 0.008 0.014 0.204 0.355 -

D 0.980 1.060 24.89 26.9 5
D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

0.300 BSC 7.62 BSC 6

- 0.430 - 10.92 7

L 0.115 0.150 2.93 3.81 4

N20 209

NOTESMIN MAX MIN MAX

Rev. 0 12/93

16

Small Outline Plastic Packages (SOIC)

N

INDEX
AREA

123

-A­D

e

B

0.25(0.010) C AMB

E

-B-

SEATING PLANE

A

-C-

M

S

0.25(0.010) B

H

α

µ

A1

0.10(0.004)

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.

M

L

h x 45

M

o

HIP4080A

HIP4080A

C

M20.3 (JEDEC MS-013-AC ISSUE C)

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.4961 0.5118 12.60 13.00 3
E 0.2914 0.2992 7.40 7.60 4

e 0.050 BSC 1.27 BSC -

H 0.394 0.419 10.00 10.65 -

h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6

N20 207

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMIN MAX MIN MAX

-

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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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17