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HIP4080A
DATA SHEET
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Datasheet
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intersil HIP4080A DATA SHEET

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Data Sheet July 2004
80V/2.5A Peak, High Frequency Full Bridge FET Driver
The HIP4080A is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 20 lead plastic SOIC and DIP packages. The HIP4080A includes an input comparator, used to facilitate the “hysteresis” and PWM modes of operation. Its HEN (high enable) lead can force current to freewheel in the bottom two external power MOSFETs, maintaining the upper power MOSFETs off. Since it can switch at frequencies up to 1MHz, the HIP4080A is well suited for driving Voice Coil Motors, switching power amplifiers and power supplies.
HIP4080A can also drive medium voltage brush motors, and two HIP4080As can be used to drive high performance stepper motors, since the short minimum “on-time” can provide fine micro-stepping capability.
Short propagation delays of approximately 55ns maximize control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in precise control of the driven load.
The similar HIP4081A IC allows independent control of all 4 FETs in a Full Bridge configuration.
The Application Note for the HIP4080A is AN9404.
Ordering Information
PART
NUMBER
HIP4080AIPZ (Note 1)
HIP4080AIP -40 to +85 20 Ld PDIP E20.3
HIP4080AIB -40 to +85 20 Ld SOIC M20.3
HIP4080AIBZ (Note 1)
NOTES:
1. Intersil Pb-Free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-Free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
2. Add “T” suffix for Tape and Reel packing option. HIP4080AIP not available in Tape and Reel.
TEMPERATURE
RANGE (°C) PACKAGE
-40 to +85 20 Ld PDIP (Pb-Free)
-40 to +85 20 Ld SOIC (Pb-Free)
PKG.
DWG. #
E20.3
M20.3
FN3658.7
Features
• Drives N-Channel FET Full Bridge Including High Side Chop Capability
• Bootstrap Supply Max Voltage to 95VDC
• Drives 1000pF Load at 1MHz in Free Air at +50°C with Rise and Fall Times of Typically 10ns
• User-Programmable Dead Time
• Charge-Pump and Bootstrap Maintain Upper Bias Supplies
• DIS (Disable) Pin Pulls Gates Low
• Input Logic Thresholds Compatible with 5V to 15V Logic Levels
• Very Low Power Consumption
• Undervoltage Protection
• Pb-Free Available as an Option
Applications
• Medium/Large Voice Coil Motors
• Full Bridge Power Supplies
• Switching Power Amplifiers
• High Performance Motor Controls
• Noise Cancellation Systems
• Battery Powered Vehicles
• Peripherals
• U.P.S.
Pinout
HIP4080A
(PDIP, SOIC)
TOP VIEW
BHB
HEN
DIS
V
OUT
IN+
IN-
HDEL
LDEL
AHB
SS
1
2
3
4
5
6
7
8
9
10
20
BHO
BHS
19
BLO
18
BLS
17
V
16
DD
V
15
CC
ALS
14
ALO
13
AHS
12
AHO
11
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
Copyright Harris Corporation 1995, Copyright Intersil Americas Inc. 2003, 2004. All Rights Reserved
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Application Block Diagram
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HEN
DIS
HIP4080A
12V
BHO
BHS
BLO
HIP4080A
80V
LOAD
IN+
IN-
ALO
AHS
AHO
GND
Functional Block Diagram (1/2 HIP4080A)
V
DD
HEN
DIS
OUT
IN+
IN
UNDER-
VOLTAGE
16
2
3
5
6
+
_
-
7
CHARGE
PUMP
LEVEL SHIFT
AND LATCH
TURN-ON
DELAY
TURN-ON
DELAY
DRIVER
DRIVER
GND
10
11
12
15
13
14
AHB
AHO
AHS
V
CC
ALO
ALS
HIGH VOLTAGE BUS ≤ 80VDC
C
BS
D
BS
TO VDD (PIN 16)
+12VDC
BIAS
C
BF
SUPPLY
8
HDEL
9
LDEL
4
V
SS
2
HIP4080A
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Typical Application (Hysteresis Mode Switching)
80V
6V
IN
12V
DIS
GND
1
BHB
2
HEN
3
DIS
4
V
SS
OUT
5
IN+
6
IN-
7
HDEL
8
LDEL
9
AHB
10
HIP4080A/HIP4080
BHO
BHS
BLO
BLS
V
DD
V
CC
ALS
ALO
AHS
AHO
20
19
18
17
16
15
14
13
12
11
12V
LOAD
-
+
6V
GND
3
HIP4080A
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Absolute Maximum Ratings Thermal Information
Supply Voltage, VDD and VCC. . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
Voltage on AHS, BHS . . . -6.0V (Transient) to 80V (25°C to 125°C)
DD
+0.3V
Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55°C to 125°C)
Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient)
Voltage on AHB, BHB . . . . . . V
AHS, BHS
Voltage on ALO, BLO. . . . . . . . . . . . .V
Voltage on AHO, BHO . . . . . . V
Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA
AHS, BHS
-0.3V to V
ALS, BLS
-0.3V to V
AHS, BHS
-0.3V to VCC +0.3V
AHB, BHB
+V
DD
+0.3V
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
All Voltages relative to V
, unless otherwise specified.
SS
Operating Conditions
Supply Voltage, VDD and VCC. . . . . . . . . . . . . . . . . . +9.5V to +15V
Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V
Voltage on AHB, BHB . . . . . . . .V
Input Current, HDEL and LDEL . . . . . . . . . . . . . . . .-500µA to -50µA
AHS, BHS
+5V to V
AHS, BHS
Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3. θ
JA
+15V
Thermal Resistance (Typical, Note 3) θ
JA
(°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Maximum Power Dissipation at +85°C
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470mW
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530mW
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Max. Junction Temperature. . . . . . . . . . . . . . . . . . +125°C
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C
(For SOIC - Lead Tips Only)
Electrical Specifications V
= VCC = V
DD
T
= +25°C, Unless Otherwise Specified
A
PARAMETERS SYMBOL TEST CONDITIONS
SUPPLY CURRENTS AND CHARGE PUMPS
V
Quiescent Current I
DD
V
Operating Current I
DD
Quiescent Current I
V
CC
Operating Current I
V
CC
AHB, BHB Quiescent Current ­Qpump Output Current
I
AHB
AHB, BHB Operating Current I
AHS, BHS, AHB, BHB Leakage Current I
AHB-AHS, BHB-BHS Qpump Output Voltage
INPUT COMPARATOR PINS: IN+, IN-, OUT
DD
DDO
CC
CCO
AHBO
I
BHBO
HLK
V
AHB
V
AHS
V
BHB
V
BHS
, I
= V
AHB
= 12V, VSS = V
BHB
ALS
= V
BLS
= V
AHS
= V
= 0V, R
BHS
T
= +25°C
J
HDEL
= R
LDEL
= - 40°C
T
J
TO +125°C
IN- = 2.5V, Other Inputs = 0V 8 11 14 7 14 mA
Outputs switching f = 500kHz, No Load 9 12 15 8 15 mA
IN- = 2.5V, Other Inputs = 0V,
= I
BLO
= 0
I
ALO
- 25 80 - 100 µA
f = 500kHz, No Load 1 1.25 2.0 0.8 3 mA
IN- = 2.5V, Other Inputs = 0V,
BHB
I
AHO=IBHO
V
DD
,
f = 500kHz, No Load 0.62 1.2 1.5 0.5 1.9 mA
V
BHS
V
AHB
-
I
AHB
= 0,
= V
= V
= V
= I
CC =VAHB
AHS BHB
AHB
= V
= 10V
BHB
= 80V, = 93V
= 0, No Load 11.5 12.6 14.0 10.5 14.5 V
-50 -25 -11 -60 -10 µA
- 0.02 1.0 - 10 µA
-
= 100K, and
UNITSMIN TYP MAX MIN MAX
Offset Voltage V
Input Bias Current I
Input Offset Current I
OS
OS
Over Common Mode Voltage Range -10 0 +10 -15 +15 mV
IB
Input Common Mode Voltage Range CMVR 1 - V
4
00.52 0 4 µA
-1 0 +1-2+2µA
1V
DD
-1.5
DD
-1.5
V
HIP4080A
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Electrical Specifications V
PARAMETERS SYMBOL TEST CONDITIONS
Voltage Gain AVOL 10 25 - 10 - V/mV
OUT High Level Output Voltage V
OUT Low Level Output Voltage V
Low Level Output Current I
High Level Output Current I
INPUT PINS: DIS
Low Level Input Voltage V
High Level Input Voltage V
Input Voltage Hysteresis -35- - -mV
Low Level Input Current I
High Level Input Current I
INPUT PINS: HEN
Low Level Input Voltage V
High Level Input Voltage V
Input Voltage Hysteresis -35- - -mV
Low Level Input Current I
High Level Input Current I
TURN-ON DELAY PINS: LDEL AND HDEL
LDEL, HDEL Voltage V
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO
= VCC = V
DD
= +25°C, Unless Otherwise Specified (Continued)
T
A
HDEL,
OH
OL
OL
OH
IL
IH
IL
IH
IL
IH
IL
IH
= V
AHB
VI
= 12V, VSS = V
BHB
IN+ > IN-, IOH = -250µAV
IN+ < IN-, IOL = +250µA - -0.4-0.5V
V
= 6V 6.5 14 19 6 20 mA
OUT
V
= 6V -17 -10 -3 -20 -2.5 mA
OUT
Full Operating Conditions - - 1.0 - 0.8 V
Full Operating Conditions 2.5 - - 2.7 - V
VIN = 0V, Full Operating Conditions -130 -100 -75 -135 -65 µA
VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 µA
Full Operating Conditions - - 1.0 - 0.8 V
Full Operating Conditions 2.5 - - 2.7 - V
VIN = 0V, Full Operating Conditions -260 -200 -150 -270 -130 µA
VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 µA
= I
HDEL
= -100µA 4.9 5.1 5.3 4.8 5.4 V
LDEL
ALS
= V
BLS
= V
AHS
= V
DD
-0.4
= 0V, R
BHS
= +25°C
T
J
HDEL
--V
= R
LDEL
= - 40°C
T
J
TO +125°C
DD
- 0.5
= 100K, and
UNITSMIN TYP MAX MIN MAX
-V
Low Level Output Voltage V
High Level Output Voltage V
Peak Pullup Current I
Peak Pulldown Current I
Under Voltage, Rising Threshold UV+ 8.1 8.8 9.4 8.0 9.5 V
Under Voltage, Falling Threshold UV- 7.6 8.3 8.9 7.5 9.0 V
Under Voltage, Hysteresis HYS 0.25 0.4 0.65 0.2 0.7 V
OL
- VOHI
CC
O
O
I
= 100mA 0.7 0.85 1.0 0.5 1.1 V
OUT
= -100mA 0.8 0.95 1.1 0.5 1.2 V
OUT
+V
-V
OUT
OUT
= 0V 1.7 2.6 3.8 1.4 4.1 A
= 12V 1.7 2.4 3.3 1.3 3.6 A
5
HIP4080A
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Switching Specifications V
PARAMETERS SYMBOL TEST CONDITIONS
Lower Turn-off Propagation Delay (IN+/IN- to ALO/BLO) T
Upper Turn-off Propagation Delay (IN+/IN- to AHO/BHO) T
Lower Turn-on Propagation Delay (IN+/IN- to ALO/BLO) T
Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO) T
Rise Time T
Fall Time T
Turn-on Input Pulse Width T
Turn-off Input Pulse Width T
Disable Turn-off Propagation Delay (DIS - Lower Outputs)
Disable Turn-off Propagation Delay (DIS - Upper Outputs)
Disable to Lower Turn-on Propagation Delay (DIS - ALO and BLO)
= VCC = V
DD
= 1000pF, and TA = +25°C, Unless Otherwise Specified
C
L
AHB
= V
BHB
= 12V, VSS = V
PWIN-ON
PWIN-OFF
T
T
T
LPHL
HPHL
LPLH
HPLH
R
F
DISLOW
DISHIGH
DLPLH
ALS
= V
BLS
= V
AHS
= V
= 0V, R
BHS
T
= +25°C
J
- 40 70 - 90 ns
-5080-110ns
- 40 70 - 90 ns
- 70 110 - 140 ns
- 10 25 - 35 ns
- 10 25 - 35 ns
50 - - 50 - ns
40 - - 40 - ns
- 45 75 - 95 ns
-5585-105ns
- 45 70 - 90 ns
HDEL
= R
LDEL
T
= - 40°C
J
TO +125°C
= 10K,
UNITSMIN TYP MAX MIN MAX
Refresh Pulse Width (ALO and BLO) T
Disable to Upper Enable (DIS - AHO and BHO) T
HEN-AHO, BHO Turn-off, Propagation Delay T
HEN-AHO, BHO Turn-on, Propagation Delay T
INPUT OUTPUT
IN+ > IN- HEN U/V DIS ALO AHO BLO BHO
X XX10000
0 0001000
1 1000110
0 1001001
1 0000010
X X1X0000
REF-PW
UEN
HEN-PHLRHDEL
HEN-PLHRHDEL
TRUTH TABLE
= R
= R
= 10K - 40 70 - 90 ns
LDEL
= 10K - 60 90 - 110 ns
LDEL
240 380 500 200 600 ns
- 480 630 - 750 ns
6
HIP4080A
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Pin Descriptions
PIN
NUMBER SYMBOL DESCRIPTION
1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
2 HEN High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO drivers
3 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.
4V
5 OUT OUTput of the input control comparator. This output can be used for feedback and hysteresis.
6 IN+ Noninverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level outputs
7 IN- Inverting input of control comparator. See IN+ (Pin 6) description.
8 HDEL High-side turn-on DELay. Connect resistor from this pin to V
9 LDEL Low-side turn-on DELay. Connect resistor from this pin to V
10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap
11 AHO A High-side Output. Connect to gate of A High-side power MOSFET.
12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of
13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET.
14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET.
15 V
16 V
17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET.
18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET.
19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of
20 BHO B High-side Output. Connect to gate of B High-side power MOSFET.
SS
CC
DD
diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
(Pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs. The pin can be driven by signal levels of 0V to 15V (no greater than V
When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than V
Chip negative supply, generally will be ground.
and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level outputs and BLO and AHO are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs. HEN (Pin 2) low level will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode, dead time in a half bridge leg is controlled by HDEL and LDEL (Pins 8 and 9).
both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V.
both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V.
diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.
bootstrap capacitor to this pin.
Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes.
Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4).
bootstrap capacitor to this pin.
DD
).
).
DD
to set timing current that defines the turn-on delay of
SS
to set timing current that defines the turn-on delay of
SS
7
Timing Diagrams
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U/V = DIS
HEN
IN+ > IN-
ALO
AHO
BLO
BHO
0
1
T
HPHL
T
LPHL
HIP4080A
T
DT
T
LPLH
T
HPLH
T
DT
FIGURE 1. BISTATE MODE
T
R
(10% - 90%)
T
F
(90% - 10%)
U/V = DIS
HEN
IN+ > IN-
ALO
AHO
BLO
BHO
U/V or DIS
HEN
IN+ > IN-
T
HEN-PHL
0
T
HEN-PLH
FIGURE 2. HIGH SIDE CHOP MODE
T
DLPLH
T
REF-PW
T
DIS
ALO
AHO
BLO
BHO
T
UEN
FIGURE 3. DISABLE FUNCTION
8
HIP4080A
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Typical Performance Curves V
14.0
12.0
10.0
8.0
6.0
SUPPLY CURRENT (mA)
DD
I
4.0
2.0 8 10 12 14
VDD SUPPLY VOLTAGE (V)
FIGURE 4. QUIESCENT I
SUPPLY VOLTAGE
20.0
15.0
10.0
SUPPLY CURRENT vs VDD
DD
= VCC = V
DD
100K, and T
= V
AHB
= +25°C, Unless Otherwise Specified
A
= 12V, VSS = V
BHB
ALS
13
12.5
12.0
11.5
11.0
SUPPLY CURRENT (mA)
DD
I
10.5
10
FIGURE 5. I
DDO
FREQUENCY (kHz)
5.0
4.0
3.0
2.0
= V
= V
= V
BLS
AHS
200 400 600 800 1000
SWITCHING FREQUENCY (kHz)
BHS
= 0V, R
HDEL
= R
NO-LOAD IDD SUPPLY CURRENT vs
+125°C
+75°C +25°C
0°C
-40°C
LDEL
=
5.0
FLOATING SUPPLY BIAS CURRENT (mA)
0.0
0 100 200 300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs
FREQUENCY (LOAD = 1000pF)
2.5
2
1.5
1
0.5
FLOATING SUPPLY BIAS CURRENT (mA)
0 400
FIGURE 8. I
200
AHB
CURRENT vs FREQUENCY
SWITCHING FREQUENCY (kHz)
, I
NO-LOAD FLOATING SUPPLY BIAS
BHB
600 800 1000
SUPPLY CURRENT (mA)
CC
1.0
I
0.0
0 100 200 300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
FIGURE 7. I
1.0
0.5
COMPARATOR INPUT CURRENT (µA)
-40 -20 0 20 40 60 80 100 120
, NO-LOAD ICC SUPPLY CURRENT vs
CCO
FREQUENCY (kHz) TEMPERATURE
JUNCTION TEMPERATURE (°C)
FIGURE 9. COMPARATOR INPUT CURRENT IL vs
TE M PERAT U RE AT V
CM
= 5V
9
HIP4080A
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Typical Performance Curves V
= VCC = V
DD
100K, and T
-90
-100
-110
LOW LEVEL INPUT CURRENT (µA)
-120
-50 -25 0 25 50 75 100 125
JUNCTION TEMPERATURE (°C)
FIGURE 10. DIS LOW LEVEL INPUT CURRENT IIL vs
TEMPERATURE
15.0
14.0
= V
AHB
= +25°C, Unless Otherwise Specified (Continued)
A
= 12V, VSS = V
BHB
-180
-190
-200
-210
-220
LOW LEVEL INPUT CURRENT (µA)
-230
= V
ALS
-40 -20 0 20 40 60 80 100 120
= V
BLS
AHS
JUNCTION TEMPERATURE (°C)
FIGURE 11. HEN LOW LEVEL INPUT CURRENT IIL vs
TEMPERATURE
80
70
= V
BHS
= 0V, R
HDEL
= R
LDEL
=
13.0
12.0
11.0
10.0
-40 -20 0 20 40 60 80 100 120
NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
FIGURE 12. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP
VOLTAGE vs TEMPERATURE
525
500
475
450
PROPAGATION DELAY (ns)
60
50
40
PROPAGATION DELAY (ns)
30
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 13. UPPER DISABLE TURN-OFF PROPAGATION
DELAY T
80
70
60
50
PROPAGATION DELAY (ns)
40
vs TEMPERATURE
DISHIGH
425
-50 -25 0 25 50 75 100 125 150
JUNCTION TEMPERATURE (°C)
FIGURE 14. DISABLE TO UPPER ENABLE T
PROPAGATION DELAY vs TEMPERATURE
UEN
30
-40 -20 0 20 40 60 80 100 120
FIGURE 15. LOWER DISABLE TURN-OFF PROPAGATION
10
JUNCTION TEMPERATURE (°C)
DELAY T
vs TEMPERATURE
DISLOW
HIP4080A
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Typical Performance Curves V
10K, and T
450
425
400
375
REFRESH PULSE WIDTH (ns)
350
-50 -25 0 25 50 75 100 125 150
JUNCTION TEMPERATURE (°C)
FIGURE 16. T
TEMPERATURE
90.0
80.0
REFRESH PULSE WIDTH vs
REF-PW
= VCC = V
DD
= V
AHB
= +25°C, Unless Otherwise Specified
A
= 12V, VSS = V
BHB
ALS
80
70
60
50
40
PROPAGATION DELAY (ns)
30
20
-40 -20 0 20 40 60 80 100 120
FIGURE 17. DISABLE TO LOWER ENABLE TDLPLH
90.0
80.0
= V
= V
= V
BLS
AHS
JUNCTION TEMPERATURE (°C)
BHS
= 0V, R
HDEL
= R
PROPAGATION DELAY vs TEMPERATURE
LDEL
=
70.0
60.0
50.0
PROPAGATION DELAY (ns)
40.0
-40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C)
FIGURE 18. UPPER TURN-OFF PROPAGATION DELAY T
vs TEMPERATURE
90.0
80.0
70.0
60.0
50.0
PROPAGATION DELAY (ns)
HPHL
70.0
60.0
50.0
PROPAGATION DELAY (ns)
40.0
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 19. UPPER TURN-ON PROPAGATION DELAY THPLH
vs TEMPERATURE
90.0
80.0
70.0
60.0
50.0
PROPAGATION DELAY (ns)
40.0
-40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (°C)
FIGURE 20. LOWER TURN-OFF PROPAGATION DELAY T
vs TEMPERATURE
LPHL
40.0
-40 -20 0 20 40 60 80 100 120
FIGURE 21. LOWER TURN-ON PROPAGATION DELAY T
11
JUNCTION TEMPERATURE (°C)
vs TEMPERATURE
LPLH
13.5
HIP4080A
www.BDTIC.com/Intersil
Typical Performance Curves V
12.5
11.5
10.5
GATE DRIVE FALL TIME (ns)
9.5
8.5
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
FIGURE 22. GATE DRIVE FALL TIME T
6.0
5.5
5.0
4.5
HDEL, LDEL INPUT VOLTAGE (V)
4.0
-40 -20 0 20 40 60 80 100 120
JUNCTION TEMPERATURE (°C)
, V
FIGURE 24. V
LDEL
VOLTAGE vs TEMPERATURE FIGURE 25. HIGH LEVEL OUTPUT VOLTAGE, VCC - VOH vs
HDEL
vs TEMPERATURE
F
= VCC = V
DD
100K, and T
= V
AHB
= +25°C, Unless Otherwise Specified
A
= 12V, VSS = V
BHB
ALS
13.5
12.5
11.5
10.5
TURN-ON RISE TIME (ns)
9.5
8.5
-40 -20 0 20 40 60 80 100 120
FIGURE 23. GATE DRIVE RISE TIME T
1500
1250
1000
(mV)
OH
750
- V
CC
V
500
250
0
10 12 14
= V
= V
= V
BLS
AHS
BHS
JUNCTION TEMPERATURE (°C)
-40°C
0°C
+25°C
+75°C
+125°C
BIAS SUPPLY VOLTAGE (V)
= 0V, R
vs TEMPERATURE
R
HDEL
= R
LDEL
BIAS SUPPLY AND TEMPERATURE AT 100µA
=
3.5
3.0
2.5
2.0
1.5
1.0
GATE DRIVE SINK CURRENT (A)
0.5
0.0 6 7 8 9 10 11 12 13 14 15 16
FIGURE 27. PEAK PULLDOWN CURRENT IO- BIAS SUPPLY
1500
1250
1000
750
(mV)
OL
V
500
250
-40°C 0°C
+25°C +75°C
+125°C
0
10
12 14
BIAS SUPPLY VOLTAGE (V)
FIGURE 26. LOW LEVEL OUTPUT VOLTAGE V
SUPPLY AND TEMPERATURE AT 100µA
vs BIAS
OL
12
VOLTAGE
VCC, VDD, V
AHG
, V
BHB
(V)
HIP4080A
www.BDTIC.com/Intersil
Typical Performance Curves V
= VCC = V
DD
100K, and T
3.5
3.0
2.5
2.0
1.5
1.0
GATE DRIVE SINK CURRENT (A)
0.5
0.0 6 7 8 9 10 11 12 13 14 15 16
VCC, VDD, V
ABH
, V
BHB
(V)
FIGURE 28. PEAK PULLUP CURRENT IO+ vs SUPPLY
VO LTAGE
1000
500
200
= V
AHB
= +25°C, Unless Otherwise Specified (Continued)
A
= 12V, VSS = V
BHB
500
200
100
50
20
10
5
2
1
0.5
LOW VOLTAGE BIAS CURRENT (mA)
0.2
0.1
= V
ALS
10,000
3,000
1,000
1 10 100 10002 5 20 50 500200
= V
BLS
AHS
100
SWITCHING FREQUENCY (kHz)
FIGURE 29. LOW VOLTAGE BIAS CURRENT IDD AND I
(LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE
9
(V)
DD
8.8
= V
UV+
BHS
= 0V, R
HDEL
= R
LDEL
CC
=
100
50
20
LEVEL-SHIFT CURRENT (µA)
10
10 100 100020 50 200 500
SWITCHING FREQUENCY (kHz)
FIGURE 30. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs
FREQUENCY AND BUS VOLTAGE
150
120
90
60
DEAD-TIME (ns)
30
8.6
UV-
8.4
BIAS SUPPLY VOLTAGE, V
8.2 50 25 0 25 50 75 100 125 150
TEMPERATURE (°C)
FIGURE 31. UNDERVOLTAGE LOCKOUT vs TEMPERATURE
0
10 50 100 150 200 250
HDEL/LDEL RESISTANCE (kΩ)
FIGURE 32. MINIMUM DEAD-TIME vs DEL RESISTANCE
13
14
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IN2 IN1
CONTROL LOGIC
SECTION
1
U2
CD4069UB
13
U2
CD4069UB
5
U2
CD4069UB
11
U2
CD4069UB
2
12
6
10
R29
JMPR1
JMPR2
JMPR3
JMPR4
OUT/BLI
IN+/ALI
HEN/BHI
IN-/AHI
+12V
R33
2
CW CW
JMPR5
3
1
R34
2
+
DRIVER SECTION
C6
HIP4080A/81A
1
2
3
4
SS
5
OUT/BLI
6
IN+/ALI
7
8
9
10 11
3
1
U1
CR1
C3
POWER SECTION
B+
2
CR2
C4
20
BHOBHB
19
BHSHEN/BHI
18
BLODIS
17
BLSV
V
DD
V
CC
ALSIN-/AHI
ALOHDEL
AHSLDEL
AHOAHB
+12V
16
15
14
13
12
R21
R22
R23
R24
CX CY
Q1
1
3
1
L1
2
Q2
1
3
R30 R31
C1
1
Q4
Q3
C8
2
3
AO
L2
2
3
BO
C2
HIP4080A
FIGURE 33. HIP4080A EVALUATION PC BOARD SCHEMATIC
C5
ALS
NOTES:
1. DEVICE CD4069UB PIN 7 = COM. PIN 14 = +12V.
2. COMPONENTS L1, L2, C1, C2, CX, CY, R30, R31, ARE NOT
BLS
SUPPLIED. REFER TO APPLICATION NOTE FOR HELP IN DETERMINING JMPR1 - JMPR4 JUMPER LOCATIONS.
COM
15
www.BDTIC.com/Intersil
GND
+12V
B+
COM
R27
R28
R26
JMPR1 JMPR2 JMPR3 JMPR4
O
LDEL
R34
DIS
C6
CR2
+
U1
CR1
C4
BHO
BLO BLS
HIP4080/81
ALS ALO
AHO
C3
C5
R22
R24
R23
R21
CX
IN1
O
IN2
ALS
BLS
R29
C7
JMPR5
+
R32
U2
I
HDEL
R33
FIGURE 33. HIP4080A EVALUATION BOARD SILKSCREEN
R30
C8
CY
Q3
1
L1
Q4
1
R31
L2
Q1
1
Q2
1
C1
C2
AO
BO
HIP4080A
Dual-In-Line Plastic Packages (PDIP)
www.BDTIC.com/Intersil
HIP4080A
N
D1
-C-
E1
-B-
A1
A2
E
A
L
e
C
C
L
e
A
C
e
B
INDEX
AREA
BASE
PLANE
SEATING
PLANE
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpen­dicular to datum .
7. e strained. e
8. B1 maximum dimensions do not include dambar protrusions. Dam­bar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
12 3 N/2
-A-
D1
B1
B
e
A
and eC are measured at the lead tips with the leads uncon-
B
D
e
0.010 (0.25) C AM BS
-C-
must be zero or greater.
C
E20.3 (JEDEC MS-001-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 ­B1 0.045 0.070 1.55 1.77 8
C 0.008 0.014 0.204 0.355 -
D 0.980 1.060 24.89 26.9 5 D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
e
A
e
B
L 0.115 0.150 2.93 3.81 4
N20 209
0.300 BSC 7.62 BSC 6
- 0.430 - 10.92 7
NOTESMIN MAX MIN MAX
Rev. 0 12/93
16
HIP4080A
www.BDTIC.com/Intersil
Small Outline Plastic Packages (SOIC)
N
INDEX AREA
123
-A­D
e
B
0.25(0.010) C AMB
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In­terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact.
E
-B-
SEATING PLANE
A
-C-
S
M
0.25(0.010) B
H
α
µ
A1
0.10(0.004)
M
L
h x 45
M
o
M20.3 (JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.014 0.019 0.35 0.49 9 C 0.0091 0.0125 0.23 0.32 ­D 0.4961 0.5118 12.60 13.00 3
E 0.2914 0.2992 7.40 7.60 4
e 0.050 BSC 1.27 BSC ­H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
C
L 0.016 0.050 0.40 1.27 6 N20 207
o
α
0
o
8
o
0
o
8
NOTESMIN MAX MIN MAX
-
Rev. 1 1/02
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
17
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