Intersil Corporation HIP4080 Datasheet

December 1996

HIP4080

80V/2.5A Peak, High Frequency

Full Bridge FET Driver

Features

• Drives N-Channel FET Full Bridge Including High Side
Chop Capability

• Bootstrap Supply Max Voltage to 95V

DC

• Drives 1000pF Load at 1MHz in Free Air at 50oC with
Rise and Fall Times of 10ns (Typ)

• User-Programmable Dead Time

• Charge-Pump and Bootstrap Maintain Upper Bias
Supplies

• DIS (Disable) Pin Pulls Gates Low

• Input Logic Thresholds Compatible with 5V to 15V
Logic Levels

• Very Low Power Consumption

Applications

• Medium/Large Voice Coil Motors

• Full Bridge Power Supplies

• Class D Audio Power Amplifiers

• High Performance Motor Controls

• Noise Cancellation Systems

Description

The HIP4080 is a high frequency, medium voltage Full Bridge
N-Channel FET driver IC, av ailable in 20 lead plastic SOIC and
DIP packages. The HIP4080 includes an input comparator,
used to facilitate the “hysteresis” and PWM modes of operation.
Its HEN (high enable) lead can force current to freewheel in the
bottom two external power MOSFETs, maintaining the upper
power MOSFETs off. Since it can switch at frequencies up to
1MHz, the HIP4080 is well suited for driving Voice Coil Motors,
switching amplifiers in class D high-frequency switching audio
amplifiers and power supplies.

HIP4080 can also drive medium voltage brush motors, and
two HIP4080s can be used to drive high performance step­per motors, since the short minimum “on-time” can provide
fine micro-stepping capability.

Short propagation delays of approximately 55ns maximizes
control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion, resulting
in precise control of the driven load.

The similar HIP4081 IC allows independent control of all 4
FETs in an Full Bridge configuration.

See also, Application Note AN9324 for the HIP4080.
Similar part, HIP4080A, includes under voltage circuitry

which doesn’t require the circuitry shown in Figure 30 of this
data sheet.

• Battery Powered Vehicles

• Peripherals

• U.P.S.

Pinout

HIP4080 (PDIP, SOIC)

TOP VIEW

1

BHB
HEN

2

DIS

3

V

4

SS

OUT

5

IN+

6

IN-

7

HDEL

8

LDEL

9

AHB

10

Ordering Information

PART

NUMBER

HIP4080IP -40 to 85 20 Lead PDIP E20.3
HIP4080IB -40 to 85 20 Lead SOIC M20.3

20
19
18
17
16
15
14
13
12
11

TEMP.

RANGE (oC) PACKAGE

BHO
BHS
BLO
BLS
V

DD

V

CC

ALS
ALO
AHS
AHO

PKG.

NO.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

1

File Number 3178.10

Application Block Diagram

12V

HEN
DIS

HIP4080

BHO
BHS

BLO

HIP4080

80V

LOAD

IN+
IN-

Functional Block Diagram

CHARGE

PUMP

16

V

DD

2

HEN

3

DIS

5

OUT

6

IN+

IN

_

+

-

7

ALO
AHS
AHO

GND

(1/2 HIP4080)

LEVEL SHIFT

AND LATCH

TURN-ON

DELAY

TURN-ON

DELAY

DRIVER

DRIVER

10

11

12

15

13

14

GND

AHB

AHO

AHS

V

ALO

ALS

CC

HIGH VOLTAGE BUS ≤ 80V

C

BS

D

BS

TO VDD (PIN 16)

C

BF

DC

+12V

DC

BIAS

SUPPLY

HDEL

LDEL

V

SS

8

9

4

2

HIP4080

Typical Application (Hysteresis Mode Switching)

80V

6V

IN

12V

DIS

GND

1

BHB

2

HEN

3

DIS

4

V

SS

OUT

5

IN+

6

IN-

7

HDEL

8

LDEL

9

AHB

10

BHO

BHS
BLO

BLS
V

DD

V

CC

ALS
ALO
AHS

AHO

20
19
18
17
16
15
14
13
12
11

12V

LOAD

-

+

6V

GND

3

HIP4080

Absolute Maximum Ratings Thermal Information

Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . -0.3V to 16V

Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD +0.3V

Voltage on AHS, BHS. . . . -6.0V (Transient) to 80V (25oC to 125oC)

Voltage on AHS, BHS. . . . -6.0V (Transient) to 70V (-55oC to 125oC

Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient)

Voltage on AHB, BHBV

AHS, BHS

Voltage on ALO, BLO . . . . . . . . . . . . V

Voltage on AHO, BHO . . . . . .V

-0.3V to V

ALS, BLS

AHS, BHS

AHS, BHS

+16VVoltage on

-0.3V to VCC +0.3V

-0.3V to V

AHB, BHB

+0.3V

Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA

Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20V/ns

NOTE: All V oltages relativ e to pin 4, VSS, unless otherwise specified.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Operating Conditions

Supply Voltage, VDD and VCC . . . . . . . . . . . . . . . . . . . +8V to +15V

Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V

Voltage on AHB, BHB. . . . . . . . V

AHS, BHS

+5V to V

AHS, BHS

+15V

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Maximum Power Dissipation at 85oC

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .470mW

DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530mW

Storage Temperature Range. . . . . . . . . . . . . . . . . . -65oC to 150oC

Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . 125oC

Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

Input Current, HDEL and LDEL. . . . . . . . . . . . . . . . -500µA to -50µA

Operating Ambient Temperature Range . . . . . . . . . . .-40oC to 85oC

Electrical Specifications V

= VCC = V

DD

AHB

= V

BHB

= 12V, VSS = V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

= 100K,

and TA = 25oC, Unless Otherwise Specified

TJ= - 40oC

T

PARAMETERS SYMBOL TEST CONDITIONS

= 25oC

J

TO 125oC

UNITSMIN TYP MAX MIN MAX

SUPPLY CURRENTS AND CHARGE PUMPS

VDD Quiescent Current I
VDD Operating Current I
VCC Quiescent Current I

VCC Operating Current I
AHB, BHB Quiescent Current -

I

AHB

Qpump Output Current

AHB, BHB Operating Current I

AHBO

AHS, BHS, AHB, BHB Leakage Current I
AHB-AHS, BHB-BHS Qpump

Output Voltage

V
V

AHB

BHB

DD

DDO

CC

CCO

HLK

IN- = 2.5V, Other Inputs = 0V 8 10.5 13 7 14 mA
Outputs switching f = 500kHz 9 11 14 8 15 mA
IN- = 2.5V, Other Inputs = 0V,

I

= I

BLO

= 0

ALO

- 25 80 - 100 µA

f = 500kHz, No Load 1 1.5 2.0 0.8 3 mA

, I

IN- = 2.5V, Other Inputs = 0V, I

BHB

I

= 0, VDD = VCC= V

BHO

V

= 10V

BHB

, I

f = 500kHz, No Load 0.5 0.9 1.3 0.4 1.7 mA

BHBO

V

= V

= V

BHS

= 0, No Load 11.5 12.6 14.0 10.5 14.5 V

AHB

- V

AHS

I

AHB

= I

AHS

- V

BHS

AHB

AHB

= V

=

AHO

-50 -30 -15 -60 -10 µA

=

= 95V - 0.02 1.0 - 10 µA

BHB

INPUT COMPARATOR PINS: IN+, IN-, OUT

Offset Voltage V
Input Bias Current I
Input Offset Current I

OS

Input Common Mode Voltage Range CMVR 1 - V

Over Common Mode Voltage Range -10 0 +10 -15 +15 mV

OS

IB

0 0.5 2 0 4 µA

-1 0 +1 -2 +2 µA

DD

-1.5

1V

DD

-1.5
Voltage Gain AVOL 10 25 - 10 - V/mV
OUT High Level Output Voltage V

OUT Low Level Output Voltage V
High Level Output Current I

Low Level Output Current I

OH
OL

IN+ > IN-, IOH = -300µAV

OH

--V

DD

-0.4

IN+ < IN-, IOL = 300µA - - 0.3 - 0.4 V

OL

V
V

OUT
OUT

= 6V
= 6V

-9 -7 -4 -11 -2 mA
8 10 12 5 14 mA

DD

- 0.5

-V

INPUT PINS: DIS

Low Level Input Voltage V
High Level Input Voltage V

Full Operating Conditions - - 1.0 - 0.8 V

IL

Full Operating Conditions 2.5 - - 2.7 - V

IH

Input Voltage Hysteresis - 35 - - - mV

V

4

HIP4080

Electrical Specifications V

= VCC = V

DD

AHB

= V

BHB

= 12V, VSS = V

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

= 100K,

and TA = 25oC, Unless Otherwise Specified (Continued)

TJ= - 40oC

PARAMETERS SYMBOL TEST CONDITIONS

Low Level Input Current I
High Level Input Current I

= 25oC

T

J

VIN = 0V, Full Operating Conditions -130 -100 -75 -135 -65 µA

IL

VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 µA

IH

TO 125oC

UNITSMIN TYP MAX MIN MAX

INPUT PINS: HEN

Low Level Input Voltage V
High Level Input Voltage V

Full Operating Conditions - - 1.0 - 0.8 V

IL

Full Operating Conditions 2.5 - - 2.7 - V

IH

Input Voltage Hysteresis - 35 - - - mV
Low Level Input Current I
High Level Input Current I

VIN = 0V, Full Operating Conditions -260 -200 -150 -270 -130 µA

IL

VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 µA

IH

TURN-ON DELAY PINS: LDEL AND HDEL

LDEL, HDEL Voltage V

HDEL,

VI

HDEL

= I

= -100µA 4.9 5.1 5.3 4.8 5.4 V

LDEL

GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO

Low Level Output Voltage V
High Level Output Voltage VCC - VOHI
Peak Pull-up Current IO+V
Peak Pull-down Current IO-V

Switching Specifications V

= VCC = V

DD

OL

I

= 100mA .70 0.85 1.0 0.5 1.1 V

OUT

= -100mA 0.8 0.95 1.1 0.5 1.2 V

OUT

= 0V 1.7 2.6 3.8 1.4 4.1 A

OUT

= 12V 1.7 2.4 3.3 1.3 3.6 A

OUT

= V

AHB

= 12V, VSS = V

BHB

ALS

= V

BLS

= V

AHS

= V

BHS

= 0V, R

HDEL

= R

LDEL

= 10K,

CL = 1000pF, and TA = 25oC, Unless Otherwise Specified

TJ = - 40oC

T

PARAMETERS SYMBOL TEST CONDITIONS

Lower Turn-off Propagation Delay (IN+/IN- to ALO/BLO) T
Upper Turn-off Propagation Delay (IN+/IN- to AHO/BHO) T
Lower Turn-on Propagation Delay (IN+/IN- to ALO/BLO) T
Upper Turn-on Propagation Delay (IN+/IN- to AHO/BHO) T

HPHL
LPLH
HPLH

Rise Time T
Fall Time T
Turn-on Input Pulse Width T
Turn-off Input Pulse Width T
Disable Turn-off Propagation Delay

PWIN-ONRHDEL

PWIN-OFFRHDEL

T

DISLOW

LPHL

r
f

R
R

HDEL
HDEL

= R
= R

= R
= R

= 25oC

J

- 40 70 - 90 ns

- 50 80 - 110 ns

= 10K - 45 70 - 90 ns

LDEL

= 10K - 70 110 - 140 ns

LDEL

- 10 25 - 35 ns

- 10 25 - 35 ns

= 10K 50 - - 50 - ns

LDEL

= 10K 40 - - 40 - ns

LDEL

- 45 75 - 95 ns

TO 125oC

UNITSMIN TYP MAX MIN MAX

(DIS - Lower Outputs)
Disable Turn-off Propagation Delay

T

DISHIGH

- 55 85 - 105 ns

(DIS - Upper Outputs)
Disable to Lower Turn-on Propagation Delay

T

DLPLH

- 35 70 - 90 ns

(DIS - ALO and BLO)
Refresh Pulse Width (ALO and BLO) T
Disable to Upper Enable (DIS - AHO and BHO) T
HEN-AHO, BHO Turn-off, Propagation Delay T
HEN-AHO, BHO Turn-on, Propagation Delay T

HEN-PHLRHDEL
HEN-PLHRHDEL

REF-PW

UEN

= R
= R

= 10K - 35 70 - 90 ns

LDEL

= 10K - 60 90 - 110 ns

LDEL

160 260 380 140 420 ns

- 335 500 - 550 ns

TRUTH TABLE

INPUT OUTPUT

IN+ > IN- HEN DIS ALO AHO BLO BHO

X X10000

1 100110
0 101001
1 000010
0 001000

5

HIP4080

Pin Descriptions

PIN

NUMBER SYMBOL DESCRIPTION

1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-

strap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

2 HEN High-side Enable input. Logic level input that when low overrides IN+/IN- (Pins 6 and 7) to put AHO and BHO

drivers (Pins 11 and 20) in low output state. When HEN is high AHO and BHO are controlled by IN+/IN- inputs.
The pin can be driven by signal levels of 0V to 15V (no g reater than VDD). An internal 100µA pull-up to VDD will
hold HEN high, so no connection is required if high-side and low-side outputs are to be controlled by IN+/IN­inputs.

3 DIS DISable input. Logic level input that when taken high sets all four outputs low . DIS high ov errides all other inputs.

When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of
0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold DIS high if this pin is not driven.

4VSSChip negative supply, generally will be ground.

5 OUT OUTput of the input control comparator. This output can be used for feedback and hysteresis.

6 IN+ Non-inverting input of control comparator. If IN+ is greater than IN- (Pin 7) then ALO and BHO are low level

outputs and BLO and AHO are high level outputs. If IN+ is less than IN- then ALO and BHO are high level out­puts and BLO and AHO are low level outputs. DIS (Pin 3) high level will override IN+/IN- control for all outputs.
HEN (Pin 2) low level will override IN+/IN- control of AHO and BHO. When switching in four quadrant mode,
dead time in a half bridge leg is controlled by HDEL and LDEL (Pins 8 and 9).

7 IN- Inverting input of control comparator. See IN+ (Pin 6) description.

8 HDEL High-side turn-on DELay . Connect resistor from this pin to VSS to set timing current that defines the turn-on delay

of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees
no shoot-through by delaying the turn-on of the high-side drivers. HDEL ref erence voltage is approximately 5.1V.

9 LDEL Low-side turn-on DELay . Connect resistor from this pin to VSS to set timing current that defines the turn-on delay

of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees
no shoot-through by delaying the turn-on of the low-side drivers. LDEL ref erence v oltage is appro ximately 5.1V.

10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of boot-

strap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this
pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V.

11 AHO A High-side Output. Connect to gate of A High-side power MOSFET.

12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of

bootstrap capacitor to this pin.

13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET.

14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET.

15 V

16 V

17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET.

CC

DD

Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap
diodes.

Positive supply to lo wer gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4).

18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET.

19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of

bootstrap capacitor to this pin.

20 BHO B High-side Output. Connect to gate of B High-side power MOSFET.

6