Intersil Corporation HIP1012A, HIP1012 Datasheet
HIP1012, HIP1012A
Data Sheet November 1999
Dual Power Distribution Controller
The HIP1012 is a HOTSWAP dual supply power distribution
controller. Two external N-Channel MOSFETs are driven to
distribute power while providing load fault isolation.
At turn-on, the gate of each external N-Channel MOSFET is
charged with a 10µA current source. Capacitors on each
gate (see the Typical Application Diagram), create a
programmable ramp (soft turn-on) to control inrush currents.
A built in charge pump supplies the gate drive for the 12V
supply N-Channel MOSFET switch.
Over current protection is facilitated b y tw o external current
sense resistors. When the current through either resistor
exceeds the user programmed v alue the controller enters the
current regulation mode. The time-out capacitor, C
charging as the controller enters the time out period. Once
C
charges to a 2V threshold, the N-Channel MOSFETs
TIM
are latched off. In the event of a fault at least three times the
current limit level, the N-Channel MOSFET gates are pulled
low immediately before entering time out period. The
controller is reset by a rising edge on either PWRON pin.
TIM
, starts
File Number 4419.4
Features
• HOT SWAP Dual Power Distribution Control for +5V and
+12V or +5V and +3.3V
• Provides Fault Isolation
• Programmable Current Regulation Level
• Programmable Time Out
• Charge Pump Allows the Use of N-Channel MOSFETs
• Power Good and Over Current Latch Indicators
• Enhanced Over Current Sensitivity Available
• Redundant Power On Controls
• Adjustable Turn-On Ramp
• Protection During Turn-On
• Two Levels of Current Limit Detection Provide Fast
Response to Varying Fault Conditions
• Less Than 1µs Response Time to Dead Short
•3µs Response Time to 200% Current Overshoot
Choosing the voltage selection mode the HIP1012 controls
either +12V/5V or +3.3V/+5V supplies.
For those applications where voltage tolerance is a concern
the HIP1012A has a minimum nominal over current threshold
voltage of 50mV as compared to 100mV for the HIP1012.
Ordering Information
PART NUMBER
HIP1012CB
HIP1012ACB
HIP1012CB-T
HIP1012ACB-T
Pinout
3/12VS
3/12VG
MODE/
PWRON1
PWRON2
V
DD
5VG
5VS
1
2
3
4
5
6
7
TEMP.
RANGE (oC) PACKAGE
-0 to 70 14 Ld SOIC M14.15
-0 to 70 14 Ld SOIC
Tape and Reel
HIP1012 (SOIC)
TOP VIEW
3/12VISEN
14
R
13
ILIM
GND
12
C
11
PUMP
C
10
TIM
PGOOD
9
5VISEN
8
PKG.
NO.
M14.15
Typical Application Diagram
V
OPTIONAL
R
FILTER
DD
C
FILTER
Applications
• Redundant Array of Independent Disks (RAID) System
• Power Distribution Control
• Hot Plug™, Hot Swap Components
C
PUMP
R
12V
5V
C
GATE
POWER ON
C
GATE
R
GATE
INPUTS
R
GATE
SENSE
HIP1012
3/12VISEN
3/12VS
3/12VG
V
DD
M/
PON1
PWRON2
5VG
5VS
R
SENSE
R
ILIM
GND
C
PUMP
C
TIM
PGOOD
5ISEN
R
ILIM
R
LOAD
R
LOAD
C
TIM
5V OR 3.3V
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
Hot Plug™ is a trademark of Core International, Inc.
| Copyright © Intersil Corporation 1999
Simplified Schematic
R
3X
+
-
+
CLIM
+
-
-
+
3X
SENSE
R
2R
18V
ENABLE
12V
2R
R
+
-
PGOOD
POR
100µA
QPUMP
12V
2V
12V
+
-
10µA
12ISEN
R
ILIM
GND
C
PUMP
C
TIM
PGOOD
5ISEN
R
C
PUMP
C
TIM
12VIN
2
C
20Ω
GATE
OPTIONAL
R
V
FILTER
DD
C
FILTER
20Ω
C
GATE
12VS
12VG
V
DD
PWRON1
PWRON2
5VG
5VS
18V
12V
10µA
RISING
EDGE
RESET
10µA
FALLING
EDGE
DELAY
ENABLE
R
QN
R
S
ENABLE
FALLING
EDGE
DELAY
OC
Q
CLIM
OC
ILIM
TO LOAD
TO V
DD
OC
LATCH
OPTIONAL
HIP1012, HIP1012A
5VIN
HIP1012
R
SENSE
TO LOAD
HIP1012, HIP1012A
Pin Descriptions
PIN # SYMBOL FUNCTION DESCRIPTION
1 3V/12VS 3.3 V/12V Source Connect to source of associated external N-Channel MOSFET switch to sense output
voltage.
2 3V/12VG 3.3V/12V Gate Connect to the gate of associated N-Channel MOSFET switch. A capacitor from this node
togroundsets theturn-on ramp. Atturn-on thiscapacitorwill be charged to 17.4V by a 10µA
current source when in 5v/12V mode of operation, otherwise capacitor will be charged to
11.4V. A small resistor (10 - 200Ω) should be placed in series with the gate capacitor to
ground to prevent current oscillations.
3VDDChip Supply Connect to 12V supply. This can be either connected directly to the +12V rail supplying the
load voltage or to a dedicated VDD+12V supply. If the former is chosen special attention to
VDDdecoupling must be paid.
4 MODE/
PWRON1
5 PWRON2 Power ON/ Reset
6 5VG 5V Gate Connect to the gate of the external 5V N-Channel MOSFET. A capacitor from this node to
7 5VS 5V Source Connect to the source side of 5V external N-Channel MOSFET switch to sense output
8 5VISEN 5V Current Sense Connect to the load side of the 5V sense resistor to measure the voltage drop across this
9 PGOOD Power Good indicator Indicates that all output voltages are within specification. PGOOD is driven by an open drain
10 C
11 C
12 GND Chip Ground
13 R
TIM
PUMP
ILIM
Power ON/ Reset
Invokes 3.3V operation
whenshorted to VDD,pin 3.
Current Limit Timing
Capacitor
Charge Pump
Capacitor
Current Limit Set
Resistor
PWRON1 and PWRON2 are used to turn-on and reset the chip. Both outputs turn-on when
either pin is driven low. After a current limit time out, the chip is reset by the rising edge of a
reset signal applied to either PWRON pin. Each input has 100µA pull up capability which is
compatible with 3V and 5V open drain and standard logic. PWRON1 is also used to invoke
3.3V control operation in preference to +12V control. By tying pin 4 to pin 3the charge pump
is disabled and the UV threshold also shifts to 2.8V.
ground sets the turn-on ramp. At turn-on this capacitor will be charged to 11.4V by a 10µA
current source. A small resistor (10 - 200Ω) should be placed in series with the gate
capacitor to ground to prevent current oscillations.
voltage.
resistor between 5VS and 5VISEN pins.
N-Channel MOSFET. It is pulled low when any output is not within specification.
Connect a capacitor from this pin to ground. This capacitor controls the time between the
onset of current limit and chip shutdown (current limit time-out). The duration of current limit
time-out (in seconds) = 200kΩ x C
Connecta 0.1µF capacitor betweenthis pin and VDD(pin3).Directly connect this pinto V
when in 3.3V control mode.
A resistor connected between this pin and ground determines the current level at which
current limit is activated. This current is determined by the ratio of the R
sense resistor (R
R
). The HIP1012 is limited to a 10kΩ min value (OC Vth = 100mV) resistor whereas
SENSE
the HIP1012A can accommodate a 5kΩ resistor for a lower OC Vth (50mV).
). The current at current limit onset is equal to 10µA x (R
SENSE
TIM
(Farads).
resistor to the
ILIM
ILIM
/
DD
14 3V/12VISEN 3.3V/12V Current Sense Connect to the load side of sense resistor to measure the voltage drop across this resistor.
3
HIP1012, HIP1012A
Absolute Maximum Ratings T
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +13.2V
3/12VG, C
3/12VISEN, 3/12VS . . . . . . . . . . . . . . . . . . . . . . . -5V to VDD+ 0.3V
5VISEN, 5VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-5V to 7.5V
PGOOD, R
MODE/PWRON1, PWRON2, C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 18.5V
PUMP
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7.5V
ILIM
TIM
=25oC Thermal Information
A
Thermal Resistance (Typical, Note 1) θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
, 5VG . . . . .-0.3V to VDD + 0.3V
(SOIC - Lead Tips Only)
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV (Class 2)
Operating Conditions
VDD Supply Voltage Range. . . . . . . . . . . . . . . . . . . +10.5V to +13.2
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications V
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
12V CONTROL SECTION
Current Limit Threshold Voltage
(Voltage Across Sense Resistor)
3X Current Limit Threshold Voltage
(Voltage Across Sense Resistor)
±20% Current Limit Response Time
(Current within 20% of Regulated Value)
±10% Current Limit Response Time
(Current within 10% of Regulated Value)
±1% Current Limit Response Time
(Current within 1% of Regulated Value)
Response Time To Dead Short RT
Gate Turn-On Time t
Gate Turn-On Current I
3X Gate Discharge Current 3XdisI 12VG = 18V 0.5 0.75 - A
12V Under Voltage Threshold 12V
Qpumped 12VG Voltage V12VG C
3.3V/5V CONTROL SECTION
Current Limit Threshold Voltage
(Voltage Across Sense Resistor)
3X Current Limit Threshold Voltage
(Voltage Across Sense Resistor)
±20% Current Limit Response Time
(Current within 20% of regulated value)
±10% Current Limit Response Time
(Current within 10% of Regulated Value)
±1% Current Limit Response Time
(Current within 1% of Regulated Value)
Response Time To Dead Short RT
= 12V,CVG= 0.01µF, C
DD
Unless Otherwise Specified
V
V
3XV
3XV
IL12V
IL12V
iL12V
IL12V
R
R
R
R
20%iLrt 200% Current Overload, R
R
10%iLrt 200% Current Overload, R
R
1%iLrt 200% Current Overload, R
R
SHORTC12VG
ON12V
ON12V
V
IL5V
C
C
VUV
R
R
3XV
IL5VRILIM
R
200% Current Overload, R
R
200% Current Overload, R
R
200% Current Overload, R
R
SHORTCVG
= 0.1µF, R
TIM
=10kΩ
ILIM
= 5kΩ HIP1012A only
ILIM
=10kΩ
ILIM
= 5kΩ HIP1012A only
ILIM
= 6.0Ω
SHORT
= 6.0Ω
SHORT
= 6.0Ω
SHORT
SENSE
= 0.1Ω,C
= 10kΩ,
ILIM
= 10kΩ,
ILIM
= 10kΩ,
ILIM
= 220µF, ESR = 0.5Ω,TA=TJ=0oCto70oC,
BULK
92
47
250
100
100
53
300
165
108
59
350
210
-2-µs
-4-µs
-10-µs
= 0.01µF - 500 1000 ns
= 0.01µF - 12 - ms
12VG
= 0.01µF 8 10 12 µA
12VG
10.5 10.8 11.0 V
= 0.1µF 16.8 17.3 17.9 V
PUMP
=10kΩ
ILIM
= 5kΩ HIP1012A only
ILIM
=10kΩ
= 5kΩ HIP1012A only
ILIM
= 2.5Ω
SHORT
= 2.5Ω
SHORT
= 2.5Ω
SHORT
ILIM
ILIM
ILIM
= 10kΩ,
= 10kΩ,
= 10kΩ,
92
47
250
100
100
53
300
155
108
59
350
210
-2-
-4-
-10-
= 0.01µF - 500 800 ns
mV
mV
mV
mV
mV
mV
mV
mV
µs
µs
µs
4
HIP1012, HIP1012A
Electrical Specifications V
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Gate Turn-On Time t
Gate Turn-On Current I
3X Gate Discharge Current 3XdisI CVG= 0.01µF, PWRON = Low 0.5 0.75 - A
5V Under Voltage Threshold 5V
3.3V Under Voltage Threshold 3.3V
3.3/5VG High Voltage 3/5VG 11.2 11.9 - V
SUPPLY CURRENT AND IO SPECIFICATIONS
VDD Supply Current I
VDD POR Rising Threshold 9.5 10.0 10.7 V
VDD POR Falling Threshold 9.3 9.8 10.3 V
Current Limit Time-Out T
PWRON Pull-up Voltage PWRN_V PWRON pin open 1.8 2.4 3.2 V
PWRON Rising Threshold PWR_Vth 1.1 1.5 2 V
PWRON Hysteresis PWR_hys 0.1 0.2 0.3 V
PWRON Pull-Up Current PWRN_I 60 80 100 µA
Current Limit Time-Out Threshold (C
C
Charging Current C
TIM
C
Discharge Current C
TIM
C
Pull-Up Current C
TIM
R
Pin Current Source Output R
ILIM
Charge Pump Output Current Qpmp_Io C
Charge Pump Output Voltage Qpmp_Vo No load 17.2 17.4 - V
Charge Pump Output Voltage - Loaded Qpmp_VIo Load current = 100µA 16.2 16.7 - V
Charge Pump POR Rising Threshold Qpmp+Vth 15.6 16 16.5 V
Charge Pump POR Falling Threshold Qpmp-Vth 15.2 15.7 16.2 V
= 12V,CVG= 0.01µF, C
DD
Unless Otherwise Specified (Continued)
ON5V
ON5V
VUV
VUV
VDD
ILIM
)C
TIM
_Vth 1.8 2 2.2 V
TIM
_I 8 10 12 µA
TIM
_disI 1.7 2.6 3.5 mA
TIM
_disI V
TIM
_Io 90 100 110 µA
ILIM
= 0.1µF, R
TIM
CVG= 0.01µF-5-ms
CVG= 0.01µF 8 10 12 µA
C
= 0.1µF 162024ms
TIM
= 8V 3.5 5 6.5 mA
CTIM
= 0.1µF, C
PUMP
= 0.1Ω,C
SENSE
= 16V 320 560 800 µA
PUMP
= 220µF, ESR = 0.5Ω,TA=TJ=0oCto70oC,
BULK
4.35 4.5 4.65 V
2.65 2.8 2.95 V
4 8 10 mA
HIP1012 Description and Operation
The HIP1012 is a multi featured dual power supply
distribution controller, including programmable current
limiting regulation and time to latch off. Additionally the
HIP1012 operates both as a +3.3V and 5V or a +5V and
+12V power supply controller with each mode having
appropriate Under Voltage (UV) fault notification levels.
Upon initial power up HIP1012 can either isolate the
voltage supply from the load by holding the external
N-Channel MOSFET switches off or apply the supply rail
voltage directly to the load for true hot swap capability. In
either case the HIP1012 turns on in a soft start mode
protecting the supply rail from sudden current loading. If
either
PWRON pin is pulled low the HIP1012 will be in true
hot swap mode. Both
the HIP1012 thus isolating the power supply from the load
through the external FETs.
PWRON pins must be high to turn off
5
At turn-on, the gate capacitor of each external N-Channel
MOSFET is charged with a 10µA current source. These
capacitors create a programmable ramp (soft turn-on). A
charge pump supplies the gate drive for the 12V supply
switch driving that gate to 17V.
The load currents pass through two external current sense
resistors. When the voltage across either resistor exceeds
the user programmed Over Current (OC) voltage threshold
value, (see Table 1) the controller enters current regulation.
At this time the time-out capacitor,C
, starts charging with
TIM
a10µA current source and the controller enters the time out
period. The length of the time out period is set by the single
external capacitor (see Table 2) placed from the C
TIM
pin
(pin 10) to ground and is characterized by a lowered gate
drive voltage to the appropriate external N-Channel
MOSFET. Once C
charges to 2V, an internal comparator
TIM
is tripped resulting in both N-Channel MOSFETs being
latched off.
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