Intersil Corporation HIP0063 Datasheet

HIP0063

PRELIMINARY

October 1995

Features

• Six Channel MOSFET Driver with Gate Drive
Control by Serial (SPI) or Parallel Interface and
an Option for PWM Logic Switching Control

• Drain Monitor Provides Fault Detection and
Voltage Clamp for Each Channel

• Output Voltage Zener Clamp. . . . . . . . . . 67V Typ

• 5V CMOS Logic Level Input Control

•V

Logic Level Power Supply

CC

- 5V V

- Turns Off Gate Drive for Low or Loss of V

•V

PWR

- 5.5V to 17V Battery/System Level Power

- Over-Voltage Shutdown. . . . . . . . . . . . 35V Typ

• Output Supply/Load Short and Open
Load/Ground Short Fault Detection

• Automatic Change to Low Duty Cycle Drive
Mode When Output Short-to-Supply Detected

• Fault Diagnostic Feedback via the SPI Bus

• Operating Temp Range . . . . . . . -40

Applications

• Automotive and Industrial Systems

• Control of Solenoids, Relays and Lamp Drivers

• Interface to Logic and µP Controllers

• Robotic System Controller

Logic Power Supply

CC

System Level Power Supply Management

Supply Monitor

o

C to +125oC

Hex Low Side MOSFET Driver with Serial or

Parallel Interface and Diagnostic Fault Control

Description

The HIP0063 is a logic controlled, six channel Low Side Power Driver. As
shown in the Block Diagram, the outputs are controlled via the serial data
interface or, by user option, each output may be independently controlled
from the respective parallel input. In addition, PWM logic switching control
(HLOS) may be directly applied to channels 0 and 1 in parallel, or channels 4
and 5 in parallel.

Output fault conditions may be detected as an output load short to supply
when the output is ON or as an open load/ground short when the output is
OFF. If an over-current short exists at one output, gate drive goes to a low
duty cycle mode. It will remain in the low duty cycle mode until switched off or
the fault is cleared. Fault bits are sent to a fault register to indicate which

CC

channel is at fault. The fault bits are indicated by a logic one and is internally
latched when CS goes low. A f ault bit will return to zero when the fault disap­pears. Either an 8-bit or 16-bit SPI communication mode may be used. Ref er
to the application section for bit control information.

Over-voltage shutdown protection f or all outputs will occur when V

PWR

(Battery/
MOSFET Supply) exceeds 35V typical. When VCC is less than 3.5V, gate drive
is switched off. The input and gate control logic is fully function when the V

CC

supply is greater than 4V typical. The HIP0063 has an internal drain-to-gate
zener which is used to voltage clamp the output drain-to-source voltage of the
MOSFET.

The HIP0063 is fabricated in a Pow er BiMOS IC process, and is intended for
use in automotive and other applications having a wide range of temperature
and electrical stress conditions. It is particularly well suited for MOSFET con­trol in circuits driving lamps, displays, relays, and solenoids in applications
requiring low operating power .

Ordering Information

PART

NUMBER

HIP0063AB -40oC to +125oC 28 Lead Plastic SOIC (W)

TEMPERATURE

RANGE PACKAGE

Pinout

Block Diagram

HIP0063 SOIC

TOP VIEW

28

HLOS

1

P10

P11
P12
P13
P14
P15

CS
SO

SCK

GND

2
3
4
5
6
7
8

9
10
11
12

SI

13
14

HPW01
HPW45

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

V

PWR

G0

27

D0

26
25

G1

24

D1

23

D2
G2

22
21

G3

20

D3

19

D4

18

G4

17

D5

16

G5

15

V

CC

V

PWR

V

CC

HPW01
HPW45

HLOS

CS

SI

SO

SCK

PI0-5

| Copyright © Intersil Corporation 1999

OVSD

POR

MUX

PWM

CONTROL

SPI (SER.)
CONTROL

(6)

1

CHANNEL#0 - (1 OF 6)

+5V

S0

S6

P0

S0-5
F0-5
PI0-5

F0

OVSD

TG

TG

HIP0063

FAULT LOGIC

AND LATCH

FAULT DATA

GATE

CONTROL

LOGIC

POR

OSC AND

TIME DELAY

CONTROL

+V

PWR

D0

(DRAIN
MONITOR
VOLT,V

G0

(GATE DR.

GND

EXT POWER
MOSFET AND
TYP LOAD

DM

VOLT.,VG)

)

File Number 4009

HIP0063

S0
SI
SCK
CS

PI0

PI1

PI2

PI3

PARALLEL INPUTS

PI4

PI5

SPI

PARALLEL/
SERIAL IN,
SHIFT REG.
CONTROL

PARALLEL/
SERIAL IN,
SHIFT REG.
CONTROL

PARALLEL/
SERIAL IN,
SHIFT REG.
CONTROL

PARALLEL/
SERIAL IN,
SHIFT REG.
CONTROL

PARALLEL/
SERIAL IN,
SHIFT REG.
CONTROL

PARALLEL/
SERIAL IN,
SHIFT REG.
CONTROL

DAT A

LATCH

DAT A

LATCH

DAT A

LATCH

DAT A

LATCH

DAT A

LATCH

DAT A

LATCH

V

CC

5V

POR, TIMING OSC,
BAND GAP REF.,
OVER-VOLT. DET.

DRIVE CONTROL

CHANNEL #0

DRIVE CONTROL

CHANNEL #1

DRIVE CONTROL

CHANNEL #2

DRIVE CONTROL

CHANNEL #3

DRIVE CONTROL

CHANNEL #4

DRIVE CONTROL

CHANNEL #5

V

PWR

14V

V

(V

14V

BATT

)

DRAIN MONITOR

GATE DRIVER

DRAIN MONITOR

GATE DRIVER

DRAIN MONITOR

GATE DRIVER

DRAIN MONITOR

GATE DRIVER

DRAIN MONITOR

GATE DRIVER

DRAIN MONITOR

GATE DRIVER

PWR

D0

G0

D1

G1

D2

G2

D3

G3

D4

G4

D5

G5

HLOS (SEL)
HPW01
HPW45

HLOS

GND

HARDWARE GENERATED OR CUSTOM LOGIC
SOURCED PWM CONTROL SIGNAL INPUTS

HIP0063

2 - HIP0061
OR EQUIVALENT

FIGURE 1. TYPICAL APPLICATION CIRCUIT FOR THE HIP0063 SHOWING HOW THE GATE DRIVE OUTPUT AND DRAIN MONITOR

INPUT CONTROLS TWO HIP0061 THREE FET ARRAYS

CS

SCK

(CPOL = 0, CPHA = 1)

MSB 6 5 4 3 2 1 LSB

INTERNAL STROBE FOR DATA CAPTURE

FIGURE 2. SPI DATA AND CLOCK TIMING DIAGRAM. SERIAL COMMUNICATION IS INITIATED WHEN CS GOES LOW AND SCK

IS LOW. 8 OR 16 BITS OF DATA IS CLOCKED INTO SI ON THE LEADING EDGE OF SCK. DATA IS CLOCKED OUT OF
SO ON THE TRAIL EDGE OF SCK. WHEN CS GOES HIGH, DATA IS LATCHED TO CONTROL EACH CHANNEL

2

Specifications HIP0063

Absolute Maximum Ratings Thermal Information (Typical)

Logic Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V

Max Quiescent Logic Supply Current, ICC. . . . . . . . . . . . . . . . .5mA

Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . .-0.3V to VCC+ 0.3V

System Supply Voltage Monitor, V

PWR

(Note 1)

Max Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 38V

Max Drain Clamp Voltage, VDM (Note 2) . . . . . . . . . . . . . . . . . . 75V

Max Gate Drive Output Voltage, VG (Note 3) . . . .-0.3 to VCC + 0.3V

Operating Ambient Temperature Range, TA. . . . -40oC to +125oC

Operating Junction Temperature Range . . . . . . -40oC to +150oC

Storage Temperature Range, T

. . . . . . . . . . -55oC to +150oC

STG

Lead Temperature (Soldering 10s Max). . . . . . . . . . . . . . . +265oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Resistance θ

28 Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . . . 75oC/W

JA

Electrical Specifications V

= 4.5V to 5.5V, V

CC

PARAMETERS SYMBOL CONDITIONS MIN TYP MAX UNITS

POWER SUPPLY
Logic Supply Quiescent Current I
VCC Threshold for POR Reset V

POR Hysteresis V

Undervoltage Lockout, Low V

CC

Battery Supply Monitor Current I
V

Over-Voltage Shutdown

PWR

V

Threshold
V

Over-Voltage Shutdown

PWR

V

PWR_OVHYS

Hysteresis
LOGIC INPUTS
Input High Voltage; SI, SCK, CS V
Input Low Voltage; SI, SCK, CS V
Input Leakage Current; SI, SCK I
Input Pulldown Currents;

PI0-5, HPW01, HPW45
Input Pullup Currents; CS, HLOS I
Threshold Voltage at Falling Edge,

PI0-5, HLOS, HPW01, HPW45
Threshold Voltge at Rising Edge,

PI0-5, HLOS, HPW01, HPW45
Input Hysteresis Voltage;

PI0-5, HLOS, HPW01, HPW45
Input Capacitance, SCK, SI C
DATA OUTPUT
SO Data Output High Voltage V
SO Data Output Low Voltage V
SO Three-State Leakage Current I
SO Three-State Capacitance C

= 5.5V to 17V, TA = -40oC to +125oC, Unless Otherwise Specified

PWR

CC

POR

PI0-5 High (ON), Increase VCC, Measure

--5mA

3.5 4 4.25 V
VCC Threshold When Gate Drive Goes
High

POR_HYS

PI0-5 High, Decrease VCC, Measure V

CC

- 500 - mV
Threshold when Gate Drive goes Low,
Hysteresis Equals Differential VCC Voltage
for Gate Drive High to Gate Drive Low

V

CC

PWR

PWR_OVTHVPWR

V

= 14V 1 2 3.7 V

PWR

V

= 14V - - 150 µA

PWR

Threshold Measured When Gate

30 35 40 V

Drive Voltage, VGGoes Low

-1-V

LK

I

IN_PD

IN_PU

IH

IL

0.7V

CC

- - 0.3V

-10 0 10 µA

0.3VCC< VIN< V

GND < VIN < 0.7 V

CC

CC

31025µA

-25 -10 -2 µA

--V

CC

VT- 1.5 2.2 3.0 V

VT+ 1.8 2.6 3.4 V

V

IN_HYS

SOT

IN

OH

OL

SOT

0 < VIN< V

CC

IO = 5mA Source Current 0.8V
IO = 5mA Sink Current - 0.2 0.4 V
VCC = 0V to 5.5V -10 1 10 µA
0 < VIN< V

CC

250 500 650 mV

- 7 12 pF

CC

--V

-1520pF

V

3