Intersil HI5905EVAL2 User Manual
TM
HI5905EVAL2 Evaluation Board User’s Manual
Application Note January 1999
Description
The HI5905EV AL2 evaluation board allows the circuit
designer to evaluate the performance of the Intersil HI5905
monolithic 14-bit, 5MSPS analog-to-digital converter (ADC).
As shown in the Evaluation Board Functional Block Diagr am,
the evaluation board includes sample cloc k gener ation
circuitry, a single-ended to differential analog input amplifier
configuration and digital data output latches/buffers . The
buffered digital data outputs are conveniently provided for
easy interfacing to a ribbon connector or logic probes. In
addition, the evaluationboardincludessomeprototypingarea
for the addition of user designed custom interfaces or circuits .
The sample clock generator circuit accepts the external
sampling signal through anSMAtypeRFconnector, J2. This
input is AC-coupled and terminated in 50Ω allowing for
connection to most laboratory signal generators. In addition,
the duty cycle of the clock driving the A/D converter is
Evaluation Board Functional Block Diagram
AN9785
adjustable by way of a potentiometer. This allows the effects
of sample clock duty cycle on the HI5905 to be observed.
The analog input signal is also connected through an SMA
type RF connector, J1, and applied to a single-ended to
differential analog input amplifier. This input is AC-coupled
and terminated in 50Ω allowing for connection to most
laboratory signal generators. Also, provisions for a
differential RC lowpass filter is incorporated on the output of
the differential amplifier to limit the broadband noise going
into the HI5905 converter.
The digital data output latches/buffers consist of a pair of
74ALS574A D-type flip-flops. With this digital output
configuration the digital output data transitions seen at the
I/O connector are essentially time aligned with the rising
edge of the sampling clock.
CLK IN
J2
ANALOG
J1
DGND
TTL COMPARATOR
CLOCK
50Ω
-5V
D
IN
50Ω
AGND
+5V
-5V
D
D
+5V
G = +1
G = -1
+5VA-5V
D
CLK
V
REFOUT
V
REFIN
V
IN+
0-D13
14
D>Q
D
V
IN-
HI5905
A
14
OUT
(CLK)
DIGITAL
DAT A
OUT
(D0 - D13)
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3-1
Application Note 9785
Reference Generator, V
ROUT
and V
RIN
The HI5905 has an internal reference voltage generator,
therefore no external reference voltage is required. The eval
board, however, offers the ability to use the internal or an
external reference.V
must be connected to V
ROUT
RIN
when
using the internal reference. Internal to the converter, two
reference voltages of 1.3V and 3.3V are generated making
for a fully differential analog input signal range of
±2V.
The HI5905 can be used with an external reference. The
converter requires only one external reference voltage
connected to the V
evaluation board is configured with V
pin with V
RIN
left open. The
ROUT
ROUT
connected to V
RIN
through a 0Ωresistor , R4. If it is desired to e v aluate the
performance of the converter utilizing an externally provided
reference voltage, R4 can be remo v ed and the alternate
referencevoltagecanbebrought in through twisted pair wire or
coaxial cable. The latter would be the recommended method
since it would provide the greatest immunity to e xternally
coupled noise voltages. In order to minimize overall converter
noise it is recommended that adequate high frequency
decoupling be provided at the reference input pin, V
RIN
.
Analog Input
The fully differential analog input of the HI5905 A/D can be
configured in various ways depending on the signal source
and the required level of performance.
The difference between the conv erter's two internally
generated voltage references is 2V. For the AC coupled
differentialinput(Figure1),ifV
IN
is a 2V
sinewav ewith-V
P-P
being 180 degrees out of phase with VIN, the converter will be
at positivefullscalewhen the V
V
- input is at VDC - 1V (VIN+ - VIN- = +2V). Conversely, the
IN
ADC will be at negative full scale when the V
to V
- 1V and VIN- is at VDC + 1V (VIN+ - VIN- = -2V).
DC
+ input isatVDC+ 1Vandthe
IN
+ input is equal
IN
It should be noted that overdriving the analog input beyond
the ±2.0V fullscale input voltage range will not damage the
converter as long as the overdrive voltage stays within the
converters analog supply voltages. In the event of an
overdrive condition the converter will recover within one
sample clock cycle.
+5V
VIN+V
VIN+
2.0V
2.0V
P-P
FIGURE 2A.
P-P
FIGURE 2B.
-
IN
VDC = 4.0V
V
-
IN
1.0V < VDC < 4.0V
+5V
IN
Differential Analog Input Configuration
A fully differential connection (Figure 1) will yield the best
performance from the HI5905 A/D converter. Since the HI5905
is powered off a single +5V supply, the analog input must be
biased so it lies within the analog input common mode voltage
range of 1.0V to 4.0V .Figure2illustratesthedifferentialanalog
input common mode voltage range that the conv erter will
accommodate. The performance of the ADC does not change
significantly with the value of the common mode voltage.
V
IN
-V
IN
FIGURE 1. AC COUPLED DIFFERENTIAL INPUT
A 2.3V DC bias voltage source, V
DC
and bottom internally generated reference voltages, is made
availableto the user to help simplify circuit design when using a
differential input. This low output impedance voltage source is
not designed to be a reference but makes an excellent bias
source and stays within the analog input common mode
voltage range ov er temperature . The DC v oltage source has a
temperature coefficient of about +200ppm/
VIN+
HI5905
V
DC
VIN-
, half way between the top
o
C.
+
V
IN
2.0V
P-P
0V
FIGURE 2C.
FIGURE 2. DIFFERENTIAL ANALOG INPUT COMMON MODE
VOLTAGE RANGE
V
-
IN
VDC = 1.0V
0V
Evaluation Board Layout and
Power Supplies
The HI5905 evaluation board is a four layer board with a
layout optimized for the best performance of the ADC. This
application note includes an electrical schematic of the
evaluation board, a component parts list, a component
placement layout drawing and reproductions of the various
board layers used in the board stack-up. The user should
feel free to copy the layout in their application. Refer to the
component layout and the evaluation board electrical
schematic for the following discussions.
The HI5905 monolithic A/D converter has been designed
with separate analog and digital supply and ground pins to
keep digital noise out of the analog signal path. The
evaluation board provides separate low impedance analog
and digital ground planes on layer 2. Since the analog and
digital ground planes are connected together at a single
point where the power supplies enter the board, DO NOT tie
them together back at the power supplies.
3-2
Application Note 9785
The analog and digital supplies are also kept separate on
the evaluation board and should be driven by clean linear
regulated supplies. The external power supplies are hooked
up with the twisted pair wires soldered to the plated through
holes marked +5VAIN, +5VAIN1, -5VAIN, +5VDIN,
+5VD1IN, +5VD2IN, -5VDIN, AGND and DGND near the
analog prototyping area. +5VDIN, +5VD1IN, +5VD2IN
and -5VDIN are digital supplies and are returned to DGND.
+5VAIN, +5VAIN1 and -5VAIN are the analog supplies and
are returned to AGND. Table 1 lists the operational supply
voltages, typical current consumption and the evaluation
board circuit function being powered. Single supply
operation of the converter is possible but the overall
performance of the converter may degrade.
TABLE 1. HI5905EVAL2EVALUATION BOARDPOWER
SUPPLIES
POWER
SUPPLY
+5VAIN 5.0V ±5% 80mA Op Amps, A/D AV
-5VAIN -5.0V ±5% 30mA Op Amps
+5VDIN 5.0V ±5%3 60mA CLK Comparator,
+5VD1IN 5.0V ±5% 14mA A/D DV
+5VD2IN 5.0V ±5% 6mA A/D DV
-5VDIN -5.0V ±5% 3mA CLK
NOMINAL
VALUE
CURRENT
(TYP)
FUNCTION(S)
SUPPLIED
CC
Inverter
D0-D13 D-FF’s
CC1
CC2
Comparator
Sample Clock Driver, Timing and I/O
In order to ensure rated performance of the HI5905, the duty
cycle of the sample clock should be held at 50% ±5%. It
must also have low phase noise and operate at standard
TTL levels.
A voltage comparator (U3) with TTL output levelsisprovided
on the evaluation board to generate the sampling clock for
the HI5905 when a sinewave (< ±3V) or squarewave clock is
applied to the CLK input (J2) of the evaluation board. A
potentiometer (VR1) is provided to allow the user to adjust
the duty cycle of the sampling clock to obtain the best
performance from the ADC and to allow the user to
investigate the effects of expected duty cycle variations on
the performance of the converter. The HI5905 clock input
trigger level is approximately 1.5V. Therefore, the duty cycle
of the sampling clock should be measured at this 1.5V
trigger level. Test point TP2 provides a convenient point to
monitor the sample clock duty cycle and make any required
adjustments.
Figure 3 shows the sample clock and digital data timing
relationship for the evaluation board. The data
corresponding to a particular sample will be available at the
digital data outputs of the HI5905 after the data latency time,
t
, of 4 sample clock cycles plus the HI5905 digital data
LAT
output delay, t
expected fortheindicatedtiming delays.Refer to the HI5905
data sheet for additional timing information.
. Table 2 lists the values that can be
OD
SINEWAVE CLK IN
HI5905 SAMPLE
CLOCK INPUT
(CLK AT TP2)
HI5905 DIGITAL
DATA OUTPUT
(CLK AT TP1, P2-C20 OR P2-31)
DIGITAL DATA OUTPUTS
(J2)
(D0 - D13)
CLOCK OUT
(74ALS574)
FIGURE 3. EVALUATION BOARD CLOCK AND DATA TIMING RELATIONSHIPS
t
PD1
t
OD
DATA N-1
DATA N
t
PD2
DATA NDATA N-1
3-3
Application Note 9785
TABLE 2. TIMING SPECIFICATIONS
PARAMETER DESCRIPTION TYP
t
t
PD1
t
PD2
OD
HI5905 Digital Output Data Delay 50ns
U4 Prop Delay 4.5ns
U2/3 Prop Delay 9ns
The sample clock and digital output data signals are made
available through two connectors contained on the
evaluation board. The line buffering provided by the data
output latches allows for driving long leads or analyzer
inputs. These data latches are not necessary for the digital
output data if the load presented to the converter does not
exceedthedatasheetloadlimits of 100µA and 15pF. TheP2
I/O connector allows the evaluation board to be interfaced to
the DSP evaluation boards available from Intersil.
Alternatively, the digital output data and sample clock can
also be accessed by clipping the test leads of a logic
analyzer or data acquisition system onto the I/O pins of
connector header P1.
HI5905 Performance Characterization
Dynamic testing is used to evaluate the performance of the
HI5905 A/D converter. Among the tests performed are
Signal-to-Noise and Distortion Ratio (SINAD), Signal-toNoise Ratio (SNR), Total Harmonic Distortion (THD),
Spurious Free Dynamic Range (SFDR) and InterModulation
Distortion (IMD).
Figure 4 shows the test system used to perform dynamic
testing on high-speed ADCs at Intersil. The clock (CLK) and
analog input (V
HP8662A synthesized signal generators that are phase locked
to each other to ensure coherence. The output of the signal
generator driving the ADC analog input is bandpass filtered to
improve the harmonic distortion of the analog input signal. The
comparator on the evaluation board will con v ert the sine wav e
CLK input signal to a square wave at TTL logic le vels to drive
the sample clock input of the HI5905. The ADC data is
captured bya logic analyzer andthentransferred overtheGPIB
) signals are sourced from low phase noise
IN
bustothePC.The PC has the required software to perform the
Fast F ourier Transform (FFT) and do the data analysis.
Coherent testing is recommended in order to avoid the
inaccuracies of windowing. The sampling frequency and
analog input frequency have the following relationship: F
I/FS
= M/N, where FI is the frequency of the input analog
sinusoid, F
is the sampling frequency, N is the number of
S
samples, and M is the number of cycles over which the
samples are taken. By making M an integer and odd number
(1, 3, 5, ...) the samples are assured of being nonrepetitive.
Refer to the HI5905 data sheet for a complete list of test
definitions and the results that can be expected using the
evaluation board with the test setup shown. Evaluating the
part with a reconstruction DAC is only suggested when
doing bandwidth or video testing.
HP8662A
CLK
COMPARATOR
EVALUATION BOARD
FIGURE 4. HIGH-SPEED A/D PERFORMANCE TEST SYSTEM
REF
HI5905EVAL2
HP8662A
BANDPASS
FILTER
V
IN
V
IN
CLK
HI5905
DIGITAL DATA OUTPUT
14
DAS9200
GPIB
PC
3-4
Application Note 9785
HI5905EVAL2 Typical Performance (Input Amplitude at -0.5dBFS)
12
11
10
9
ENOB (BITS)
8
7
1
INPUT FREQUENCY (MHz)
10
FIGURE 5. EFFECTIVE NUMBER OF BITS(ENOB) vs INPUT
FREQUENCY
75
65
100
75
65
-THD (dB)
55
45
1
INPUT FREQUENCY (MHz)
10
FIGURE 6. TOTAL HARMONIC DISTORTION(THD) vs INPUT
FREQUENCY
90
80
100
SINAD (dB)
55
45
1
75
65
SNR (dB)
55
70
-2HD (dB)
60
INPUT FREQUENCY (MHz)
10
100
50
1
INPUT FREQUENCY (MHz)
10
FIGURE 7. SINAD vs INPUT FREQUENCY FIGURE 8. SECOND HARMONIC DISTORTION (2HD)vs
INPUT FREQUENCY
80
70
-3HD (BITS)
60
100
45
1
INPUT FREQUENCY (MHz)
10
FIGURE 9. SNR vs INPUT FREQUENCY FIGURE10. THIRD HARMONIC DISTORTION (3HD) vsINPUT
3-5
100
50
1
INPUT FREQUENCY (MHz)
10
100
FREQUENCY
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