Intersil Corporation HI5813 Datasheet

August 1997

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HI5813

CMOS 3.3V, 25 Microsecond, 12-Bit, Sampling

A/D Converter with Internal Track and Hold

[ /Title
(HI581

3)
Sub­ect

(CMO
S

3.3V,

25
Micro­sec­ond,
12­Bit,
Sam­pling
A/D
Con­verter
with
Inter­nal
Track
and
Hold)

Autho

r ()

Key-

words
(Inter­sil
Corpo­ration,
Semi­con­ductor,
A/D,
ADC,
flash,

Features

• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 25µs

• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .40 KSPS

• Built-In Track and Hold

• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . +3.3V

o

• Maximum Power Consumption at 25

C. . . . . . . . 3.3mW

Applications

• Remote Low Power Data Acquisition Systems

• Battery Operated Systems

• Pen Based PC Handheld Scanners

• DSP Modems

• General Purpose DSP Front End

• µP Controlled Measurement Systems

• PCMCIA Type II Compliant

• PC Based Industrial Controls/DAQ Systems

Pinout

HI5813 (PDIP, CERDIP, SOIC)

TOP VIEW

1

DRDY

(LSB) D0

2
3

D1

4

D2

5

D3

6

D4

7

D5

8

D6

9

D7

10

D8

11

D9

V

12

SS

Description

The HI5813 is a 3.3V, very low power, 12-bit, successive
approximation analog-to-digital converter. It can operate
from a single 3V to 6V supply and typically draws a maxi­mum of 1.0mA (at 25
HI5813 features a built-in track and hold. The conversion
time is as low as 25µs with a 3.3V supply.

The twelve data outputs feature full high speed CMOS three­state bus driver capability, and are latched and held through
a full conversion cycle. The output is user selectable: (i.e.)
12-bit , 8-bit (MSBs), and/or 4-bit (LSBs). A data ready flag
and conversion start input complete the digital interface.

o

C) when operating at 3.3V. The

Ordering Information

INL (LSB)

PART

NUMBER

HI5813JIP ±4.0 -40 to 85 24 Ld PDIP E24.3
HI5813KIP ±2.5 -40 to 85 24 Ld PDIP E24.3
HI5813JIB ±4.0 -40 to 85 24 Ld SOIC M24.3
HI5813KIB ±2.5 -40 to 85 24 Ld SOIC M24.3
HI5813JIJ ±4.0 -40 to 85 24 Ld CERDIP F24.3
HI5813KIJ ±2.5 -40 to 85 24 Ld CERDIP F24.3

24
23
22
21
20
19
18
17
16
15
14
13

(MAX OVER

V

DD

OEL
CLK
STRT
V

-

REF

+

V

REF

V

IN

+

V

AA

VAA­OEM
D11 (MSB)
D10

TEMP.)

TEMP.

RANGE

(oC) PACKAGE

PKG.

NO.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

6-1802

File Number 3634.1

Functional Block Diagram

HI5813

V

V
V

REF

V

AA

VAA-

STRT

DD
SS

V

IN

+

+

TO INTERNAL LOGIC

50Ω
SUBSTRATE

64C

63

32C

16C

8C

4C

2C

C

32C

16C

8C

4C

2C

CONTROL

AND

TIMING

12-BIT

SUCCESSIVE

APPROXIMATION

REGISTER

12-BIT EDGE

TRIGGERED

“D” LATCHED

CLOCK

CLK

DRDY

OEM

D11 (MSB)

D10

D9

D8

D7

D6

D5

D4

V

REF

P1

-

C

C

D3

D2

D1

D0 (LSB)

OEL

6-1803

HI5813

Absolute Maximum Ratings Thermal Information

Supply Voltage

VDD to VSS . . . . . . . . . . . . . . . . . . . .(VSS -0.5V) < VDD < +6.5V

VAA+ to VAA-. . . . . . . . . . . . . . . . . . . . (VSS -0.5V) to (VSS +6.5V)

VAA+ to VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V

Analog and Reference Inputs

VIN,V

Digital I/O Pins . . . . . . . . . . . . . . (VSS -0.3V) < VI/O < (VDD+0.3V)

REF

+, V

-. . . . . . . . . (VSS -0.3V) < V

REF

< (VDD +0.3V)

INA

Operating Conditions

Temperature Range

PDIP, SOIC, and CERDIP Packages . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 80 N/A

SOIC Package. . . . . . . . . . . . . . . . . . . 75 N/A

CERDIP Package . . . . . . . . . . . . . . . . 60 12

Maximum Junction Temperature

PDIP and SOIC Packages. . . . . . . . . . . . . . . . . . . . . . . . . . 150oC

CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC

Maximum Storage Temperature Range . . . . . . . . . .-65οC to 150oC

Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

Electrical Specifications V

PARAMETER TEST CONDITIONS

ACCURACY

Resolution 12 - - 12 - Bits
Integral Linearity Error, INL

(End Point)

Differential Linearity Error, DNL J - - ±4.0 - ±4.0 LSB

Gain Error, FSE
(Adjustable to Zero)

Offset Error, V
(Adjustable to Zero)

DYNAMIC CHARACTERISTICS

Signal to Noise Ratio, SINAD

Signal to Noise Ratio, SNR

Total Harmonic Distortion, THD J fS = 750kHz, fIN = 1kHz - -68.4 - - - dBc

Spurious Free Dynamic Range,
SFDR

ANALOG INPUT

Input Current, Dynamic At VIN = V
Input Current, Static Conversion Stopped - ±0.4 ±10 - ±10 µA

OS

RMS Signal

RMS Noise + Distortion

RMS Signal

RMS Noise

= VAA+ = V

DD

CLK = 500kHz (K suffix), Unless Otherwise Specified

J--±4.0 - ±4.0 LSB
K--±2.5 - ±2.5 LSB

K--±2.0 - ±2.0 LSB
J--±2.0 - ±2.0 LSB
K--±2.0 - ±2.0 LSB
J--±3.0 - ±3.0 LSB
K--±2.5 - ±2.5 LSB

JfS = 600kHz, fIN = 1kHz - 61.5 - - - dB
KfS = 500kHz, fIN = 1kHz - 63.9 - - - dB

JfS = 600kHz, fIN = 1kHz - 63.2 - - - dB
KfS = 500kHz, fIN = 1kHz - 65.1 - - - dB

KfS = 750kHz, fIN = 1kHz - -70.8 - - - dBc
JfS = 600kHz, fIN = 1kHz - 69.0 - - - dB
KfS = 500kHz, fIN = 1kHz - 71.8 - - - dB

+ = 3.3V, VSS = VAA- = V

REF

+, 0V - ±50 ±100 - ±100 µA

REF

- = GND, CLK = 600kHz (J suffix),

REF

25oC -40oC TO 85oC

UNITSMIN TYP MAX MIN MAX

6-1804

HI5813

Electrical Specifications V

= VAA+ = V

DD

+ = 3.3V, VSS = VAA- = V

REF

- = GND, CLK = 600kHz (J suffix),

REF

CLK = 500kHz (K suffix), Unless Otherwise Specified (Continued)

25oC -40oC TO 85oC

PARAMETER TEST CONDITIONS

UNITSMIN TYP MAX MIN MAX

Input Bandwidth -3dB - 1 - - MHz
Reference Input Current - 160 - - - µA
Input Series Resistance, R

Input Capacitance, C
Input Capacitance, C

SAMPLE
HOLD

S

In Series with Input
C

SAMPLE

- 420 - - - Ω

During Sample State - 380 - - - pF

During Hold State - 20 - - - pF
DIGITAL INPUTS OEL, OEM, STRT
High-Level Input Voltage, V
Low-Level Input Voltage, V
Input Leakage Current, I
Input Capacitance, C

IL

IN

IH

IL

Except CLK, VIN = 0V, 5V - - ±10 - ±10 µA

2.4 - - 2.4 - V

- - 0.8 - 0.8 V

-10 - - pF

DIGITAL OUTPUTS

High-Level Output Voltage, V
Low-Level Output Voltage, V
Three-State Leakage, I

OZ

OH

OL

I

SOURCE

I

SINK

Except DRDY, V

= -400µA 2.6 - - 2.6 - V

= 1.6mA - - 0.4 - 0.4 V

OUT

= 0V,

--±10 - ±10 µA

3.3V

Output Capacitance, C

OUT

Except DRDY - 20 - - - pF

TIMING

Conversion Time (t
(Includes Acquisition Time)

Clock Frequency
Clock Pulse Width, t

CONV

LOW

+ t

, t

ACQ

HIGH

)

J25--25-µs
K30--30-µs

(Note 2) 0.05 - 0.75 0.05 0.75 MHz

(Note 2) 100 - - 100 - ns
Aperture Delay, tDAPR (Note 2) - 35 50 - 70 ns
Clock to Data Ready Delay, tD1DRDY (Note 2) - 180 210 - 240 ns
Clock to Data Ready Delay, tD2DRDY (Note 2) - 180 220 - 250 ns
Start Removal Time, tRSTRT (Note 2) 75 30 - 75 - ns
Start Setup Time, tSUSTRT (Note 2) 85 60 - 30 - ns
Start Pulse Width, tWSTRT (Note 2) - 15 25 - 25 ns
Start to Data Ready Delay, tD3DRDY (Note 2) - 110 130 - 160 ns
Output Enable Delay, t
Output Disabled Delay, t

EN

DIS

(Note 2) - 65 75 - 80 ns

(Note 2) - 95 110 - 130 ns

POWER SUPPLY CHARACTERISTICS

Supply Current, IDD + I

AA

- 0.5 1 - 2.5 mA

NOTE:

2. Parameter guaranteed by design or characterization, not production tested.

6-1805