Intersil Corporation HI5762 Datasheet

HI5762

Data Sheet February 1999 File Number 4318.2

Dual 10-Bit, 60MSPS A/D Converter with
Internal Voltage Reference

The HI5762 is a monolithic, dual 10-bit, 60MSPS analog-to­digital converter fabricated in an advanced CMOS process.
It is designed for high speed applications where integration,
bandwidth and accuracy are essential. Built by combining
two cores of the HI5767 single channel 10-bit 60MSPS
analog-to-digital converter, the HI5762 reaches a new level
of multi-channel integration. The fully pipeline architecture
and an innovativeinputstageenable the HI5762 to accept a
variety of input configurations, single-ended or fully
differential. Only one external clock is necessary to drive
both converters and an internal band-gap voltage reference
is provided. This allows the system designer to realize an
increased level of system integration resulting in decreased
cost and power dissipation.

The HI5762 has excellent dynamic performance while
consuming only 650mW of power at 60MSPS. The A/D only
requires a single +5V power supply and encode clock. Data
output latches are provided which present valid data to the
output bus with a latency of 6 clock cycles.

For those customers needing dual channel 8-bit resolution,
please refer to the HI5662. For single channel 10-bit
applications, please refer to the HI5767.

Ordering Information

PART

NUMBER

HI5762/6IN -40 to 85 44 Ld MQFP Q44.10x10
HI5762EVAL2 25 Evaluation Platform

TEMP.

RANGE (oC) PACKAGE PKG. NO.

Features

• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .60MSPS

• 8.8 Bits at f

= 10MHz

IN

• Low Power at 60MSPS. . . . . . . . . . . . . . . . . . . . . 650mW

• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz

• Excellent Channel-to-Channel Isolation. . . . . . . . . >75dB

• On-Chip Sample and Hold Amplifiers

• Internal Band-Gap Voltage Reference . . . . . . . . . . . . 2.5V

• Fully Differential or Single-Ended Analog Inputs

• Single Supply Voltage Operation . . . . . . . . . . . . . . . . +5V

• TTL/CMOS Compatible Sampling Clock Input

• CMOS Compatible Digital Outputs. . . . . . . . . . . . 3.0/5.0V

• Offset Binary Digital Data Output Format

• Dual 10-Bit A/D Converters on a Monolithic Chip

Applications

• Wireless Local Loop

• PSK and QAM I&Q Demodulators

• Medical Imaging

• High Speed Data Acquisition

Pinout

HI5762 (MQFP)

TOP VIEW

IVDCI

IN-IIN+

GND

A

V

RIN

NC

ROUT

V

CC1

AV

IN+QIN-

Q

DC

QV

17

44 43 42 41 40

A

GND

AV

CC2

ID9
ID8
ID7
ID6
ID5

DV

CC3

D

GND

ID4
ID3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

1
2
3
4
5

6
7
8
9

10
11

12 13 14 15 16 17

ID2

ID1

ID0

39 38 37 36 35 34

CC1

DV

CLK

CC2

DV

GND

D

GND

D

QD0

2221201918

QD1

33
32
31
30
29

28
27
26
25
24
23

QD2

| Copyright © Intersil Corporation 1999

A

GND

AV
QD9
QD8
QD7
QD6
QD5
DV
D

GND

QD4
QD3

CC2

CC3

Functional Block Diagram

HI5762

I/QIN-

I/Q

BIAS

+

IN

S/H

STAGE 1

X2

2-BIT

FLASH

+

∑

-

STAGE 8

2-BIT

FLASH

+

∑

-

2-BIT

DAC

DIGITAL DELAY

AND

DIGITAL ERROR

CORRECTION

2-BIT

DAC

I/QV

DC

DV

CC3

I/QD9 (MSB)

I/QD8

I/QD7

I/QD6

I/QD5

I/QD4

I/QD3

I/QD2

I/QD1

I/QD0 (LSB)

V

REFOUT

V

REFIN

X2

REFERENCE

18

2-BIT

FLASH

STAGE 9

AV

CC1,2

AGND DV

CC1,2

DGND

CLOCK

I or Q CHANNEL

CLK

Typical Application Schematic

HI5762

HI5762

+

I

IN

IIN-

Q

+

IN

Q

-

IN

0.1µF

(42) I

IN

(44) IV
(43) IIN-

(36) Q
(34) QV
(35) QIN-

(40) V

RIN

(38) V

ROUT

(39) NC

+

DC

+

IN

DC

(LSB) ID0 (14)

ID1 (13)
ID2 (12)
ID3 (11)
ID4 (10)
ID5 (7)
ID6 (6)
ID7 (5)
ID8 (4)

(MSB) ID9 (3)

(LSB) QD0 (20)

QD1 (21)
QD2 (22)
QD3 (23)
QD4 (24)
QD5 (27)
QD6 (28)
QD7 (29)
QD8 (30)

(MSB) QD9 (31)

CLK (17)

DV

(8,26)

CC3

ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ID8
ID9

QD0
QD1
QD2
QD3
QD4
QD5
QD6
QD7
QD8
QD9

0.1µF10µF

+

CLOCK

+5V or +3V

+5V

10µF

(37) AV

CC1

(2,32) AV

+

0.1µF

AGND

BNC

CC2

(1,33,41) AGND

DGND

DV

(18)

CC2

DV

(16)

CC1

DGND (9,15,19,25)

10µF AND 0.1µF CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE

0.1µF10µF

+

+5V

19

Pin Descriptions

HI5762

PIN NO. NAME DESCRIPTION

1A
2AV

GND

CC2

Analog Ground

Analog Supply (+5.0V)
3 ID9 I-Channel, Data Bit 9 Output (MSB)
4 ID8 I-Channel, Data Bit 8 Output
5 ID7 I-Channel, Data Bit 7 Output
6 ID6 I-Channel Data Bit 6 Output
7 ID5 I-Channel, Data Bit 5 Output
8DV

CC3

Digital Output Supply

(+3.0V or +5.0V)
9D

GND

Digital Ground

10 ID4 I-Channel, Data Bit 4 Output
11 ID3 I-Channel, Data Bit 3 Output
12 ID2 I-Channel, Data Bit 2 Output
13 ID1 I-Channel, Data Bit 1 Output
14 ID0 I-Channel, Data Bit 0 Output (LSB)
15 D
16 DV

GND

CC1

Digital Ground

Digital Supply (+5.0V)

17 CLK Sample Clock Input
18 DV
19 D

CC2

GND

Digital Supply (+5.0V)

Digital Ground

20 QD0 Q-Channel, DataBit 0 Output (LSB)
21 QD1 Q-Channel, Data Bit 1 Output
22 QD2 Q-Channel, Data Bit 2 Output
23 QD3 Q-Channel, Data Bit 3 Output

PIN NO. NAME DESCRIPTION

24 QD4 Q-Channel, Data Bit 4 Output
25 DGND Digital Ground
26 DV

CC3

Digital Output Supply

(+3.0V or +5.0V)
27 QD5 Q-Channel, Data Bit 5 Output
28 QD6 Q-Channel, Data Bit 6 Output
29 QD7 Q-Channel, Data Bit 7 Output
30 QD8 Q-Channel, Data Bit 8 Output
31 QD9 Q-Channel, Data Bit 9 Output

(MSB)
32 AV
33 A
34 QV
35 Q
36 Q
37 AV
38 V

ROUT

CC2

GND

DC

IN-

IN+

CC1

Analog Supply (+5.0V)

Analog Ground

Q-Channel DC Bias Voltage Output

Q-Channel Negative Analog Input

Q-Channel Positive Analog Input

Analog Supply (+5.0V)

+2.5V Reference Voltage Output
39 NC No Connect
40 V
41 A
42 I
43 I
44 IV

RIN
GND
IN+

IN-

DC

+2.5V Reference Voltage Input
Analog Ground
I-Channel Positive Analog Input
I-Channel Negative Analog Input
I-Channel DC Bias Voltage Output

20

HI5762

Absolute Maximum Ratings T

Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .6V

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V

Digital I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DV

Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AV

=25oC Thermal Information

A

Thermal Resistance (Typical, Note 1) θJA (oC/W)

HI5762/6IN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

CC
CC

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

Operating Conditions

(Lead Tips Only)

Temperature Range

HI5762/6IN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications AV

= DV

CC1,2

= 10pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified

C

L

CC1,2

= +5.0V, DV

= +3.0V; V

CC3

= 2.50V; fS = 60MSPS at 50% Duty Cycle;

RIN

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ACCURACY

Resolution 10 - - Bits
Integral Linearity Error, INL f
Differential Linearity Error, DNL

(Guaranteed No Missing Codes)
Offset Error, V

OS

Full Scale Error, FSE f

= 10MHz - 2 - LSB

IN

f

= 10MHz - ±0.4 ±1.0 LSB

IN

fIN = DC -40 - +40 LSB

= DC - 4 - LSB

IN

DYNAMIC CHARACTERISTICS

Minimum Conversion Rate No Missing Codes - 1 - MSPS
Maximum Conversion Rate No Missing Codes 60 - - MSPS
Effective Number of Bits, ENOB f
Signal to Noise and Distortion Ratio, SINAD f

RMS Signal

--------------------------------------------------------------=

RMS Noise + Distortion

= 10MHz 8.4 8.8 - Bits

IN

= 10MHz - 54.7 - dB

IN

Signal to Noise Ratio, SNR fIN = 10MHz - 54.7 - dB

RMS Signal

-------------------------------=

RMS Noise

Total Harmonic Distortion, THD f
2nd Harmonic Distortion f
3rd Harmonic Distortion f
Spurious Free Dynamic Range, SFDR f
Intermodulation Distortion, IMD f

= 10MHz - -68 - dBc

IN

= 10MHz - -70 - dBc

IN

= 10MHz - -73 - dBc

IN

= 10MHz - 70 - dBc

IN

= 1MHz, f2 = 1.02MHz - 64 - dBc

1

I/Q Channel Crosstalk - -75 - dBc
I/Q Channel Offset Match - 10 - LSB
I/Q Channel Full Scale Error Match - 10 - LSB
Transient Response (Note 2) - 1 - Cycle
Over-Voltage Recovery 0.2V Overdrive (Note 2) - 1 - Cycle

ANALOG INPUT

Maximum Peak-to-Peak Differential Analog Input
Range (V

+ - VIN-)

IN

Maximum Peak-to-Peak Single-Ended

- ±0.5 - V

- 1.0 - V

Analog Input Range
Analog Input Resistance, R

IN+

or R

IN-

V

, V

= V

IN+

IN-

, DC - 1 - MΩ

REF

21