Datasheet HI5760 Datasheet (intersil)

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HI5760

Data Sheet March 30, 2005 FN4320.8

10-Bit, 125/60MSPS, High Speed D/A Converter

The HI5760 is a 10-bit, 125MSPS, high speed, low power, D/A converter which is implemented in an advanced CMOS process. Operating from a single +3V to +5V supply, the converter provides 20mA of full scale output current and includes edge-triggered CMOS input data latches. Low glitch energy and excellent frequency domain performance are achieved using a segmented current source architecture. For an equivalent performance dual version, see the HI5728.

This device complements the HI5X60 family of high speed converters offered by Intersil, which includes 8, 10, 12, and 14-bit devices.

Ordering Information

PART

NUMBER

HI5760BIB -40 to 85 28 Ld SOIC M28.3 125MHz HI5760BIBZ

(See Note) HI5760IA -40 to 85 28 Ld TSSOP M28.173 125MHz HI5760IAZ

(See Note) HI5760/6IB -40 to 85 28 Ld SOIC M28.3 60MHz HI5760/6IBZ

(See Note) HI5760EVAL1 25 Evaluation Platform 125MHz * Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

TEMP.

RANGE (

C) PACKAGE

-40 to 85 28 Ld SOIC

-40 to 85 28 Ld TSSOP

-40 to 85 28 Ld SOIC

(Pb-free)

PKG.

NO.

M28.3 125MHz

M28.173 125MHz

M28.3 60MHz

CLOCK SPEED

Features

• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .125MSPS

• Low Power . . . . . . . . . . . . . . . 165mW at 5V, 27mW at 3V

• Power Down Mode. . . . . . . . . . 23mW at 5V, 10mW at 3V

• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . .

±1 LSB

• Adjustable Full Scale Output Current. . . . . 2mA to 20mA

• SFDR to Nyquist at 5MHz Output . . . . . . . . . . . . . .68dBc

• Internal 1.2V Temperature Compensated Bandgap Voltage Reference

• Single Power Supply from +5V to +3V

• CMOS Compatible Inputs

• Excellent Spurious Free Dynamic Range

• Pb-Free Available (RoHS Compliant)

Applications

• Cable Modems

• Set Top Boxes

• Wireless Communications

• Direct Digital Frequency Synthesis

• Signal Reconstruction

• Test Instrumentation

• High Resolution Imaging Systems

• Arbitrary Waveform Generators

Pinout

HI5760 (SOIC, TSSOP)

TOP VIEW

D8 D7 D6 D5 D4 D3 D2 D1

NC NC NC NC

1 2 3 4 5 6 7 8

9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

CLK DV

DCOM NC AV

NC IOUTA IOUTB ACOM COMP1 FSADJ REFIO REFLO SLEEP

D9 (MSB)

D0 (LSB)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Typical Applications Circuit

HI5760

50Ω

FERRITE

BEAD

10µF

10µH

Functional Block Diagram

D9 D8

D7 D6 D5 D4 D3 D2 D1

0.1µF

(11-14, 25)

D9 (MSB) (1) D8 (2) D7 (3) D6 (4) D5 (5) D4 (6) D3 (7) D2 (8) D1 (9) D0 (LSB) (10)

CLK (28)

DCOM (26)

DVDD (27)

(15) SLEEP (16) REFLO

(17) REFIO

(18) FSADJ

(22) IOUTA

(21) IOUTB

(23) NC

(19) COMP1

(20) ACOM

(24) AV

DCOM

D/A OUT

10µH

ACOM

SET

+5V OR +3V (V

10µF

2kΩ

)

0.1µF

50Ω

0.1µF FERRITE

BEAD

0.1µF

(LSB) D0

(MSB) D9

CLK

LATCH

UPPER

5-BIT

DECODER

LATCH

INT/EXT

REFERENCE

SELECT

IOUTA IOUTB

SWITCH MATRIX

INT/EXT

VOLTAGE

REFERENCE

CASCODE CURRENT

SOURCE

SEGMENTS

GENERATION

5 LSBs

31 MSB

BIAS

COMP1

ACOM DVDDDCOM

FSADJ

REFLO

REFIO

SLEEP

HI5760

Absolute Maximum Ratings Thermal Information

Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V

Analog Supply Voltage AV

Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . -0.3V To + 0.3V

Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . DV

Internal Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . ±50µA

Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV

Analog Output Current (I

to ACOM . . . . . . . . . . . . . . . . . +5.5V

) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA

OUT

+ 0.3V

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

is measured with the component mounted on an evaluation PC board in free air.

1. θ

Thermal Resistance (Typical, Note 1) θ

(oC/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Maximum Junction Temperature

HI5760 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Maximum Storage Temperature Range . . . . . . . . . -65

C to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300

(SOIC - Lead Tips Only)

Electrical Specifications AV

= DVDD = +5V, V

= Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values

REF

HI5760

= -40oC TO 85oC

PARAMETER TEST CONDITIONS

UNITSMIN TYP MAX

SYSTEM PERFORMANCE

Resolution 10 - - Bits Integral Linearity Error, INL “Best Fit” Straight Line (Note 7) -1 ±0.5 +1 LSB Differential Linearity Error, DNL (Note 7) -0.5 ±0.25 +0.5 LSB Offset Error, I Offset Drift Coefficient (Note 7) - 0.1 - ppm

(Note 7) -0.025 +0.025 % FSR

FSR/

Full Scale Gain Error, FSE With External Reference (Notes 2, 7) -10 ±2+10% FSR

With Internal Reference (Notes 2, 7) -10 ±1+10% FSR

Full Scale Gain Drift With External Reference (Note 7) - ±50 - ppm

With Internal Reference (Note 7) - ±100 - ppm

Full Scale Output Current, I

2-20mA

FSR/

Output Voltage Compliance Range (Note 3) -0.3 - 1.25 V

DYNAMIC CHARACTERISTICS

Maximum Clock Rate, f Output Settling Time, (t

CLK

) 0.2% (±1 LSB, equivalent to 9 Bits) (Note 7) - 20 - ns

SETT

(Note 3) 125 - - MHz

0.1% (±1/2 LSB, equivalent to 10 Bits) (Note 7) - 35 - ns

Singlet Glitch Area (Peak Glitch) R

= 25Ω (Note 7) - 5 - pV•s

Output Rise Time Full Scale Step - 1.0 - ns Output Fall Time Full Scale Step - 1.5 - ns Output Capacitance -10- pF Output Noise IOUTFS = 20mA - 50 - pA/√Hz

IOUTFS = 2mA - 30 - pA/√Hz

HI5760

Electrical Specifications AV

= DVDD = +5V, V

= Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued)

REF

HI5760

= -40oC TO 85oC

PARAMETER TEST CONDITIONS

UNITSMIN TYP MAX

AC CHARACTERISTICS - HI5760BIB, HI5760IA - 125MHz

Spurious Free Dynamic Range, SFDR Within a Window

Total Harmonic Distortion (THD) to Nyquist

Spurious Free Dynamic Range, SFDR to Nyquist

= 125MSPS, f

CLK

= 100MSPS, f

CLK

= 60MSPS, f

CLK

= 50MSPS, f

CLK

= 50MSPS, f

CLK

= 100MSPS, f

CLK

= 50MSPS, f

CLK

= 50MSPS, f

CLK

= 125MSPS, f

CLK

= 125MSPS, f

CLK

= 100MSPS, f

CLK

= 100MSPS, f

CLK

= 100MSPS, f

CLK

= 100MSPS, f

CLK

= 60MSPS, f

CLK

= 50MSPS, f

CLK

= 50MSPS, f

CLK

= 50MSPS, f

CLK

= 50MSPS, f

CLK

= 32.9MHz, 10MHz Span (Notes 4, 7) - 75 - dBc

OUT

= 5.04MHz, 4MHz Span (Notes 4, 7) - 76 - dBc

OUT

= 10.1MHz, 10MHz Span (Notes 4, 7) - 75 - dBc

OUT

= 5.02MHz, 2MHz Span (Notes 4, 7) - 76 - dBc

OUT

= 1.00MHz, 2MHz Span (Notes 4, 7) - 78 - dBc

OUT

= 2.00MHz (Notes 4, 7) - 71 - dBc

OUT

= 2.00MHz (Notes 4, 7) - 71 - dBc

OUT

= 1.00MHz (Notes 4, 7) - 76 - dBc

OUT

= 32.9MHz, 62.5MHz Span (Notes 4, 7) - 54 - dBc

OUT

= 10.1MHz, 62.5MHz Span (Notes 4, 7) - 64 - dBc

OUT

= 40.4MHz, 50MHz Span (Notes 4, 7) - 52 - dBc

OUT

= 20.2MHz, 50MHz Span (Notes 4, 7) - 60 - dBc

OUT

= 5.04MHz, 50MHz Span (Notes 4, 7) - 68 - dBc

OUT

= 2.51MHz, 50MHz Span (Notes 4, 7) - 74 - dBc

OUT

= 10.1MHz, 30MHz Span (Notes 4, 7) - 63 - dBc

OUT

= 20.2MHz, 25MHz Span (Notes 4, 7) - 55 - dBc

OUT

= 5.02MHz, 25MHz Span (Notes 4, 7) - 68 - dBc

OUT

= 2.51MHz, 25MHz Span (Notes 4, 7) - 73 - dBc

OUT

= 1.00MHz, 25MHz Span (Notes 4, 7) - 73 - dBc

OUT

AC CHARACTERISTICS - HI5760/6IB, HI5760/6IA - 60MHz

Spurious Free Dynamic Range, SFDR Within a Window

Total Harmonic Distortion (THD) to Nyquist

Spurious Free Dynamic Range, SFDR to Nyquist

= 60MSPS, f

CLK

= 50MSPS, f

CLK

= 50MSPS, f

CLK

= 50MSPS, f

CLK

= 50MSPS, f

CLK

= 60MSPS, f

CLK

= 60MSPS, f

CLK

= 50MSPS, f

CLK

= 50MSPS, f

CLK

= 50MSPS, f

CLK

= 50MSPS, f

CLK

= 25MSPS, f

CLK

= 10.1MHz, 10MHz Span (Notes 4, 7) - 75 - dBc

OUT

= 5.02MHz, 2MHz Span (Notes 4, 7) - 76 - dBc

OUT

= 1.00MHz, 2MHz Span (Notes 4, 7) - 78 - dBc

OUT

= 2.00MHz (Notes 4, 7) - 71 - dBc

OUT

= 1.00MHz (Notes 4, 7) - 76 - dBc

OUT

= 20.2MHz, 30MHz Span (Notes 4, 7) - 56 - dBc

OUT

= 10.1MHz, 30MHz Span (Notes 4, 7) - 63 - dBc

OUT

= 20.2MHz, 25MHz Span (Notes 4, 7) - 55 - dBc

OUT

= 5.02MHz, 25MHz Span (Notes 4, 7) - 68 - dBc

OUT

= 2.51MHz, 25MHz Span (Notes 4, 7) - 73 - dBc

OUT

= 1.00MHz, 25MHz Span (Notes 4, 7) - 73 - dBc

OUT

= 5.02MHz, 25MHz Span (Notes 4, 7) - 71 - dBc

OUT

VOLTAGE REFERENCE

Internal Reference Voltage, V

FSADJ

Pin 18 Voltage with Internal Reference 1.04 1.16 1.28 V Internal Reference Voltage Drift - ±60 - ppm/ Internal Reference Output Current

-0.1- µA

Sink/Source Capability Reference Input Impedance -1-MΩ Reference Input Multiplying Bandwidth (Note 7) - 1.4 - MHz

HI5760

Electrical Specifications AV

= DVDD = +5V, V

= Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued)

REF

HI5760

= -40oC TO 85oC

PARAMETER TEST CONDITIONS

UNITSMIN TYP MAX

DIGITAL INPUTS D9-D0, CLK

Input Logic High Voltage with 5V Supply, V

Input Logic High Voltage with 3V Supply, V

Input Logic Low Voltage with 5V Supply, V

Input Logic Low Voltage with 3V Supply, V

Input Logic Current, I Input Logic Current, I

IH IL

Digital Input Capacitance, C

(Note 3) 3.5 5 - V

(Note 3) 2.1 3 - V

(Note 3) - 0 1.3 V

(Note 3) - 0 0.9 V

-10 - +10 µA

-5-pF

TIMING CHARACTERISTICS

Data Setup Time, t Data Hold Time, t

HLD

Propagation Delay Time, t CLK Pulse Width, t

PW1

, t

PW2

See Figure 41 (Note 3) 3 - - ns

See Figure 41 - 1 - ns

See Figure 41 (Note 3) 4 - - ns

POWER SUPPLY CHARACTERISTICS

Power Supply (Note 8) 2.7 5.0 5.5 V

Analog Supply Current (I

) (5V or 3V, IOUTFS = 20mA) - 23 30 mA

AVDD

(5V or 3V, IOUTFS = 2mA) - 4 - mA Digital Supply Current (I

) (5V, IOUTFS = Don’t Care) (Note 5) - 3 5 mA

DVDD

(3V, IOUTFS = Don’t Care) (Note 5) - 1.5 - mA Supply Current (I

) Sleep Mode (5V or 3V, IOUTFS = Don’t Care) - 1.6 3 mA

AVDD

Power Dissipation (5V, IOUTFS = 20mA) (Note 6) - 165 - mW

(5V, IOUTFS = 2mA) (Note 6) - 70 - mW

(5V, IOUTFS = 20mA) (Note 9) - 150 - mW

(3.3V, IOUTFS = 20mA) (Note 9) - 75 - mW

(3V, IOUTFS = 20mA) (Note 6) - 85 - mW

(3V, IOUTFS = 20mA) (Note 9) - 67 - mW

(3V, IOUTFS = 2mA) (Note 6) - 27 - mW Power Supply Rejection Single Supply (Note 7) -0.2 - +0.2 % FSR/V

NOTES:

2. Gain Error measured as the error in the ratio between the full scale output current and the current through R ratio should be 31.969.

(typically 625µA). Ideally the

SET

3. Parameter guaranteed by design or characterization and not production tested.

4. Spectral measurements made with differential coupled transformer.

5. Measured with the clock at 50MSPS and the output frequency at 1MHz.

6. Measured with the clock at 100MSPS and the output frequency at 40MHz.

7. See ‘Definition of Specifications’.

8. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DV do not have to be equal.

and AVDD

9. Measured with the clock at 60MSPS and the output frequency at 10MHz.

HI5760

Typical Performance Curves, 5V Power Supply

SFDR (dBc)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

-12dBFS

OUTPUT FREQUENCY (MHz)

FIGURE 1. SFDR vs f

0dBFS

SFDR (dBc)

-12dBFS

0dBFS

OUT

-6dBFS

, CLOCK = 5MSPS FIGURE 2. SFDR vs f

SFDR (dBc)

12345678910

-12dBFS

SFDR (dBc)

-12dBFS

OUTPUT FREQUENCY (MHz)

, CLOCK = 25MSPS

OUT

-6dBFS

0dBFS

-6dBFS

0dBFS

02468101214161820

OUTPUT FREQUENCY (MHz)

FIGURE 3. SFDR vs f

-12dBFS

SFDR (dBc)

0 5 10 15 20 25 30 35 40 45 50

OUTPUT FREQUENCY (MHz)

FIGURE 5. SFDR vs f

, CLOCK = 50MSPS FIGURE 4. SFDR vs f

OUT

6dBFS

0dBFS

, CLOCK = 125MSPS FIGURE 6. SFDR vs AMPLITUDE, f

OUT

0 5 10 15 20 25 30 35 40 45

OUTPUT FREQUENCY (MHz)

, CLOCK = 100MSPS

OUT

SFDR (dBc)

-25 -20 -15 -10 -5 0

125MSPS

AMPLITUDE (dBFS)

25MSPS

100MSPS

CLK/fOUT

50MSPS

= 10

HI5760

Typical Performance Curves, 5V Power Supply (Continued)

SFDR (dBc)

-25 -20 -15 -10 -5 0 AMPLITUDE (dBFS)

100MSPS

FIGURE 7. SFDR vs AMPLITUDE, f

SFDR (dBc)

2 4 6 8 10 12 14 16 18 20

(mA)

OUT

25MSPS

125MSPS

CLK/fOUT

2.5MHz

10MHz

20MHz

50MSPS

= 5 FIGURE 8. SFDR vs AMPLITUDE OF TWO TONES, f

40MHz

25MSPS

SFDR (dBc)

-25 -20 -15 -10 -5 0

AMPLITUDE (TOTAL PEAK POWER OF COMBINED TONES) (dBFS)

(3.38/3.63MHz)

50MSPS

(6.75/7.25MHz)

100MSPS

(13.5/14.5MHz)

125MSPS

(16.9/18.1MHz)

CLK/fOUT

SFDR (dBc)

0 5 10 15 20 25 30 35 40

-6dBFS DIFF 0dBFS DIFF

-6dBFS SINGLE

0dBFS SINGLE

OUTPUT FREQUENCY (MHz)

= 7

FIGURE 9. SFDR vs I

SFDR (dBc)

-40-200 20406080 TEMPERATURE (

, CLOCK = 100MSPS FIGURE 10. DIFFERENTIAL vs SINGLE-ENDED,

OUT

2.5MHz

10.1MHz

40.4MHz

-10

-20

-30

-40

-50

-60

-70

AMP (dB)

Amp (dB)

-80

-90

-100

-110

CLOCK = 100MSPS

Amplitude = 0dBFS

14dB EXTERNAL ANALYZER ATTENUATION

14dB External Analyzer Attenuation

0 5MHz/DIV.. 50

5MHz/DIV.

Frequency (MHz)

FREQUENCY (MHz)

CLK

= 100MSPS

OUT

Fout = 9.95MHz

AMPLITUDE = 0dBFS

SFDR = 64dBc

FIGURE 11. SFDR vs TEMPERATURE, CLOCK = 100MSPS FIGURE 12. SINGLE TONE SFDR

= 100MSPS

= 9.95MHz

SFDR = 64dBc

HI5760

Typical Performance Curves, 5V Power Supply (Continued)

-20

Fclk = 100MSPS

= 100MSPS

-30

-40

-50

-60

-70

AMP (dB)

Amp (dB)

-80

-90

-100

-110

-110 0 5MHz/DIV. 50

Combined Peak Amplitude = 0dBFS

14dB External Analyzer Attenuation

ANALYZER ATTENUATION

5MHz/DIV.

Frequency (MHz)

FREQUENCY (MHz)

CLK

Fout = 13.5/14.5MHz

= 13.5/14.5MHz

OUT

COMBINED PEAK

MTPR = 62.9dBc

AMPLITUDE = 0dBFS

SFDR = 62.9dBc

14dB EXTERNAL

-10

-20

-30

-40

-50

-60

AMP (dB)

-70

-80

-90

-100

0.5

OUT

1.45MHz/DIV.

FIGURE 13. TWO TONE, CLOCK = 100MSPS FIGURE 14. FOUR-TONE, CLOCK = 100MSPS

-20

-30

-40

-50

-60

-70

AMP (dB)

-80

-90

-100

-110

0.5

= 100MSPS

= 2.6,3.2,3.8,4.4,5.6,6.2,6.8MHz

OUT

SFDR = 67dBc (IN A WINDOW)

1.95MHz/DIV. 20

FREQUENCY (MHz)

CLK

COMBINED PEAK

AMPLITUDE = 0dBFS

-10

-20

-30

-40

-50

-60

AMP (dB)

-70

-80

-90

-100

0.5 950kHz/DIV. 10 FREQUENCY (MHz)

OUT

= 100MSPS

CLK

= 3.8,4.4,5.6,6.2MHz

COMBINED PEAK

AMPLITUDE = 0dBFS

SFDR = 71.4dBc

(IN A WINDOW)

= 50MSPS

CLK

= 1.9,2.2,2.8,3.1MHz

COMBINED PEAK

AMPLITUDE = 0dBFS

SFDR = 73.6dBc

(IN A WINDOW)

FIGURE 15. EIGHT-TONE, CLOCK = 100MSPS FIGURE 16. FOUR-TONE, CLOCK = 50MSPS

0.4

0.2

LSB

-0.2

-0.4

0 200 400 600 800 1000

CODE

0.4

0.2

LSB

-0.2

-0.4

0 200 400 600 800 1000

CODE

FIGURE 17. DIFFERENTIAL NONLINEARITY FIGURE 18. INTEGRAL NONLINEARITY

HI5760

Typical Performance Curves, 5V Power Supply (Continued)

160 155 150 145 140 135 130 125

POWER (mW)

120 115 110 105

0 20 40 60 80 100 120

CLOCK RATE (MSPS)

FIGURE 19. POWER vs CLOCK RATE, f

Typical Performance Curves, 3V Power Supply

SFDR (dBc)

-12dBFS

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

OUTPUT FREQUENCY (MHz)

FIGURE 20. SFDR vs f

-6dBFS

-12dBFS

SFDR (dBc)

0dBFS

, CLOCK = 5MSPS FIGURE 21. SFDR vs f

OUT

0dBFS

-6dBFS

CLK/fOUT

= 10, I

SFDR (dBc)

1 2 3 4 5 6 7 8 9 10

-12dBFS

SFDR (dBc)

= 20mA

OUT

0dBFS

-12dBFS

OUTPUT FREQUENCY (MHz)

0dBFS

-6dBFS

, CLOCK = 25MSPS

OUT

0 2 4 6 8 10 12 14 16 18 20

OUTPUT FREQUENCY (MHz)

FIGURE 22. SFDR vs f

, CLOCK = 50MSPS FIGURE 23. SFDR vs f

OUT

0 5 10 15 20 25 30 35 40 45

OUTPUT FREQUENCY (MHz)

, CLOCK = 100MSPS

OUT

HI5760

Typical Performance Curves, 3V Power Supply (Continued)

SFDR (dBc)

0 5 10 15 20 25 30 35 40 45 50

SFDR (dBc)

-25 -20 -15 -10 -5 0

0dBFS

-6dBFS

-12dBFS

OUTPUT FREQUENCY (MHz)

FIGURE 24. SFDR vs f

5MSPS

AMPLITUDE (dBFS)

, CLOCK = 125MSPS FIGURE 25. SFDR vs AMPLITUDE, f

OUT

25MSPS

50MSPS

100MSPS

125MSPS

SFDR (dBc)

-25 -20 -15 -10 -5 0 AMPLITUDE (dBFS)

SFDR (dBc)

25MSPS

(3.38/3.63MHz)

125MSPS

(16.9/18.1MHz)

-25 -20 -15 -10 -5 0 AMPLITUDE (dBFS)

25MSPS

CLK/fOUT

100MSPS

(13.5/14.5MHz)

50MSPS

100MSPS

125MSPS

= 10

50MSPS

(6.75/7.25MHz)

FIGURE 26. SFDR vs AMPLITUDE, f

SFDR (dBc)

2 4 6 8 10 12 14 16 18 20

(MA)

OUT

FIGURE 28. SFDR vs I

, CLOCK = 100MSPS FIGU RE 29. DIFFERENTIAL vs SINGLE-ENDED,

OUT

CLK/fOUT

2.5MHz

10MHz

20MHz

40MHz

= 5

FIGURE 27. SFDR vs AMPLITUDE OF TWO TONES, f

SFDR (dBc)

0dBFS DIFF

-6dBFS SINGLE

0 5 10 15 20 25 30 35 40

OUTPUT FREQUENCY (MHz)

-6dBFS DIFF

0dBFS SINGLE

CLOCK = 100MSPS

CLK/fOUT

= 7

HI5760

Typical Performance Curves, 3V Power Supply (Continued)

SFDR (dBc)

-40 -20 0 20 40 60 80 TEMPERATURE (oC)

2.5MHz

10.1MHz

40.4MHz

-10

-20

-30

-40

-50

-60

AMP (dB)

-70

-80

-90

-100

-110 0 5MHz/DIV. 50

FREQUENCY (MHz)

ANALYZER ATTENUATION

CLK

OUT

AMPLITUDE = 0dBFS

SFDR = 63dBc

14dB EXTERNAL

FIGURE 30. SFDR vs TEMPERATURE, CLOCK = 100MSPS FIGURE 31. SINGLE TONE SFDR

-20 f

= 100MSPS

-30

-40

-50

-60

-70

AMP (dB)

-80

-90

-100

-110 0 5MHz/DIV. 50

FREQUENCY (MHz)

ANALYZER ATTENUATION

CLK

= 13.5/14.5MHz

OUT

COMBINED PEAK

AMPLITUDE = 0dBFS

SFDR = 61.5dBc

14dB EXTERNAL

-10

-20

-30

-40

-50

-60

AMP (dB)

-70

-80

-90

-100

0.5 1.45MHz/DIV. 15 FREQUENCY (MHz)

CLK

= 3.8,4.4,5.6,6.2MHz

OUT

COMBINED PEAK

AMPLITUDE = 0dBFS

SFDR = 70.6dBc

(IN A WINDOW)

= 100MSPS

= 9.95MHz

= 100MSPS

FIGURE 32. TWO-TONE, CLOCK = 100MSPS FIGURE 33. FOUR-TONE, CLOCK = 100MSPS

-20

-30

-40

-50

-60

-70

AMP (dB)

-80

-90

-100

-110

0.5 1.95MHz/DIV. 20 FREQUENCY (MHz)

= 100MSPS

CLK

= 2.6, 3.2, 3.8, 4.4,

OUT

5.6, 6.2, 6.8MHz

COMBINED PEAK

AMPLITUDE = 0dBFS

SFDR = 67.4dBc

(IN A WINDOW)

-10

-20

-30

-40

-50

-60

AMP (dB)

-70

-80

-90

-100 0 950kHz/DIV. 10

FREQUENCY (MHz)

= 1.9, 2.2, 2.8, 3.1MHz

OUT

AMPLITUDE = 0dBFS

FIGURE 34. EIGHT-TONE, CLOCK = 100MSPS FIGURE 35. FOUR-TONE, CLOCK = 50MSPS

= 50MSPS

CLK

COMBINED PEAK

SFDR = 74.2dBc

(IN A WINDOW)

HI5760

Typical Performance Curves, 3V Power Supply (Continued)

0.4

0.2

LSB

-0.2

-0.4

0 200 400 600 800 1000

CODE

0.4

0.2

LSB

-0.2

-0.4

0 200 400 600 800 1000

CODE

FIGURE 36. DIFFERENTIAL NONLINEARITY FIGURE 37. INTEGRAL NONLINEARITY

POWER (mW)

0 20 40 60 80 100 120

CLOCK RATE (MSPS)

FIGURE 38. POWER vs CLOCK RATE, f

CLK/fOUT

= 10, I

OUT

= 20mA

Timing Diagrams

HI5760

CLK

D9-D0

OUT

SETT

50%

/2 LSB ERROR BAND

FIGURE 39. OUTPUT SETTLING TIME DIAGRAM

CLK

PW1

PW2

GLITCH AREA =

HEIGHT (H)

WIDTH (W)

/2 (H x W)

t(ps)

FIGURE 40. PEAK GLITCH AREA (SINGLET) MEASUREMENT

METHOD

50%

D9-D0

OUT

HLD

SETT

HLD

SETT

HLD

SETT

FIGURE 41. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MIN IMUM PULSE WIDTH DIAGRAM

HI5760

Definition of Specifications

Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve.

Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity.

Output Settling Time, is the time required for the output voltage to settle to within a specified error band measured from the beginning of the output transition. In the case of the HI5760, the measurement was done by switching from code 0 to 256, or quarter scale. Termination impedance was 25 due to the parallel resistance of the output 50 oscilloscope’s 50

Ω input. This also aids the ability to resolve

Ω and the

the specified error band without overdriving the oscilloscope. Singlet Glitch Area, is the switching transient appearing on

the output during a code transition. It is measured as the area under the overshoot portion of the curve and is expressed as a Volt-Time specification.

Full Scale Gain Error, is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through R

SET

Full Scale Gain Drift, is measured by setting the data inputs to all ones and measuring the output voltage through a known resistance as the temperature is varied from T T

. It is defined as the maximum deviation from the value

MAX

measured at room temperature to the value measured at either T

MIN

or T

. The units are ppm of FSR (full scale

MAX

range) per degree C. Total Harmonic Distortion, THD, is the ratio of the DAC

output fundamental to the RMS sum of the first five harmonics.

Spurious Free Dynamic Range, SFDR, is the amplitude difference from the fundamental to the largest harmonically or non-harmonically related spur within the specified window.

Output Voltage Compliance Range, is the voltage limit imposed on the output. The output impedance load should be chosen such that the voltage developed does not violate the compliance range.

Offset Error, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance. Offset error is defined as the maximum deviation of the output current from a value of 0mA.

Offset Drift, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance as the temperature is varied from T

MIN

to T It is defined as the maximum deviation from the value measured at room temperature to the value measured at

MIN

MAX

Ω

either T

MIN

or T

. The units are ppm of FSR (full scale

MAX

range) per degree C. Power Supply Rejection, is measured using a single power

supply. Its nominal +5V is varied

±10% and the change in

the DAC full scale output is noted. Reference Input Multiplying Bandwidth, is defined as the

3dB bandwidth of the voltage reference input. It is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. The frequency is increased until the amplitude of the output waveform is

0.707 of its original value. Internal Reference Voltage Drift, is defined as the

maximum deviation from the value measured at room temperature to the value measured at either Tmin or Tmax. The units are ppm per degree C.

Detailed Description

The HI5760 is a 10-bit, current out, CMOS, digital to analog converter. Its maximum update rate is 125MSPS and can be powered by either single or dual power supplies in the recommended range of +3V to +5V. It consumes less than 165mW of power when using a +5V supply with the data switching at 100MSPS. The architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. The five MSBs are represented by 31 major current sources of equivalent current. The five LSBs are comprised of binary weighted current sources. Consider an input waveform to the converter which is ramped through all the codes from 0 to 1023. The five LSB current sources would begin to count up. When they reached the all high state (decimal value of

31) and needed to count to the next code, they would all turn off and the first major current source would turn on. To continue counting upward, the 5 LSBs would count up another 31 codes, and then the next major current source would turn on and the five LSBs would all turn off. The process of the single, equivalent, major current source turning on and the five LSBs turning off each time the converter reaches another 31 codes greatly reduces the glitch at any one switching point. In previous architectures that contained all binary weighted current sources or a binary weighted resistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worst-case transition points such as mid-scale and quarter scale transitions. By greatly reducing the amount of current switching at certain ‘major’ transitions, the overall glitch of the converter is dramatically reduced, improving settling times and transient problems.

HI5760

Digital Inputs and Termination

The HI5760 digital inputs are guaranteed to CMOS levels. However, TTL compatibility can be achieved by lowering the supply voltage to 3V due to the digital threshold of the input buffer being approximately half of the supply voltage. The internal register is updated on the rising edge of the clock. To minimize reflections, proper termination should be implemented. If the lines driving the clock and the digital inputs are 50Ω lines, then 50Ω termination resistors should be placed as close to the converter inputs as possible to the digital ground plane (if separate grounds are used).

Ground Plane(s)

If separate digital and analog ground planes are used, then all of the digital functions of the device and their corresponding components should be over the digital ground plane and terminated to the digital ground plane. The same is true for the analog components and the analog ground plane. The converter will function properly with a single ground plane, as the Evaluation Board is configured in this matter. Refer to the Application Note on the HI5760 Evaluation Board for further discussion of the ground plane(s) upon availability.

Noise Reduction

To minimize power supply noise, 0.1µF capacitors should be placed as close as possible to the converter’s power supply pins, AV

and DVDD. Also, should the layout be designed

using separate digital and analog ground planes, these capacitors should be terminated to the digital ground for DV

and to the analog ground for AVDD. Additional filtering

of the power supplies on the board is recommended. See the Application Note on the HI5760 Evaluation Board for more information upon availability.

Voltage Reference

The internal voltage reference of the device has a nominal value of +1.2V with a ±60 ppm / full temperature range of the converter. It is recommended that a 0.1µF capacitor be placed as close as possible to the REFIO pin, connected to the analog ground. The REFLO pin (16) selects the reference. The internal reference can be selected if pin 16 is tied low (ground). If an external reference is desired, then pin 16 should be tied high (to the analog supply voltage) and the external reference driven into REFIO, pin 17. The full scale output current of the converter is a function of the voltage reference used and the value of R

SET

. I

should be within the 2mA to 20mA

OUT

range, through operation below 2mA is possible, with performance degradation.

If the internal reference is used, V approximately 1.16V (pin 18). If an external reference is used, V I

OUT

will equal the external reference. The calculation for

FSADJ

(Full Scale) is: (Full Scale) = (V

FSADJ/RSET

C drift coefficient over the

will equal

FSADJ

)x 32

If the full scale output current is set to 20mA by using the internal voltage reference (1.16V) and a 1.86kΩ R

SET

resistor, then the input coding to output current will resemble the following:

TABLE 1. INPUT CODING vs OUTPUT CURRENT

INPUT CODE (D9-D0) IOUTA (mA) IOUTB (mA)

11111 11111 20 0 10000 00000 10 10 00000 00000 0 20

Outputs

IOUTA and IOUTB are complementary current outputs. The sum of the two currents is always equal to the full scale output current minus one LSB. If single ended use is desired, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be either grounded or equally terminated. The voltage developed at the output must not violate the output voltage compliance range of -0.3V to 1.25V. R chosen so that the desired output voltage is produced in conjunction with the output full scale current, whi c h is described above in the ‘Reference’ section. If a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. The output voltage equation is:

OUT

= I

OUT

X R

LOAD

These outputs can be used in a differential-to-single-ended arrangement to achieve better harmonic rejection. The SFDR measurements in this data sheet were performed with a 1:1 transformer on the output of the DAC (see Figure 1). With the center tap grounded, the output swing of pins 21 and 22 will be biased at zero volts. It is important to note here that the negative voltage output compliance range limit is -300mV, imposing a maximum of 600mV with this configuration. The loading as shown in Figure 1 will result in a 500mV signal at the output of the transformer if the full scale output current of the DAC is set to 20mA.

HI5760

OUT

PIN 21 PIN 22

= 2 x I

IOUTB

IOUTA

x REQ, where REQ is ~12.5Ω

OUT

50Ω

100Ω

50Ω

FIGURE 42.

LOAD

OUT

should be

amplitude

P-P

= (2 x I

OUT

50Ω

x REQ)V

HI5760

Pin Descriptions

PIN NO. PIN NAME PIN DESCRIPTION

1-10 D9 (MSB) Through

D0 (LSB)

11-14 NC No Connect. Recommend ground.

15 SLEEP Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep

16 REFLO Connect to analog ground to enable internal 1.2V reference or connect to AV

17 REFIO Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is

18 FSADJ Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output

19 COMP1 For use in reducing bandwidth/noise. Recommended: connect 0.1µF to AV 20 ACOM Analog Ground. 21 IOUTB The complimentary current output of the device. Full scale output current is achieved when all input bits

22 IOUTA Current output of the device. Full scale output current is achieved when all input bits are set to binary 1. 23 NC Internally connected to ACOM via a resistor. Recommend leave disconnected. Adding a capacitor to

24 AV 25 NC No Connect. (For upward compatibility to 12 and 14b devices, pin 25 needs to be grounded to ACOM.)

Digital Data Bit 9 (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit).

pin has internal 20µA active pulldown current.

to disable internal

reference.

enabled. Use 0.1µF cap to ground when internal reference is enabled.

Current = 32 x V

are set to binary 0.

ACOM for upward compatibility is valid. Grounding to ACOM is valid. (For upward compatibility to 12-bit and 14-bit devices, pin 23 needs the ability to have a 0.1µF capacitor to ACOM.)

Analog Supply (+3V to +5V).

FSADJ/RSET

26 DCOM Digital Ground. 27 DV 28 CLK Input for clock. Positive edge of clock latches data.

Digital Supply (+3V to +5V).

Small Outline Plastic Packages (SOIC)

HI5760

INDEX AREA

123

-A-

-B-

SEATING PLANE

-C-

0.25(0.010) BM M

h x 45

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.

0.10(0.004)

M28.3 (JEDEC MS-013-AE ISSUE C)

28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 D 0.6969 0.7125 17.70 18.10 3

E 0.2914 0.2992 7.40 7.60 4

e 0.05 BSC 1.27 BSC H 0.394 0.419 10.00 10.65 -

h 0.01 0.029 0.25 0.75 5

L 0.016 0.050 0.40 1.27 6 N28 287

Rev. 0 12/93

NOTESMIN MA X MIN MAX

HI5760

Thin Shrink Small Outline Plastic Packages (TSSOP)

INDEX AREA

123

-A-

0.05(0.002)

SEATING PLANE

0.10(0.004) C AM BS

-B-

-C-

0.25(0.010) BM M

0.10(0.004)

GAUGE

PLANE

0.25

0.010

NOTES:

1. These package dimensions are within allowable dimensions of JEDEC MO-153-AE, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)

M28.173

28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.047 - 1.20 A1 0.002 0.006 0.05 0.15 A2 0.031 0.051 0.80 1.05 -

b 0.0075 0.0118 0.19 0.30 9

c 0.0035 0.0079 0.09 0.20 -

D 0.378 0.386 9.60 9.80 3 E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.0177 0.0295 0.45 0.75 6

N28 287

Rev. 0 6/98

NOTESMIN MAX MIN MAX

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Datasheet HI5760 Datasheet (intersil)

Specifications and Main Features

Frequently Asked Questions

User Manual