Complete, 12-Bit A/D Converters with
Microprocessor Interface
The HI-X74(A) is a complete 12-bit, Analog-to-Digital
Converter, including a +10V reference clock, three-state
outputs and a digital interface for microprocessor control.
Successive approximation conversion is performed by two
monolithic dice housed in a 28 lead package. The bipolar
analog die features the Intersil Dielectric Isolation process,
which provides enhanced AC performance and freedom
from latch-up.
Custom design of each IC (bipolar analog and CMOS digital)
has yielded improved performance over existing versions of
this converter. The voltage comparator features high PSRR
plus a high speed current-mode latch, and provides precise
decisions down to 0.1 LSB of input overdrive. More than 2X
reduction in noise has been achieved by using current
instead of voltage for transmission of all signals between the
analog and digital ICs. Also, the clock oscillator is current
controlled for excellent stability over temperature.
The HI-X74(A) offers standard unipolar and bipolar input
ranges, laser trimmed for specified linearity, gain and offset
accuracy. The low noise buried zener reference circuit is
trimmed for minimum temperature coefficient.
Power requirements are +5V and ±12V to ±15V, with typical
dissipation of 385mW (HI-574A, HI-674A) at 12V.
FN3096.6
Features
• Complete 12-Bit A/D Converter with Reference and Clock
• Full 8-Bit, 12-Bit or 16-Bit Microprocessor Bus Interface
• Military and Industrial Data Acquisition Systems
• Electronic Test and Scientific Instrumentation
• Process Control Systems
Pinout
+5V SUPPLY, V
DATA MODE SEL, 12/8
BYTE ADDR/SHORT
READ/CONVERT, R/C
CHIP ENABLE, CE
+12V/+15V SUPPLY, V
+10V REF, REF OUT
REFERENCE INPUT
-12V/-15V SUPPLY, V
BIPOLAR OFFSET
LOGIC
CHIP SEL, CS
CYCLE, A
ANALOG
COMMON, AC
BIP OFF
10V INPUT
20V INPUT
HI-574A, HI-674A
(28 LD PDIP, SBDIP)
TOP VIEW
1
2
3
4
O
5
6
7
CC
8
9
10
11
EE
12
13
14
28
STATUS, STS
27
DB11
26
DB10
25
DB9
24
DB8
23
DB7
22
DB6
21
DB5
20
DB4
19
DB3
18
DB2
17
DB1
16
DB0
DIG COMMON,
15
DC
MSB
DIGITAL
DATA
OUTPUTS
LSB
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HI-574A, HI-674A
Ordering Information
TEMPERATURE RANGE
PART NUMBERPART MARKINGINL
HI3-574AJN-5HI3-574AJN-5±1.0 LSB0 to +7528 Ld PDIPE28.6
HI3-574AJN-5Z (Notes 1, 3) HI3-574AJN-5Z±1.0 LSB0 to +7528 Ld PDIP (Pb-Free)E28.6
HI3-574AKN-5HI3-574AKN-5±0.5 LSB0 to +7528 Ld PDIPE28.6
HI3-574AKN-5Z (Notes 1, 3) HI3-574AKN-5Z±0.5 LSB0 to +7528 Ld PDIP (Pb-Free)E28.6
HI1-574AJD-5 (Note 2)HI1-574AJD -5±1.0 LSB0 to +7528 Ld SBDIP (Pb-Free)D28.6
HI1-574AKD-5 (Note 2)HI1-574AKD -5±0.5 LSB0 to +7528 Ld SBDIP (Pb-Free)D28.6
HI1-574ASD-2 (Note 2)HI1-574ASD -2±1.0 LSB-55 to +12528 Ld SBDIP (Pb-Free)D28.6
HI1-574ATD-2 (Note 2)HI1- 574ATD-2±0.5 LSB-55 to +12528 Ld SBDIP (Pb-Free)D28.6
HI3-674AJN-5HI3-674AJN-5±1.0 LSB0 to +7528 Ld PDIPE28.6
HI3-674AJN-5Z (Notes 1, 3) HI3-674AJN-5Z±1.0 LSB0 to +7528 Ld PDIP (Pb-Free)E28.6
HI3-674AKN-5HI3-674AKN-5±0.5 LSB0 to +7528 Ld PDIPE28.6
HI3-674AKN-5Z (Notes 1, 3) HI3-674AKN-5Z±0.5 LSB0 to +7528 Ld PDIP (Pb-Free)E28.6
HI1-674AKD-5 (Note 2)HI1-674AKD -5±0.5 LSB0 to +7528 Ld SBDIP (Pb-Free)D28.6
HI1-674ATD/883 (Note 2)HI1-674ATD /883±0.5 LSB-55 to +12528 Ld SBDIP (Pb-Free)D28.6
NOTES:
1. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
2. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
(°C)PACKAGE
PKG.
DWG. #
2
FN3096.6
August 7, 2008
Functional Block Diagram
HI-574A, HI-674A
BIT OUTPUTS
MSBLSB
12/8
CS
A
O
R/C
CE
IN
V
REF
V
OUT
REF
CONTROL
LOGIC
OSCILLATOR
DIGITAL CHIP
ANALOG CHIP
+10V
REF
THREE-STATE BUFFERS AND CONTROL
POWER-UP RESET
CLK
12 BITS
10k
+
-
NIBBLE B (NOTE)NIBBLE C (NOTE)NIBBLE A (NOTE)
V
LOGIC
12 BITS
SAR
STROBE
COMP
DAC
5k
10k
5k
5k
+
-
2.5k
DIGITAL
COMMON
STS
V
CC
V
EE
ANALOG
COMMON
NOTE: “Nibble” is a 4-bit digital word.
BIP
OFF
20V
INPUT
10V
INPUT
3
FN3096.6
August 7, 2008
HI-574A, HI-674A
Absolute Maximum RatingsThermal Information
Supply Voltage
V
to Digital Common . . . . . . . . . . . . . . . . . . . . . . 0V to +16.5V
CC
V
to Digital Common . . . . . . . . . . . . . . . . . . . . . . .0V to -16.5V
EE
V
to Digital Common . . . . . . . . . . . . . . . . . . . . . .0V to +7V
LOGIC
Analog Common to Digital Common . . . . . . . . . . . . . . . . . . . .±1V
Control Inputs
(CE, CS
, AO, 12/8, R/C) to Digital Common . . -0.5V to V
Analog Inputs
LOGIC
+0.5V
(REFIN, BIPOFF, 10VIN) to Analog Common . . . . . . . . . . ±16.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
DC and Transfer Accuracy Specifications Typical at +25°C with V
= +15V or +12V, V
CC
= +5V, VEE = -15V or -12V;
LOGIC
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not
production tested.
TEMPERATURE RANGE
-5 (0°C to +75°C)
PARAMETER
UNITSJ SUFFIXK SUFFIX
DYNAMIC CHARACTERISTICS
Resolution (Max)1212Bits
Linearity Error
1
+25°C (Max)±1±
0°C to +75°C (Max)±1±
/
2
1
/
2
Max Resolution For Which No Missing Codes Is Guaranteed
+25°C1212Bits
T
MIN
to T
MAX
1112Bits
Unipolar Offset (Max)
Adjustable to Zero±2±1.5LSB
Bipolar Offset (Max)
V
= 0V (Adjustable to Zero)±4±4LSB
IN
= -10V±0.15±0.1% of FS
V
IN
Full Scale Calibration Error
+25°C (Max), With Fixed 50Ω Resistor From REF OUT To REF IN
±0.25±0.25% of FS
(Adjustable to Zero)
T
T
MIN
MIN
to T
to T
(No Adjustment At +25°C)±0.475±0.375% of FS
MAX
(With Adjustment To Zero +25°C)±0.22±0.12% of FS
MAX
LSB
LSB
4
FN3096.6
August 7, 2008
HI-574A, HI-674A
DC and Transfer Accuracy Specifications Typical at +25°C with V
= +15V or +12V, V
CC
= +5V, VEE = -15V or -12V;
LOGIC
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not
production tested. (Continued)
TEMPERATURE RANGE
-5 (0°C to +75°C)
PARAMETER
Temperature Coefficients
Guaranteed Max Change, T
MIN
to T
(Using Internal Reference)
MAX
Unipolar Offset±2±1LSB
Bipolar Offset±2±1LSB
Full Scale Calibration±9±2LSB
Power Supply Rejection Max Change In Full Scale Calibration
+13.5V < V
+4.5V < V
-16.5V < V
< +16.5V or +11.4V < VCC < +12.6V±2±1LSB
CC
< +5.5V±1/
LOGIC
< -13.5V or -12.6V < VEE < -11.4V±2±1LSB
EE
2
±1/
2
ANALOG INPUTS
Input Ranges
Bipolar-5 to +5 (Note 6)V
-10 to +10 (Note 7)V
Unipolar0 to +10 (Note 6)V
0 to +20 (Note 7)V
Input Impedance
10V Span5k, ±25%Ω
20V Span10k, ±25%Ω
POWER SUPPLIES
Operating Voltage Range
V
LOGIC
V
CC
V
EE
+4.5 to +5.5V
+11.4 to +16.5V
-11.4 to -16.5V
Operating Current
I
LOGIC
I
+15V Supply11 Typ, 15 MaxmA
CC
-15V Supply21 Typ, 28 MaxmA
I
EE
7 Typ, 15 MaxmA
Power Dissipation
±15V, +5V515 Typ, 720 MaxmW
±12V, +5V385 TypmW
Internal Reference Voltage
T
to T
MIN
MAX
Output Current, Available For External Loads (External Load Should Not
+10.00 ±0.05 MaxV
2.0 MaxmA
Change During Conversion).
UNITSJ SUFFIXK SUFFIX
LSB
5
FN3096.6
August 7, 2008
HI-574A, HI-674A
8
DC and Transfer Accuracy Specifications Typical at +25°C with V
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not
production tested. (Continued)
PARAMETER
DYNAMIC CHARACTERISTICS
Resolution (Max)1212Bits
Linearity Error
+25°C ±1±
-55°C to +125°C (Max)±1±1LSB
Max Resolution For Which No Missing Codes Is Guaranteed
+25°C1212Bits
T
to T
MIN
MAX
Unipolar Offset (Max)
Adjustable to Zero±2±1.5LSB
Bipolar Offset (Max)
V
= 0V (Adjustable to Zero)±4±4LSB
IN
= -10V±0.15±0.1% of FS
V
IN
Full Scale Calibration Error
+25°C (Max), With Fixed 50Ω Resistor From REF OUT To REF IN
(Adjustable To Zero)
to T
T
MIN
to T
T
MIN
Temperature Coefficients
Guaranteed Max Change, T
Unipolar Offset±2±1LSB
Bipolar Offset±2±2LSB
Full Scale Calibration±20±10LSB
Power Supply Rejection Max Change In Full Scale Calibration
+13.5V < V
+4.5V < V
-16.5V < V
ANALOG INPUTS
Input Ranges
Bipolar-5 to +5 (Note 6)V
Unipolar0 to +10 (Note 6)V
Input Impedance
10V Span5k, ±25%Ω
20V Span10k, ±25%Ω
POWER SUPPLIES
Operating Voltage Range
V
LOGIC
V
CC
V
EE
(No Adjustment At +25°C)±0.75±0.50% of FS
MAX
(With Adjustment To Zero At +25°C)±0.50±0.25% of FS
MAX
to T
MIN
< +16.5V or +11.4V < VCC < +12.6V±2±1LSB
CC
< +5.5V±1/
LOGIC
< -13.5V or -12.6V < VEE < -11.4V±2±1LSB
EE
(Using Internal Reference)
MAX
= +15V or +12V, V
CC
= +5V, VEE = -15V or -12V;
LOGIC
TEMPERATURE RANGE
-2 (-55°C to +125°C)
1
/
2
1112Bits
±0.25±0.25% of FS
2
±1/
2
-10 to +10 (Note 7)V
0 to +20 (Note 7)V
+4.5 to +5.5V
+11.4 to +16.5V
-11.4 to -16.5V
UNITSS SUFFIXT SUFFIX
LSB
LSB
6
FN3096.6
August 7, 2008
HI-574A, HI-674A
DC and Transfer Accuracy Specifications Typical at +25°C with V
= +15V or +12V, V
CC
= +5V, VEE = -15V or -12V;
LOGIC
Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not
production tested. (Continued)
TEMPERATURE RANGE
-2 (-55°C to +125°C)
PARAMETER
UNITSS SUFFIXT SUFFIX
Operating Current
I
LOGIC
+15V Supply11 Typ, 15 MaxmA
I
CC
I
-15V Supply21 Typ, 28 MaxmA
EE
7 Typ, 15 MaxmA
Power Dissipation
±15V, +5V515 Typ, 720 MaxmW
±12V, +5V385 TypmW
Internal Reference Voltage
T
to T
MIN
MAX
Output current, available for external loads (external load should not
+10.00 ±0.05 MaxV
2.0 MaxmA
change during conversion).
Digital Specifications All Models, Over Full Temperature Range; Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production tested.
STS Delay from CE--200ns
CE Pulse Width50--ns
CS to CE Setup50--ns
CS Low During CE High50--ns
R/C to CE Setup50--ns
R/C Low During CE High50--ns
AO to CE Setup0--ns
AO Valid During CE High50--ns
Conversion Time12-Bit Cycle T
5. Time is measured from 50% level of digital transitions. Tested with a 50pF and 3kΩ load.
6. For the “10V Input”, Pin 13.
7. For the “20V Input”, Pin 14.
Access Time from CE-75150ns
Data Valid After CE Low25--ns
Output Float Delay-100150ns
CS to CE Setup50--ns
R/C to CE Setup0--ns
AO to CE Setup50--ns
CS Valid After CE Low0--ns
R/C High After CE Low0--ns
AO Valid After CE Low50--ns
STS Delay After Data Valid300-1200ns
STS Delay from CE--200ns
CE Pulse Width50--ns
CS to CE Setup50--ns
CS Low During CE High50--ns
R/C to CE Setup50--ns
R/C Low During CE High50--ns
AO to CE Setup0--ns
AO Valid During CE High50--ns
Conversion Time12-Bit Cycle T
8-Bit Cycle T
MIN
MIN
to T
to T
MAX
MAX
81215µs
5810µs
Access Time from CE-75150ns
Data Valid After CE Low25--ns
Output Float Delay-100150ns
CS to CE Setup50--ns
R/C to CE Setup0--ns
AO to CE Setup50--ns
CS Valid After CE Low0--ns
R/C High After CE Low0--ns
AO Valid After CE Low50--ns
STS Delay After Data Valid25-850ns
8
FN3096.6
August 7, 2008
HI-574A, HI-674A
Pin Descriptions
PINSYMBOLDESCRIPTION
1V
212/8Data Mode Select - Selects between
3CS
4A
5R/C
6CEChip Enable - Chip Enable low disables
7V
8REF OUT +10V Reference
9ACAnalog Common
10REF INReference Input
11V
12BIP OFFBipolar Offset
1310V Input 10V Input - Used for 0V to 10V and -5V to
1420V Input 20V Input - Use d for 0V to 20V a nd -10 V to
15DCDigital Common
16DB0Data Bit 0 (LSB)
17DB1Data Bit 1
18DB2Data Bit 2
19DB3Data Bit 3
20DB4Data Bit 4
21DB5Data Bit 5
22DB6Data Bit 6
23DB7Data Bit 7
24DB8Data Bit 8
25DB9Data Bit 9
26DB10Data Bit 10
27DB11Data Bit 11 (MSB)
28STSStatus Bit - S tatus high implies a conversion
LOGIC
Logic supply pin (+5V)
12-bit and 8-bit output modes.
Chip Select - Chip Select high disables
the device.
Byte Address/Short Cycle - See Table 3
O
for operation.
Read/Convert - See T able 3 for operation.
the device.
Positive Supply (+12V/+15V)
CC
Negative Supply (-12V/-15V).
EE
+5V input ranges.
+10V input ranges.
is in progress.
Definitions of Specifications
Linearity Error
Linearity error refers to the deviation of each individual code
from a line drawn from “zero” through “full scale”. The point
used as “zero” occurs
the first code transition (all zeros to only the LSB “on”). “Full
scale” is defined as a level 1
transition (to all ones). The deviation of a code from the true
straight line is measured from the middle of each particular
code.
1
/2 LSB (1.22mV for 10V span) before
1
/2 LSB beyond the last code
The HI-X74AK grade is guaranteed for maximum nonlinearity
1
of ±
/2 LSB. For this grade, this means that an analog value
which falls exactly in the center of a given code width will result
in the correct digital output code. Values nearer the upper or
lower transition of the code width may produce the next upper
or lower digital output code. The HI-X74AJ is guaranteed to ±1
LSB max error. For this grade, an analog value which falls
within a given code width will result in either the correct code for
that region or either adjacent one.
Note that the linearity error is not user-adjustable.
Differential Linearity Error (No Missing Codes)
A specification which guarantees no missing codes requires
that every code combination appear in a monotonic increasing
sequence as the analog input level is increased. Thus every
code must have a finite width. For the HI-X74AK grade, which
guarantees no missing codes to 12-bit resolution, all 4096
codes must be present over the entire operating temperature
ranges. The HI-X74AJ grade guarantees no missing codes to
11 -bit resolution over tempe rature; this means th at all code
combinations of the upper 1 1 bits must be present; in practice
very few of the 12-bit codes are missing.
Unipolar Offset
The first transition should occur at a level 1/2 LSB above analog
common. Unipolar offset is defined as the deviation of the
actual transition from that point. This offset can be adjusted as
discussed on the following pages. The unipolar offset
temperature coefficient specifies the maximum change of the
transition point over temperature, with or without external
adjustment.
Bipolar Offset
Similarly, in the bipolar mode, the major carry transition
(0111 1111 1111 to 1000 0000 0000) should occur for an
analog value
1
/2 LSB below analog common. The bipolar
offset error and temperature coefficient specify the initial
deviation and maximum change in the error over
temperature.
Full Scale Calibration Error
The last transition (from 111 1 1111 1110 to 1111 1111 1111)
should occur for an analog value 1
nominal full scale (9.9963V for 10.000V full scale). The full
scale calibration error is the deviation of the actu al level at
the last transition from the ideal level. This error, which is
typically 0.05 to 0.1% of full scale, can be trimmed out as
shown in Figures 1 and 2. The full scale calibration error
over temperature is given with and without the initial error
trimmed out. The temperature coefficients for each grade
indicate the maximum change in the full scale gain from the
initial value using the internal 10V reference.
1
/2 LSB below the
9
FN3096.6
August 7, 2008
HI-574A, HI-674A
Temperature Coefficients
The temperature coefficients for full-scale calibration,
unipolar offset, and bipolar offset specify the maximum
change from the initial (25°C) value to the value at T
T
.
MAX
MIN
or
Power Supply Rejection
The standard specifications for the HI-X74A assume use of
+5.00V and ±15.00V or ±12.00V supplies. The only effect of
power supply error on the performance of the device will be
a small change in the full scale calibration. This will result in
a linear change in all lower order codes. The specifications
show the maximum change in calibration from the initial
value with the supplies at the various limits.
Code Width
A fundamental quantity for A/D converter specifications is
the code width. This is defined as the range of analog input
values for which a given digital output code will occur. The
nominal value of a code width is equivalent to 1 least
significant bit (LSB) of the full scale range or 2.44mV out of
10V for a 12-bit ADC.
Quantization Uncertainty
Analog-to-digital converters exhibit an inherent quantization
uncertainty of ±
characteristic of the quantization process and cannot be
reduced for a converter of given resolution.
1
/2 LSB. This uncertainty is a fundamental
Left-Justified Data
The data format used in the HI-X74A is left-justified. This
means that the data represents the analog input as a fraction
of full-scale, ranging from 0 to. This implies a binary
point to the left of the MSB.
4095
4096
Applying the HI-X74A
For each application of this converter, the ground
connections, power supply bypassing, analog signal source,
digital timing and signal routing on the circuit board must be
optimized to assure maximum performance. These areas
are reviewed in the following sections, along with basic
operating modes and calibration requirements.
Physical Mounting and Layout Considerations
LAYOUT
Unwanted, parasitic circuit components, (L, R, and C) can
make 12-bit accuracy impossible, even with a perfect A/D
converter. The best policy is to eliminate or minimize these
parasitics through proper circuit layout, rather than try to
quantify their effects.
The recommended construction is a double-sided printed
circuit board with a ground plane on the component side.
Other techniques, such as wire-wrapping or point-to-point
wiring on vector board, will have an unpredictable effect on
accuracy.
In general, sensitive analog signals should be routed between
ground traces and kept well away from digital lines. If analog
and digital lines must cross, they should do so at right angles.
Power Supplies
Supply voltages to the HI-X74A (+15V, -15V and +5V) must be
“quiet” and well regulated. Voltage spikes on these lines can
affect the converter’s accuracy , causing several LSBs to flicker
when a constant input is applied. Digital noise and spikes from
a switching power supply are especially troublesome. If
switching supplies must be used, outputs should be carefully
filtered to assure “quiet” DC voltage at the converter terminals.
Further, a bypass capacitor pair on each supply voltage
terminal is necessary to counter the effect of variations in
supply current. Connect one pair from pin 1 to 15 (V
supply), one from pin 7 to 9 (V
one from pin 11 to 9 (V
capacitor pair, a 10µF tantalum type in parallel with a 0.1µF
ceramic type is recommended.
to Analog Common). For each
EE
to Analog Common) and
CC
LOGIC
Ground Connections
Pins 9 and 15 should be tied together at the package to
guarantee specified performance for the converter. In
addition, a wide PC trace should run directly from pin 9 to
(usually) +15V common, and from pin 15 to (usually) the +5V
Logic Common. If the converter is located some dista nce from
the system’s “single point” ground, make only these
connections to pins 9 and 15: Tie them together at the
package, and back to the system ground with a single path.
This path should have low resistance. (Code dependent
currents flow in the V
through the HI-X74A’s AnalogCommon or Digital Common).
, VEE and V
CC
terminals, but not
LOGIC
Analog Signal Source
HI-574A and HI-674A
The device chosen to drive the HI-X74A analog input will see a
nominal load of 5kΩ (10V range) or 10kΩ (20V range).
However, the other end of these input resistors may change
±400mV with each bit decision, creating abrupt changes in
current at the analog input. Thus, the signal source must
maintain its output voltage while furnishing these step changes
in load current, which occur at 1.6μs and 950ns intervals for the
HI-574A and HI-674A, respectively. This requires low output
impedance and fast settling by the signal source.
The output impedance of an op amp, for example, has an
open loop value which, in a closed loop, is divided by the
loop gain available at a frequency of interest. The amplifier
should have acceptable loop gain at 600kHz for use with the
HI-X74A. To check whether the output properties of a signal
source are suitable, monitor the HI-X74A’s input (pin 13 or
14) with an oscilloscope while a conversion is in progress.
Each of the twelve disturbances should subside in 1μs or
less for the HI-574A and 500ns or less for the HI-674A. (The
comparator decision is made about 1.5µs and 850ns after
each code change from the SAR for the HI-574A and
HI-674A, respectively.)
10
FN3096.6
August 7, 2008
HI-574A, HI-674A
If the application calls for a Sample/Hold to precede the
converter, it should be noted that not all Sample/Holds are
compatible with the HI-574A in the manner described above.
These will require an additional wideband buffer amplifier to
lower their output impedance. A simpler solution is to use the
Intersil HA-5320 Sample/Hold, which was designed for use
with the HI-574A.
STS 28
HIGH BITS
MIDDLE BITS
LOW BITS
+5V 1
+15V 7
-15V 11
†
DIG COM 15
24-27
20-23
16-19
-15V
ANALOG
100K
100Ω
0V TO +10V
INPUTS
0V TO +20V
OFFSET
R1
100K
R2
+15V
GAIN
100Ω
212/8
3CS
4A
O
5R/C
6CE
10 REF IN
8REF OUT
12 BIP OFF
13 10V
IN
14 20V
IN
9 ANA
COM
†When driving the 20V (pin 14) input, minimize capacitance on pin 13.
FIGURE 1. UNIPOLAR CONNECTIONS
HIGH BITS
MIDDLE BITS
LOW BITS
-15V 11
†
DIG COM 15
STS 28
24-27
20-23
16-19
+5V 1
+15V 7
ANALOG
INPUTS
±5V
±10V
R2
R1
GAIN
100Ω
100Ω
OFFSET
2 12/8
3CS
4A
O
5R/C
6CE
10 REF IN
8REF OUT
12 BIP OFF
13 10V
IN
14 20V
IN
9 ANA
COM
†When driving the 20V (pin 14) input, minimize capacitance on pin 13.
FIGURE 2. BIPOLAR CONNECTIONS
Range Connections and Calibration Procedures
The HI-X74A is a “complete” A/D converter, meanin g it is fully
operational with addition of the power supply volt ages, a Start
Convert signal, and a few external components as shown in
Figures 1 and 2. Nothing more is required for most
applications.
Whether controlled by a processor or operating in the
stand-alone mode, the HI-X74A offers four standard input
ranges: 0V to +10V, 0V to +20V, ±5V and ±10V. The
maximum errors for gain and offset are listed under
Specifications. If required, however, these errors may be
adjusted to zero as explained below. Power supply and
ground connections have been discussed in an earlier
section.
Unipolar Connections and Calibration
Refer to Figure 1. The resistors shown (see Note below)
are for calibration of offset and gain. If this is not required,
replace R2 with a 50Ω, 1% metal film resistor and remove
the network on pin 12. Connect pin 12 to pin 9. Then,
connect the analog signal to pin 13 for the 0V to 10V range,
or to pin 14 for the 0V to 20V range. Inputs to +20V (5V
over the power supply) are no problem - the converter
operates normally.
Calibration consists of adjusting the converter’s most
negative output to its ideal value (offset adjustment), then,
adjusting the most positive output to its ideal value (gain
adjustment). To understand the procedure, note that in
principle, one is setting the output with respect to the
midpoint of an increment of analog input, as denoted by
two adjacent code changes. Nominal value of an increme nt
is one LSB. However, this approach is impractical because
nothing “happens” at a midpoint to indicate that an
adjustment is complete. Therefore, calibration is performed
in terms of the observable code changes instead of the
midpoint between code changes.
For example, midpoint of the first LSB increment should be
positioned at the origin, with an output code of all 0’s. To do
this, apply an input of +
1
/2 LSB (+1.22mV for the 10V range;
+2.44mV for the 20V range). Adjust the Offset potentiometer
R1 until the first code transition flickers between
0000 0000 0000 and 0000 0000 0001.
Next, perform a Gain Adjust at positive full scale. Again, the
ideal input corresponding to the last code change is applied.
This is 1
1
/2 LSBs below the nominal full scale (+9.9963V for
10V range; +19.9927V for 20V range). Adjust the Gain
potentiometer R2 for flicker between codes 1111 1111 1110
and 1111 1111 1111 .
Bipolar Connections and Calibration
Refer to Figure 2. The gain and offset errors listed under
Specifications may be adjusted to zero using
potentiometers R1 and R2 (see Note below). If this isn’t
11
FN3096.6
August 7, 2008
HI-574A, HI-674A
required, either or both pots may be replaced by a 50Ω, 1%
metal film resistor.
Connect the Analog signal to pin 13 for a ±5V range, or to
pin 14 for a ±10V range. Calibration of offset and gain is
similar to that for the unipolar ranges as discussed above.
First apply a DC input voltage
1
/2 LSB above negative full
scale (i.e., -4.9988V for the ±5V range, or -9.9976V for the
±10V range). Adjust the offset potentiometer R1 for flicker
between output codes 0000 0000 0000 and 0000 0000
0001. Next, apply a DC input voltage 1
1
/2 LSBs below
positive full scale (+4.9963V for ±5V range; +9.9927V for
±10V range). Adjust the Gain potentiometer R2 for flicker
between codes 1111 1111 1110 and 1111 1111 1111.
NOTE: The 100Ω potentiometer R2 provides Gain Adjust for the 10V
and 20V ranges. In some applications, a full scale of 10.24V (LSB
equals 2.5mV) or 20.48V (LSB equals 5.0mV) is more convenient.
For these, replace R2 by a 50Ω, 1% metal film resistor. Then, to provide Gain Adjust for the 10.24V range, add a 200Ω potentiometer in
series with pin 13. For the 20.48V range, add a 500Ω potentiometer
in series with pin 14.
Controlling the HI-X74A
The HI-X74A includes logic for direct interface to most
microprocessor systems. The processor may take full
control of each conversion, or the converter may operate in
the “stand-alone” mode, controlled only by the R/C
Full control consists of selecting an 8-bit or 12-bit
conversion cycle, initiating the conversion, and reading the
output data when ready-choosing either 12 bits at once or 8
followed by 4, in a left-justified format. The five control
inputs are all TTL/CMOS-compatible: (12/8
, CS, AO, R/C
and CE). Table 3 illustrates the use of these inputs in
controlling the converter’s operations. Also, a simplified
schematic of the internal control logic is shown in Figure 6.
“Stand-Alone Operation”
The simplest control interface calls for a single control line
connected to R/C
A
are wired low, and the output data appears in words of
O
12 bits each.
The R/C
signal may have any duty cycle within (and
including) the extremes shown in Figures 7 and 8. In
general, data may be read when R/C
also high, indicating a conversion is in progress. Timing
parameters particular to this mode of operation are listed in
Tables 1 and 2.
. Also, CE and 12/8 are wired high, CS and
is high unless STS is
input.
TABLE 1. HI-574A STAND-ALONE MODE TIMING
SYMBOLPARAMETERMIN TYP MAX UNITS
t
Low R/C Pulse Width50--ns
HRL
t
STS Delay from R/C--200ns
DS
t
t
t
Time is measured from 50% level of digital transitions. Tested with a
50pF and 3kΩ load.
SYMBOLPARAMETERMIN TYP MAX UNITS
Time is measured from 50% level of digital transitions. Tested with
a 50pF and 3kΩ load.
Data Valid after R/C Low25--ns
HDR
STS Delay after Data Valid 300-1200ns
t
HS
High R/C Pulse Width150--ns
HRH
Data Access Time--150ns
DDR
TABLE 2. HI-674A STAND-ALONE MODE TIMING
t
t
t
t
Low R/C Pulse Width50--ns
HRL
t
STS Delay from R/C--200ns
DS
Data Valid after R/C Low25--ns
HDR
t
STS Delay after Data
HS
Valid
High R/C Pulse Width150--ns
HRH
Data Access Time--150ns
DDR
25-850ns
Conversion Length
A Convert Start transition (see Table 1) latches the state of
A
, which determines whether the conversion continues for
O
12 bits (A
low) or stops with 8 bits (AO high). If all 12 bits are
O
read following an 8-bit conversion, the last three LSBs will
read ZERO and DB3 will read ONE. A
is latched because it
O
is also involved in enabling the output buffers (see ““Reading
the Output Data” on page 13). No other control inputs are
latched.
A conversion may be initiated as shown in Table 3 by a logic
transition on any of three inputs: CE, CS
or R/C. The last of
the three to reach the correct state starts the conversion, so
one, two or all three may be dynamically controlled. The
nominal delay from each is the same, and if necessary, all
three may change state simultaneously. However, to ensure
that a particular input cont ro ls the start of conversion, the
other two should be set up at least 50ns earlier. See the
HI-X74A Timing Specifications, Convert Mode.
This variety of HI-X74A control modes allows a simple
interface in most system applications. The Convert Start
timing relationships are illustrated in Figure 3.
The output signal STS indicates status of the converter by
going high only while a conversion is in progress. While STS
is high, the output buffers remain in a high impedance state
and data cannot be read. Also, an additional Start Convert
will not reset the converter or re-initiate a conversion while
STS is high.
Reading the Output Data
The output data buffers remain in a high impedance state
until four conditions are met: R/C
and CS
low. At that time, data lines become active according
to the state of inputs 12/8
illustrated in Figure 4.
The 12/8
input will be tied high or low in most applications,
though it is fully TTL/CMOS-compatible. With 12/8
high, STS low, CE high
and AO. Timing constraints are
high, all
12 output lines become active simultaneously, for interface
to a 12-bit or 16-bit data bus. The A
input is ignored.
O
With 12/8 low, the output is organized in two 8-bit bytes,
selected one at a time by A
to be connected as shown in Figure 5. A
. This allows an 8-bit data bus
O
is usually tied to
O
the least significant bit of the address bus, for storing the
HI-X74A output in two consecutive memory locations. (With
A
low, the 8 MSBs only are enabled. With AO high, 4 MSBs
O
are disabled, bits 4 through 7 are forced low, and the 4 LSBs
are enabled). This two byte format is considered “left justified
data,” for which a decimal (or binary!) point is assumed to
the left of byte 1:
BYTE 1BYTE 2
XXXXXXXX XXXX0000
•
MSBLSB
Further, A
may be toggled at any time without damage to
O
the converter. Break-before-make action is guaranteed
between the two data bytes, which assures that the outputs
strapped together in Figure 5 will never be enabled at the
same time.
A read operation usually begins after the conversion is
complete and STS is low. For earliest access to the data,
however, the read should begin no later than (t
DD
+ tHS)
before STS goes low. See Figure 4.
t
CE
CS
R/C
A
STS
DB11-DB0
t
SSC
t
SRC
t
t
SAC
HRC
t
HAC
t
DSC
HIGH IMPEDANCE
O
HEC
t
HSC
t
C
See HI-X74A Timing Specifications for more information.
FIGURE 3. CONVERT START TIMING
CE
CS
R/C
A
STS
DB11-DB0
t
SSR
t
O
SRR
t
SAR
HIGH IMPEDANCE
t
HSR
t
HRR
t
HAR
t
HS
DATA
VALID
t
DD
See HI-X74A Timing Specifications for more information.
FIGURE 4. READ CYCLE TIMING
t
HD
t
HL
13
FN3096.6
August 7, 2008
HI-574A, HI-674A
A
O
1
2
12/8
3
4
A
O
5
6
7
8
9
10
11
12
13
14
ADDRESS BUS
DB11 (MSB)
HI-X74A
DB0 (LSB)
COM.
STS
DIG.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FIGURE 5. INTERFACE TO AN 8-BIT DATA BUS
DATA
BUS
INPUT BUFFERS
12/8
CS
A
O
R/C
CE
D
A
O
CK
Q
Q
LATCH
EOC9
EOC13
READ CONTROL
POWER UP
RESET
FIGURE 6. HI-X74A CONTROL LOGIC
CONVERT
CONTROL
CURRENT
CONTROLLED
OSCILLATOR
NIBBLE B ZERO
OVERRIDE
NIBBLE A, B
NIBBLE C
STATUS
STROBE
CLOCK
RESET
14
FN3096.6
August 7, 2008
R/C
STS
HI-574A, HI-674A
t
HRL
t
DS
t
HDR
t
C
t
HS
DB11-DB0
DATA
VALID
FIGURE 7. LOW PULSE FOR R/C - OUTPUTS ENABLED AFTER CONVERSION
R/C
t
HRH
STS
t
DDR
DB11-DB0
FIGURE 8. HIGH PULSE FOR R/C
DATA
VALID
t
DS
t
C
HIGH-ZHIGH-Z
DATA
VALID
t
HDR
- OUTPUTS ENABLED WHILE R/C HIGH, OTHERWISE HIGH-Z
15
FN3096.6
August 7, 2008
Die Characteristics
HI-574A, HI-674A
DIE DIMENSIONS:
Analog: 3070mm x 4610mm
Digital: 1900mm x 4510mm
METALLIZATION:
Digital Type: Nitrox
Thickness: 10kű2kÅ
Metal 1: AlSiCu
Thickness: 8k
ű1kÅ
Metal 2: AlSiCu
Thickness: 16k
ű2kÅ
Analog Type: Al
Thickness: 16k
ű2kÅ
Metallization Mask Layout
O
R/C
V
A
CE
CC
CS
PASSIVATION:
WORST CASE CURRENT DENSITY:
HI-574A, HI-674A
Type: Nitride Over Silox
Nitride Thickness: 3.5kű0.5kÅ
Silox Thickness: 12kű1.5kÅ
5
2
1.3 x 10
A/cm
12/8
LOGIC
V
V
LOGIC
STS
DB11
DB10
DB9
V
REFOUT
ANALOG
COMMON
ANALOG
COMMON
ANALOG
COMMON
V
REFIN
V
EE
10VIN20V
OFFSET
BIPOLAR
DB8
DB7
DB6
DB5
DB4
DB3
DB2
IN
DIGITAL
COMMON
DB0
DB1
16
FN3096.6
August 7, 2008
HI-574A, HI-674A
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
LEAD FINISH
c1
-A-
-B-
S
bbbC A - B
BASE
PLANE
SEATING
PLANE
S1
b2
ccc
b
CA - BM
D
A
A
e
DSS
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. Dimension Q shall be measured from the seating plane to the
base plane.
6. Measure dimension S1 at all four corners.
7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
-DBASE
E
S
S
D
Q
S2
-C-
METAL
b1
M
(b)
SECTION A-A
A
L
(c)
M
eA
aaa
eA/2
CA - BMDSS
c
D28.6 MIL-STD-1835 CDIP2-T28 (D-10, CONFIGURATION C)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implicat ion or oth erwise u nde r any p a tent or p at ent r ights of Intersil or its subsidiari es.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
FN3096.6
August 7, 2008
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