Intersil Corporation HI5741 Datasheet

TM

HI5741

Data Sheet May 2000 File Number 4071.7

14-Bit, 100 MSPS, High Speed D/A
Converter

The HI5741 is a 14-bit, 100 MSPS, D/A converter which is
implemented in the Intersil BiCMOS 10V (HBC-10) process.
Operating from +5V and -5.2V, the converter provides

20.48mA of full scale output current and includes an input
data register and bandgap voltage reference. Low glitch
energy and excellent frequency domain performance are
achieved using a segmented architecture. The digital inputs
are TTL/CMOS compatible and translated internally to ECL.
All internal logic is implemented in ECL to achieve high
switching speed with low noise. The addition of laser
trimming assures 14-bit linearity is maintained along the
entire transfer curve.

Ordering Information

TEMP.

PART NUMBER

RANGE (oC) PACKAGE

HI5741BIP -40 to 85 28 Ld PDIP E28.6
HI5741BIB -40 to 85 28 Ld SOIC M28.3
HI5741-EVS 25 Evaluation Board (SOIC)

PKG.

NO.

Features

• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 100 MSPS

• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mW

• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . . .1 LSB

• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . . . 1pV-s

• TTL/CMOS Compatible Inputs

• Improved Hold Time. . . . . . . . . . . . . . . . . . . . . . . . 0.25ns

• Excellent Spurious Free Dynamic Range

Applications

• Cellular Base Stations

• Wireless Communications

• Direct Digital Frequency Synthesis

• Signal Reconstruction

• Test Equipment

• High Resolution Imaging Systems

• Arbitrary Waveform Generators

Pinout

HI5741

(PDIP, SOIC)

TOP VIEW

3-1

D13 (MSB)

D0 (LSB)

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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

D12
D11
D10

D9
D8
D7
D6
D5
D4
D3
D2
D1

1
2
3
4
5
6
7
8

9
10
11
12
13
14

DGND

28
27

AGND

26

REF OUT

25

CTRL AMP OUT

24

CTRL AMP IN

23

R

SET

22

AV

EE

21

I

OUT

20

I

OUT

19

ARTN

18

DV

EE

17

DGND

16

DV

CC

15

CLOCK

Typical Application Circuit

HI5741

50Ω

0.01µF

0.01µF0.1µF

+5V

D13
D12

D11
D10

D9
D8
D7
D6
D5

D4
D3
D2

D1
D0

-5.2V (DVEE)

HI5741

DV

(16)

CC

D13 (MSB) (1)
D12 (2)
D11 (3)
D10 (4)
D9 (5)
D8 (6)
D7 (7)
D6 (8)
D5 (9)
D4 (10)

D3 (11)
D2 (12)

D1 (13)

D0 (LSB) (14)

CLK (15)

DGND (17, 28)

DVEE (18)

(24) CTRL AMP IN

(25) CTRL AMP OUT

(26) REF OUT

(21) I

OUT

(20) I

OUT

(23) R

SET

(19) ARTN

(27) AGND

(22) AV

EE

-5.2V (AVEE)

0.1µF

-5.2V (AVEE)

64Ω

64Ω

976Ω

0.01µF

D/A OUT

0.1µF

Functional Block Diagram

(LSB) D0

D1
D2

D3
D4
D5
D6

D7
D8

D9
D10
D11
D12

(MSB) D13

CLK

14-BIT

MASTER

REGISTER

DAT A

BUFFER/

LEVEL

SHIFTER

UPPER

4-BIT

DECODER

OVERDRIVEABLE

VOLTAGE

REFERENCE

SLAVE

REGISTER

15 15

10 LSBs

CURRENT

CELLS

15
SWITCHED
CURRENT

CELLS

REF CELL

R2R

NETWORK

227Ω 227Ω

+

25Ω

-

ARTN

I

OUT

I

OUT

CTRL AMP
IN

CTRL AMP
OUT

AVEEAGND DVEEDGND DV

3-2

CC

REF OUT

R

SET

HI5741

Absolute Maximum ratings T

Digital Supply Voltage VCC to DGND . . . . . . . . . . . . . . . . . . . +5.5V

Negative Digital Supply Voltage DVEE to DGND . . . . . . . . . . -5.5V

Negative Analog Supply Voltage AVEE to AGND, ARTN. . . . . -5.5V

Digital Input Voltages (D13-D0, CLK) to DGND. . . . . DVCC to -0.5V

Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . ±2.5mA

Voltage from CTRL AMP IN to AVEE. . . . . . . . . . . . . . . . 2.5V to 0V

Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . ±2.5mA

Reference Input Voltage Range. . . . . . . . . . . . . . . . . .-3.7V to AV

Analog Output Current (I

) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA

OUT

=25oC Thermal Information

A

Thermal Resistance (Typical, Note 1) θJA (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Maximum Junction Temperature

HI5741BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

EE

(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications AV

PARAMETER TEST CONDITIONS

SYSTEM PERFORMANCE

Resolution 14 - - Bits
Integral Linearity Error, INL

(Notes 5)
Differential Linearity Error, DNL (Note 5) TA = 25oC - 0.5 1.0 LSB

Offset Error, I
Full Scale Gain Error, FSE (Notes 3, 5) - 3.2 10 %
Offset Drift Coefficient (Note 4) - - 0.05 µA/oC
Full Scale Output Current, I
Output Voltage Compliance Range (Note 4) -1.25 - 0 V

DYNAMIC CHARACTERISTICS

Throughput Rate (Note 4) 100 - - MSPS
Output Voltage Settling Time

(1/16th Scale Step Across Segment)
Singlet Glitch Area, GE (Peak) RL = 64Ω (Note 4) - 1 - pV•s

Output Slew Rate RL = 64Ω,DAC Operating in Latched Mode (Note 4) - 1,000 - V/µs
Output Rise Time RL = 64Ω,DAC Operating in Latched Mode (Note 4) - 675 - ps
Output Fall Time RL = 64Ω,DAC Operating in Latched Mode (Note 4) - 470 - ps
Spurious Free Dynamic Range within a Window

(Note 4)

Spurious Free Dynamic Range to Nyquist
(Notes 4)

OS

FS

, DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, V

EE

TA = 25oC

“Best Fit Straight Line”, TA = 25oC - 1.0 1.5 LSB
“Best Fit Straight Line”, TA = -40oC to 85oC - - 1.75 LSB

(Note 5) - 8 75 µA

RL = 64Ω (Note 4) - Settling to 0.024% - 11 - ns
RL = 64Ω (Note 4) - Settling to 0.012% - 20 - ns

f

= 10 MSPS, f

CLK

f

= 20 MSPS, f

CLK

f

= 40 MSPS, f

CLK

f

= 50 MSPS, f

CLK

f

= 80 MSPS, f

CLK

f

= 100 MSPS, f

CLK

f

= 10 MSPS, f

CLK

f

= 10 MSPS, f

CLK

f

= 25 MSPS, f

CLK

f

= 50 MSPS, f

CLK

f

= 75 MSPS, f

CLK

f

= 100 MSPS, f

CLK

= 1.23MHz, 2MHz Span - 87 - dBc

OUT

= 5.055MHz, 2MHz Span - 77 - dBc

OUT

= 16MHz, 10MHz Span - 75 - dBc

OUT

= 10.1MHz, 2MHz Span - 80 - dBc

OUT

= 5.1MHz, 2MHz Span - 78 - dBc

OUT

= 10.1MHz, 2MHz Span - 79 - dBc

OUT

= 1.023MHz, 5MHz Span - 86 - dBc

OUT

= 2.02MHz, 5MHz Span - 85 - dBc

OUT

= 2.02MHz, 12.5MHz Span - 77 - dBc

OUT

= 5.055MHz, 25MHz Span - 74 - dBc

OUT

= 7.52MHz, 37.5MHz Span - 73 - dBc

OUT

= 10.1MHz, 50MHz Span - 71 - dBc

OUT

= Internal,

REF

HI5741BI

TA = -40oC TO 85oC

UNITSMIN TYP MAX

- -20.48 - mA

3-3

HI5741

Electrical Specifications AV

, DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, V

EE

= Internal,

REF

TA = 25oC (Continued)

HI5741BI

TA = -40oC TO 85oC

PARAMETER TEST CONDITIONS

Multi-Tone Power Ratio
(MTPR)

8 Tones, no Clipping, 110kHz Spacing, 220kHz
spacing between tones 4 and 5, f

= 20 MSPS

CLK

- 76 - dBc

UNITSMIN TYP MAX

(Note 7)

REFERENCE/CONTROL AMPLIFIER

Internal Reference Voltage, V

REF

(Notes 5) -1.27 -1.23 -1.17 V
Internal Reference Voltage Drift (Note 4) - 50 - µV/oC
Internal Reference Output Current Sink/Source

(Note 4) -500 - +50 µA
Capability

Internal Reference Load Regulation I

REF

= 0 to I

= -500µA - 100 - µV

REF

Amplifier Input Impedance (Note 4) - 3 - MΩ
Amplifier Large Signal Bandwidth 4.0V

Amplifier Small Signal Bandwidth 1.0V

Sine Wave Input, to Slew Rate Limited (Note4)- 1 - MHz

P-P

Sine Wave Input, to -3dB Loss (Note 4) - 5 - MHz

P-P

Reference Input Impedance (CTL IN) (Note 4) - 12 - kΩ
Reference Input Multiplying Bandwidth (CTL IN) RL = 50Ω, 100mV Sine Wave, to -3dB Loss at I

OUT

- 75 - MHz

(Note 4)
DIGITAL INPUTS (D9-D0, CLK, INVERT)
Input Logic High Voltage, V
Input Logic Low Voltage, V
Input Logic Current, I
Input Logic Current, I

IH
IL

Digital Input Capacitance, C

IH

IL

IN

(Note 5) 2.0 - - V

(Note 5) - - 0.8 V

(Note 5) - - 400 µA

(Note 5) - - 700 µA

(Note 4) - 3.0 - pF

TIMING CHARACTERISTICS

Data Setup Time, t
Data Hold Time, t

SU

HLD

Propagation Delay Time, t
CLK Pulse Width, t

PW1

, t

PD

PW2

See Figure 1 (Note 4) 3 2.0 - ns

See Figure 1 (Note 4) 0.5 0.25 - ns

See Figure 1 (Note 4) - 4.5 - ns

See Figure 1 (Note 4) 1.0 0.85 - ns

POWER SUPPLY CHARACTERISTICS

IV
IV
IV

EEA
EED
CCD

(Note 5) - 42 50 mA

(Note 5) - 75 95 mA

(Note 5) - 13 20 mA
Power Dissipation (Note 5) - 650 - mW
Power Supply Rejection Ratio VCC±5%, VEE±5% - 5 - µA/V

NOTES:

2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.

3. Gain Error measured as the error in the ratio between the full scale output current and the current through R

(typically 1.28mA). Ideally the

SET

ratio should be 16.

4. Parameter guaranteed by design or characterization and not production tested.

5. All devices are 100% tested at 25oC.

6. Dynamic Range must be limited to a 1V swing within the compliance range.

7. In testing MTPR, tone frequencies rangedfrom 1.95MHz to 3.05MHz. The ratio is measured as the range from peak power to peak distortion in
the region of removed tones.

3-4