Intersil Corporation HI5731 Datasheet

TM

HI5731

Data Sheet May 2000 File Number 4070.6

12-Bit, 100 MSPS, High Speed D/A
Converter

The HI5731 is a 12-bit, 100 MSPS, D/A converter which is
implemented in the Intersil BiCMOS 10V (HBC-10) process.
Operating from +5V and -5.2V, the converter provides

-20.48mA of full scale output current and includes an input
data register and bandgap voltage reference. Low glitch
energy and excellent frequency domain performance are
achieved using a segmented architecture. The digital inputs
are TTL/CMOS compatible and translated internally to ECL.
All internal logic is implemented in ECL to achieve high
switching speed with low noise. The addition of laser
trimming assures 12-bit linearity is maintained along the
entire transfer curve.

Ordering Information

TEMP.

PART NUMBER

RANGE (oC) PACKAGE PKG. NO.

HI5731BIP -40 to 85 28 Ld PDIP E28.6
HI5731BIB -40 to 85 28 Ld SOIC M28.3
HI5731-EVS 25 Evaluation Board (SOIC)

Pinout

HI5731

(PDIP, SOIC)

TOP VIEW

Features

• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . 100 MSPS

• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mW

• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . 0.75 LSB

• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . .3.0pV-s

• TTL/CMOS Compatible Inputs

• Improved Hold Time. . . . . . . . . . . . . . . . . . . . . . . . 0.25ns

• Excellent Spurious Free Dynamic Range

Applications

• Cellular Base Stations

• GSM Base Stations

• Wireless Communications

• Direct Digital Frequency Synthesis

• Signal Reconstruction

• Test Equipment

• High Resolution Imaging Systems

• Arbitrary Waveform Generators

D11 (MSB)

D10

D9
D8
D7
D6
D5
D4
D3
D2
D1

D0 (LSB)

NC
NC

1
2
3
4
5
6
7
8

9
10
11
12
13
14

3-1

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DGND

28
27

AGND

26

REF OUT

25

CTRL OUT

24

CTRL IN

23

R

22

AV

21

I

OUT

20

I

OUT

19

ARTN

18

DV

17

DGND

16

DV

15

CLOCK

SET

EE

EE

CC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Typical Application Circuit

0.01µF

+5V

DV

CC

(16)

HI5731

HI5731

50Ω

0.1µF

Functional Block Diagram

D11
D10

D9
D8
D7
D6
D5
D4
D3

D2
D1
D0

0.01µF

- 5.2V (DVEE)

D11 (MSB) (1)
D10 (2)
D9 (3)
D8 (4)
D7 (5)
D6 (6)
D5 (7)
D4 (8)
D3 (9)
D2 (10)

D1 (11)
D0 (LSB) (12)

CLK (15)

DGND (17, 28)

DVEE (18)

(24) CTRL IN

(25) CTRL OUT

(26) REF OUT

(21) I

OUT

(20) I

OUT

(23) R

SET

(19) ARTN

(27) AGND

(22) AV

EE

- 5.2V (AVEE)

0.1µF

-5.2V (AVEE)

64Ω

64Ω

976Ω

0.01µF

D/A OUT

0.1µF

(LSB) D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

(MSB) D11

CLK

12-BIT

MASTER

REGISTER

AGND DVEEDGND DV

AV

EE

DAT A

BUFFER/

LEVEL

SHIFTER

DECODER

OVERDRIVEABLE

VOLTAGE

REFERENCE

CC

UPPER

4-BIT

15

SLAVE

REGISTER

REF OUT R

15

8 LSBs

CURRENT

CELLS

15

SWITCHED

CURRENT

CELLS

REF CELL

SET

R2R

NETWORK

227Ω 227Ω

25Ω

+

-

ARTN

I

OUT

I

OUT

CTRL
IN

CTRL
OUT

3-2

HI5731

Absolute Maximum Ratings Thermal Information

Digital Supply Voltage VCC to DGND . . . . . . . . . . . . . . . . . . . +5.5V

Negative Digital Supply Voltage DVEE to DGND . . . . . . . . . . -5.5V

Negative Analog Supply Voltage AVEE to AGND, ARTN. . . . . -5.5V

Digital Input Voltages (D11-D0, CLK) to DGND. . . . . DVCC to -0.5V

Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . ±2.5mA

Voltage from CTRL IN to AVEE . . . . . . . . . . . . . . . . . . . . 2.5V to 0V

Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . ±2.5mA

Reference Input Voltage Range. . . . . . . . . . . . . . . . . .-3.7V to AV

Analog Output Current (I

) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA

OUT

EE

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA (oC/W)

PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Maximum Junction Temperature

HI5731BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

Electrical Specifications AV

, DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, V

EE

= Internal

REF

TA = 25oC for All Typical Values

HI5731BI

TA = -40oC TO 85oC

PARAMETER TEST CONDITIONS

UNITSMIN TYP MAX

SYSTEM PERFORMANCE

Resolution 12 - - Bits
Integral Linearity Error, INL (Note 4) (“Best Fit” Straight Line) - 0.75 1.5 LSB
Differential Linearity Error, DNL (Note 4) - 0.5 1.0 LSB
Offset Error, I

OS

(Note 4) - 20 75 µA
Full Scale Gain Error, FSE (Notes 2, 4) - 1 10 %
Offset Drift Coefficient (Note 3) - - 0.05 µA/oC
Full Scale Output Current, I

FS

- 20.48 - mA

Output Voltage Compliance Range (Note 3) -1.25 - 0 V

DYNAMIC CHARACTERISTICS

Throughput Rate (Note 3) 100 - - MSPS
Output Voltage Full Scale Step

Settling Time, t

SETT

, Full Scale

To ±0.5 LSB Error Band RL = 50Ω

(Note 3)

-20- ns

Singlet Glitch Area, GE (Peak) RL = 50Ω (Note 3) - 5 - pV-s
Doublet Glitch Area, (Net) - 3 - pV-s
Output Slew Rate RL = 50Ω, DAC Operating in Latched Mode (Note 3) - 1,000 - V/µs
Output Rise Time RL = 50Ω, DAC Operating in Latched Mode (Note 3) - 675 - ps
Output Fall Time RL = 50Ω, DAC Operating in Latched Mode (Note 3) - 470 - ps
Spurious Free Dynamic Range within a Window

(Note 3)

Spurious Free Dynamic Range to Nyquist
(Note 3)

f

= 10 MSPS, f

CLK

f

= 20 MSPS, f

CLK

f

= 40 MSPS, f

CLK

f

= 50 MSPS, f

CLK

f

= 80 MSPS, f

CLK

f

= 100 MSPS, f

CLK

f

= 40 MSPS, f

CLK

f

= 80 MSPS, f

CLK

f

= 100 MSPS, f

CLK

= 1.23MHz, 2MHz Span - 85 - dBc

OUT

= 5.055MHz, 2MHz Span - 77 - dBc

OUT

= 16MHz, 10MHz Span - 75 - dBc

OUT

= 10.1MHz, 2MHz Span - 80 - dBc

OUT

= 5.1MHz, 2MHz Span - 78 - dBc

OUT

= 10.1MHz, 2MHz Span - 79 - dBc

OUT

= 2.02MHz, 20MHz Span - 70 - dBc

OUT

= 2.02MHz, 40MHz Span - 70 - dBc

OUT

= 2.02MHz, 50MHz Span - 69 - dBc

OUT

REFERENCE/CONTROL AMPLIFIER

Internal Reference Voltage, V

REF

(Note 4) -1.27 -1.23 -1.17 V
Internal Reference Voltage Drift (Note 3) - 175 - µV/oC
Internal Reference Output Current Sink/Source

(Note 3) -125 - +50 µA
Capability

3-3

HI5731

Electrical Specifications AV

, DVEE = -4.94 to -5.46V, VCC = +4.75 to +5.25V, V

EE

= Internal

REF

TA = 25oC for All Typical Values (Continued)

HI5731BI

TA = -40oC TO 85oC

PARAMETER TEST CONDITIONS

Internal Reference Load Regulation I

REF

= 0 to I

= -125µA - 50 - µV

REF

UNITSMIN TYP MAX

Input Impedance at REF OUT pin (Note 3) - 1.4 - kΩ
Amplifier Large Signal Bandwidth (0.6V
Amplifier Small Signal Bandwidth (0.1V

) Sine Wave Input, to Slew Rate Limited (Note 3) - 3 - MHz

P-P

) Sine Wave Input, to -3dB Loss (Note 3) - 10 - MHz

P-P

Reference Input Impedance (Note 3) - 12 - kΩ
Reference Input Multiplying Bandwidth (CTL IN) RL = 50Ω, 100mV Sine Wave, to -3dB Loss at I

OUT

- 200 - MHz

(Note 3)

DIGITAL INPUTS (D9-D0, CLK, INVERT)

Input Logic High Voltage, V
Input Logic Low Voltage, V
Input Logic Current, I
Input Logic Current, I

IH
IL

Digital Input Capacitance, C

IH

IL

IN

(Note 4) 2.0 - - V

(Note 4) - - 0.8 V

(Note 4) - - 400 µA

(Note 4) - - 700 µA

(Note 3) - 3.0 - pF

TIMING CHARACTERISTICS

Data Setup Time, t
Data Hold Time, t

SU

HLD

Propagation Delay Time, t
CLK Pulse Width, t

PW1

, t

PD

PW2

See Figure 1 (Note 3) 3.0 2.0 - ns

See Figure 1 (Note 3) 0.5 0.25 - ns

See Figure 1 (Note 3) - 4.5 - ns

See Figure 1 (Note 3) 3.0 - - ns

POWER SUPPLY CHARACTERISTICS

I

EEA

I

EED

I

CCD

(Note 4) - 42 50 mA

(Note 4) - 70 85 mA

(Note 4) - 13 20 mA
Power Dissipation (Note 4) - 650 - mW
Power Supply Rejection Ratio VCC±5%, VEE±5% - 5 - µA/V

NOTES:

2. Gain Error measured as the error in the ratio between the full scale output current and the current through R

(typically 1.28mA). Ideally the

SET

ratio should be 16.

3. Parameter guaranteed by design or characterization and not production tested.

4. All devices are 100% tested at 25oC. 100% production tested at temperature extremes for military temperature devices, sample tested for
industrial temperature devices.

5. Dynamic Range must be limited to a 1V swing within the compliance range.

Timing Diagrams

CLK

D11-D0

I

OUT

t

t

PD

SETT

FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM FIGURE 2. PEAK GLITCHAREA (SINGLET) MEASUREMENT

3-4

50%

±1/2 LSB ERROR BAND

V

METHOD

WIDTH (W)

GLITCH AREA =

HEIGHT (H)

1

/2 (H x W)

t(ps)

Timing Diagrams (Continued)

HI5731

HLD

t

PW2

t

SU

t

HLD

t

PD

t

SU

t

HLD

t

PD

CLK

D11-D0

I

OUT

t

PW1

t

SU

t

t

PD

FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM

50%

Typical Performance Curves

680

CLOCK FREQUENCY DOES NOT

ALTER POWER DISSIPATION

640

(mW)

600

560

-50 -30 -10 10 30 50 70 90
TEMPERATURE

FIGURE 4. TYPICAL POWER DISSIPATION OVER

TEMPERATURE

-1.21

-1.23

-1.25

(V)

-1.27

-1.29

-50 -30 -10 10 30 50 70 90
TEMPERATURE

FIGURE 5. TYPICAL REFERENCE VOLTAGE OVER

TEMPERATURE

3-5