Intersil Corporation HI5662 Datasheet

HI5662

Data Sheet February 1999 File Number 4317.2

Dual 8-Bit, 60MSPS A/D Converter with
Internal Voltage Reference

The HI5662 is a monolithic, dual 8-Bit, 60MSPS analog-to­digital converter fabricated in an advanced CMOS process.
It is designed for high speed applications where integration,
bandwidth and accuracy are essential. The HI5662 reaches
a new level of multi-channel integration. The fully pipeline
architecture and an innovativeinputstageenable the HI5662
to accept a variety of input configurations, single-ended or
fully differential. Only one external clock is necessary to
drive both converters and an internal band-gap voltage
reference is provided. This allows the system designer to
realize an increased level of system integration resulting in
decreased cost and power dissipation.

The HI5662 has excellent dynamic performance while
consuming only 650mW power at 60MSPS. The A/D only
requires a single +5V power supply and encode clock. Data
output latches are provided which present valid data to the
output bus with a latency of 6 clock cycles.

For those customers needing dual channel 10-bit resolution,
please refer to the HI5762. For single channel 10-bit
applications, please refer to the HI5767.

Ordering Information

Features

• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .60MSPS

• 7.8 Bits at f

= 10MHz

IN

• Low Power at 60MSPS. . . . . . . . . . . . . . . . . . . . . 650mW

• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz

• Excellent Channel-to-Channel Isolation. . . . . . . . . >75dB

• On-Chip Sample and Hold Amplifiers

• Internal Band-Gap Voltage Reference . . . . . . . . . . . . 2.5V

• Fully Differential or Single-Ended Analog Inputs

• Single Supply Voltage Operation . . . . . . . . . . . . . . . . +5V

• TTL/CMOS Compatible Digital Inputs

• CMOS Compatible Digital Outputs. . . . . . . . . . . . 3.0/5.0V

• Offset Binary Digital Data Output Format

• Dual 8-Bit A/D Converters on a Monolithic Chip

Applications

• Wireless Local Loop

• PSK and QAM I and Q Demodulators

• Medical Imaging

PART

NUMBER

TEMP.

RANGE (oC) PACKAGE PKG. NO.

HI5662/6IN -40 to 85 44 Ld MQFP Q44.10x10
HI5662EVAL2 25 Evaluation Platform

• High Speed Data Acquisition

Pinout

HI5662

(MQFP)

TOP VIEW

AV

DV

A

D

GND

CC2

ID7
ID6
ID5
ID4
ID3

CC3

GND

ID2
ID1

DC

IV

44 43 42 41 40

1

2
3
4
5
6
7
8
9

10
11

12 13 14 15 16 17

IN-IIN+

I

GND

RIN

A

V

39 38 37 36 35 34

NC

ROUT

V

CC1

AV

IN+QIN-

Q

DC

QV

33
32
31
30
29

28
27
26
25
24
23

2221201918

A

GND

AV
QD7
QD6
QD5
QD4
QD3
DV
D

GND

QD2
QD1

CC2

CC3

10

NC

NC

ID0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

CC1

GND

CLK

D

DV

| Copyright © Intersil Corporation 1999

CC2

DV

GND

D

NC

NC

QD0

Functional Block Diagram

HI5662

I/QIN-

I/Q

BIAS

+

IN

S/H

STAGE 1

X2

2-BIT

FLASH

+

∑

-

STAGE M-1

2-BIT

FLASH

+

∑

-

2-BIT

DAC

DIGITAL DELAY

AND

DIGITAL ERROR

CORRECTION

2-BIT

DAC

I/QV

DC

DV

CC3

I/QD7 (MSB)

I/QD6

I/QD5

I/QD4

I/QD3

I/QD2

I/QD1

I/QD0 (LSB)

V

REFOUT

V

REFIN

X2

REFERENCE

11

2-BIT

FLASH

AV

CC1,2

STAGE M

AGND DV

CC1,2

DGND

CLOCK

I or Q CHANNEL

CLK

Typical Application Schematic

HI5662

HI5662

+

I

IN

IIN-

Q

+

IN

-

Q

IN

0.1µF

+

(42) I

IN

(44) IV

DC

(43) IIN-

+

(36) Q

IN

(34) QV

DC

(35) QIN-

(40) V

RIN

(38) V

ROUT

(13,14,20,21,39) NC

(LSB) ID0 (12)

ID1 (11)
ID2 (10)
ID3 (7)
ID4 (6)
ID5 (5)
ID6 (4)

(MSB) ID7 (3)

(LSB) QD0 (22)

QD1 (23)
QD2 (24)
QD3 (27)
QD4 (28)
QD5 (29)
QD6 (30)

(MSB) QD7 (31)

CLK (17)

DV

(8,26)

CC3

ID0
ID1
ID2
ID3
ID4
ID5
ID6
ID7

QD0
QD1
QD2
QD3
QD4
QD5
QD6
QD7

0.1µF10µF

+

CLOCK

+5V or +3V

+5V

10µF

(37) AV

CC1

(2,32) AV

+

0.1µF

AGND

BNC

CC2

(1,33,41) AGND

DGND

DV

(18)

CC2

DV

(16)

CC1

DGND (9,15,19,25)

10µF AND 0.1µF CAPS
ARE PLACED AS CLOSE
TO PART AS POSSIBLE

0.1µF10µF

+

+5V

12

Pin Descriptions

HI5662

PIN NO. NAME DESCRIPTION

1A
2AV

GND

CC2

Analog Ground

Analog Supply (+5.0V)
3 ID7 I-Channel, Data Bit 7 Output (MSB)
4 ID6 I-Channel, Data Bit 6 Output
5 ID5 I-Channel, Data Bit 5 Output
6 ID4 I-Channel Data Bit 4 Output
7 ID3 I-Channel, Data Bit 3 Output
8DV

CC3

Digital Output Supply

(+3.0V or +5.0V)
9D

GND

Digital Ground

10 ID2 I-Channel, Data Bit 2 Output
11 ID1 I-Channel, Data Bit 1 Output
12 ID0 I-Channel, Data Bit 0 Output (LSB)
13 NC No Connect
14 NC No Connect
15 D
16 DV

GND

CC1

Digital Ground

Digital Supply (+5.0V)

17 CLK Sample Clock Input
18 DV
19 D

CC2

GND

Digital Supply (+5.0V)

Digital Ground

20 NC No Connect
21 NC No Connect
22 QD0 Q-Channel, Data Bit 0 Output(LSB)
23 QD1 Q-Channel, Data Bit 1 Output

PIN NO. NAME DESCRIPTION

24 QD2 Q-Channel, Data Bit 2 Output
25 D
26 DV

GND

CC3

Digital Ground
Digital Output Supply

(+3.0V or +5.0V)
27 QD3 Q-Channel, Data Bit 3 Output
28 QD4 Q-Channel, Data Bit 4 Output
29 QD5 Q-Channel, Data Bit 5 Output
30 QD6 Q-Channel, Data Bit 6 Output
31 QD7 Q-Channel, Data Bit 7 Output

(MSB)
32 AV
33 A
34 QV
35 Q
36 Q
37 AV
38 V

CC2

GND

DC

IN-

IN+

CC1

ROUT

Analog Supply (+5.0V)

Analog Ground

Q-Channel DC Bias Voltage Output

Q-Channel Negative Analog Input

Q-Channel Positive Analog Input

Analog Supply (+5.0V)

+2.5V Reference Voltage Output
39 NC No Connect
40 V
41 A
42 I
43 I
44 IV

RIN

GND

IN+

IN-

DC

+2.5V Reference Voltage Input

Analog Ground

I-Channel Positive Analog Input

I-Channel Negative Analog Input

I-Channel DC Bias Voltage Output

13

HI5662

Absolute Maximum Ratings T

Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .6V

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V

Digital I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DV

Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AV

Operating Conditions

Temperature Range

HI5662/6IN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications AV

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ACCURACY

Resolution 8 - - Bits
Integral Linearity Error, INL f
Differential Linearity Error, DNL

(Guaranteed No Missing Codes)
Offset Error, V
Full Scale Error, FSE fIN = DC - 1 - LSB

DYNAMIC CHARACTERISTICS

Minimum Conversion Rate No Missing Codes - 1 - MSPS
Maximum Conversion Rate No Missing Codes 60 - - MSPS
Effective Number of Bits, ENOB fIN = 10MHz

Signal to Noise and Distortion Ratio, SINAD fIN = 10MHz - 48.7 - dB

--------------------------------------------------------------=

RMS Noise + Distortion

OS

RMS Signal

=25oC Thermal Information

A

Thermal Resistance (Typical, Note 1) θJA (oC/W)

HI5662/6IN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

CC
CC

= DV

CC1,2

= 10pF; TA = 25oC; Differential Analog Input; Unless Otherwise Specified

C

L

= +5.0V, DV

CC1,2

= 10MHz - 0.5 - LSB

IN

fIN = 10MHz - ±0.2 ±1.0 LSB

fIN = DC -10 - +10 LSB

fIN = 10MHz, Single Ended Analog Input

CC3

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(Lead Tips Only)

= +3.0V; V

= 2.50V; fS = 60MSPS at 50% Duty Cycle;

RIN

7.5

7.0

7.8

7.7

-

-

Bits
Bits

Signal to Noise Ratio, SNR f

RMS Signal

-------------------------------=

RMS Noise

Total Harmonic Distortion, THD fIN = 10MHz - -66 - dBc
2nd Harmonic Distortion fIN = 10MHz - -71 - dBc
3rd Harmonic Distortion fIN = 10MHz - -71 - dBc
Spurious Free Dynamic Range, SFDR fIN = 10MHz - 71 - dBc
Intermodulation Distortion, IMD f1 = 1MHz, f2 = 1.02MHz - 64 - dBc
I/Q Channel Crosstalk - -75 -60 dBc
I/Q Channel Offset Match - 2.5 - LSB
I/Q Channel Full Scale Error Match - 2.5 - LSB
Transient Response (Note 2) - 1 - Cycle
Over-Voltage Recovery 0.2V Overdrive (Note 2) - 1 - Cycle

= 10MHz - 48 - dB

IN

14