intersil HI-546, HI-547, HI-548, HI-549 DATA SHEET

®

www.BDTIC.com/Intersil

HI-546, HI-547, HI-548, HI-549

Data Sheet September 21, 2005

Single 16 and 8, Differential 8-Channel
and 4-Channel CMOS Analog MUXs with
Active Overvoltage Protection

The HI-546, HI-547, HI-548 and HI-549 are analog
multiplexers with active overvoltage protection and
guaranteed r
exceed either power supply without damaging the device or
disturbing the signal path of other channels. Active
protection circuitry assures that signal fidelity is maintained
even under fault conditions that would destroy other
multiplexers.

Analog inputs can withstand constant 70V
±15V supplies. Digital inputs will also sustain continuous
faults up to 4V greater than either supply. In addition, signal
sources are protected from short circuiting should
multiplexer supply loss occur. Each input presents 1kΩ of
resistance under this condition. These features make the
HI-546, HI-547, HI-548 and HI-549 ideal for use in systems
where the analog inputs originate from external equipment
or separately powered circuitry. All devices are fabricated
with 44V Dielectrically Isolated CMOS technology. The
HI-546 is a single 16-Channel, the HI-547 is an 8-Channel
differential, the HI-548 is a single 8-Channel and the HI-549
is a 4-Channel differential device. If input overvoltage
protection is not needed the HI-506/507/508/509
multiplexers are recommended. For further information see
Application Notes AN520 and AN521.

matching. Analog input levels may greatly

ON

levels with

P-P

FN3150.5

Features

• Analog Overvoltage Protection. . . . . . . . . . . . . . . . . . 70V

• No Channel Interaction During Overvoltage

• Guaranteed r

• Maximum Power Supply. . . . . . . . . . . . . . . . . . . . . . . 44V

• Break-Before-Make Switching

• Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V

• Access Time (Typical) . . . . . . . . . . . . . . . . . . . . . . . 500ns

• Standby Power (Typical). . . . . . . . . . . . . . . . . . . . . 7.5mW

• Pb-Free Plus Anneal Available (RoHS Compliant)

Matching

ON

P-P

Applications

• Data Acquisition

• Industrial Controls

• Telemetry

For MIL-STD-883 compliant parts, request the HI-546/883,
HI-547/883, HI-548/883 and HI-549/883 datasheets.

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright © Intersil Americas Inc. 2003, 2005. All Rights Reserved

HI-546, HI-547, HI-548, HI-549

www.BDTIC.com/Intersil

Ordering Information

TEMP.

PART

NUMBER

PART

MARKING

RANGE

o

C) PACKAGE

(

HI1-0546-5 HI1-546-5 0 to 75 28 Ld CERDIP F28.6
HI1-0546-2 HI1-546-2 -55 to 125 28 Ld CERDIP F28.6
HI3-0546-5 HI3-546-5 0 to 75 28 Ld PDIP E28.6
HI4P0546-5 HI4P546-5 0 to 75 28 Ld PLCC N28.45
HI4P0546-5Z

(Note)

HI4P546-5Z 0 to 75 28 Ld PLCC

(Pb-free)
HI9P0546-9** HI9P546-9 -40 to 85 28 Ld SOIC M28.3
HI9P0546-9Z**

(Note)

HI9P546-9Z -40 to 85 28 Ld SOIC

(Pb-free)
HI1-0547-5 HI1-547-5 0 to 75 28 Ld CERDIP F28.6
HI3-0547-5 HI3-547-5 0 to 75 28 Ld PDIP E28.6
HI3-0547-5Z

(Note)

HI3-0547-5Z 0 to 75 28 Ld PDIP*

(Pb-free)
HI4P0547-5 HI4P547-5 0 to 75 28 Ld PLCC N28.45
HI4P0547-5Z

(Note)

HI4P547-5Z 0 to 75 28 Ld PLCC

(Pb-free)
HI9P0547-9 HI9P547-9 -40 to 85 28 Ld SOIC M28.3
HI9P0547-9Z

(Note)

HI9P547-9Z -40 to 85 28 Ld SOIC

(Pb-free)
HI1-0548-2 HI1-548-2 -55 to 125 16 Ld CERDIP F16.3
HI1-0548-5 HI1-548-5 0 to 75 16 Ld CERDIP F16.3
HI3-0548-5 HI3-548-5 0 to 75 16 Ld PDIP E16.3
HI4P0548-5 HI4P548-5 0 to 75 20 Ld PLCC N20.35

PKG.

DWG. #

N28.45

M28.3

E28.6

N28.45

M28.3

Ordering Information (Continued)

TEMP.

PART

NUMBER

PART

MARKING

RANGE

o

C) PACKAGE

(

HI9P0548-5** HI9P548-5 0 to 75 16 Ld SOIC M16.15
HI9P0548-5Z**

(Note)

HI9P548-5Z 0 to 75 16 Ld SOIC

(Pb-free)
HI9P0548-9 HI9P548-9 -40 to 85 16 Ld SOIC M16.15
HI9P0548-9Z

(Note)

HI9P548-9Z -40 to 85 16 Ld SOIC

(Pb-free)
HI1-0549-2 HI1-549-2 -55 to 125 16 Ld CERDIP F16.3
HI3-0549-5 HI3-549-5 0 to 75 16 Ld PDIP E16.3
HI4P0549-5 HI4P549-5 0 to 75 20 Ld PLCC N20.35
HI4P0549-5Z

(Note)

HI4P549-5Z 0 to 75 20 Ld PLCC

(Pb-free)
HI9P0549-9 HI9P549-9 -40 to 85 16 Ld SOIC M16.15
HI9P0549-9Z

(Note)

HI9P549-9Z -40 to 85 16 Ld SOIC

(Pb-free)
*Pb-free PDIPs can be used for through hole wave solder processing

only. They are not intended for use in Reflow solder processing
applications.

**Add “96” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

PKG.

DWG. #

M16.15

M16.15

N20.35

M16.15

Pinouts

ADDRESS A

HI-546 (CERDIP, PDIP, SOIC)

TOP VIEW

+V

SUPPLY

NC

NC
IN 16
IN 15
IN 14
IN 13
IN 12
IN 11
IN 10

IN 9

GND

V

REF

1
2
3
4
5
6
7
8

9
10
11
12
13
14

3

HI-547 (CERDIP, PDIP, SOIC)

TOP VIEW

28

OUT

28

-V

27

SUPPLY

26

IN 8

25

IN 7

24

IN 6
IN 5

23

IN 4

22
21

IN 3

20

IN 2

19

IN 1
ENABLE

18

ADDRESS A

17
16

ADDRESS A
ADDRESS A

15

+V

SUPPLY

0
1
2

OUT B

NC
IN 8B
IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
IN 2B
IN 1B

GND

V

REF

NC

1
2
3
4
5
6
7
8

9
10
11
12
13
14

OUT A

-V

27

SUPPLY

IN 8A

26

IN 7A

25

IN 6A

24

IN 5A

23

IN 4A

22

IN 3A

21
20

IN 2A
IN 1A

19

ENABLE

18

ADDRESS A

17
16

ADDRESS A
ADDRESS A

15

0
1
2

2

Pinouts (Continued)

www.BDTIC.com/Intersil

HI-546 (PLCC)

TOP VIEW

HI-546, HI-547, HI-548, HI-549

HI-547 (PLCC)

TOP VIEW

IN 15
IN 14
IN 13
IN 12
IN 11
IN 10

IN 9

IN 16NCNC

5
6
7
8

9
10
11

12 13 14 15 16 17 18

A3A2A

REF

GND

V

HI-548 (CERDIP, PDIP, SOIC)

TOP VIEW

1

A

0

IN 1
IN 2
IN 3
IN 4

OUT

2
3
4
5
6
7
8

ENABLE

-V

SUPPLY

SUPPLY

+V

1234

OUT

1

SUPPLY

-V

IN 8

262728

5

25

IN 7

24

IN 6

23

IN 5

22

IN 4

21

IN 3

20

IN 2

19

IN 1

0

A

ENABLE

IN 7B
IN 6B
IN 5B
IN 4B
IN 3B
IN 2B
IN 1B

6
7
8

9
10
11

IN 8B

NC

12 13 14 15 16 17 18

GND

V

SUPPLY

OUT B

+V

1234

2A1

A

NC

REF

SUPPLY

OUT A

-V

IN 8A

262728

25

IN 7A

24

IN 6A

23

IN 5A

22

IN 4A

21

IN 3A

20

IN 2A

19

IN 1A

0

A

ENABLE

HI-549 (CERDIP, PDIP, SOIC)

TOP VIEW

16

A

1

A

15

2

14

GND
+V

13

SUPPLY

12

IN 5
IN 6

11

IN 7

10

9

IN 8

ENABLE

-V

SUPPLY

A

IN 1A
IN 2A
IN 3A
IN 4A

OUT A

1

0

2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

A

1

GND
+V

SUPPLY

IN 1B
IN 2B
IN 3B
IN 4B
OUT B

HI-548 (PLCC)

TOP VIEW

A1A

193 2 201

IN 8

2

IN 7

-V

18

GND

17

+V

SUPPLY

16

NC

15

IN 5

14

IN 6

SUPPLY

IN 1A

NC

IN 2A
IN 3A

-V

SUPPLY

IN 1

NC
IN 2
IN 3

ENABLE

A0NC

4
5
6
7
8

9

10 11 12 13

IN 4

NC

OUT

3

HI-549 (PLCC)

TOP VIEW

ENABLE

A0NC

4
5
6
7
8

9

10 11 12 13

IN 4A

OUT A

NC

A1GND

193 2 201

IN 4B

OUT B

+V

18

SUPPLY

IN 1B

17

NC

16

IN 2B

15
14

IN 3B

HI-546, HI-547, HI-548, HI-549

www.BDTIC.com/Intersil

TRUTH TABLE HI-546

A

A

3

A

2

A

1

EN “ON” CHANNEL

0

XXXXL None
LLLLH 1
LLLHH 2
LLHLH 3
LLHHH 4
LHLLH 5
LHLHH 6
LHHLH 7
LHHHH 8
HLLLH 9
HLLHH 10
HLHLH 11
HLHHH 12
HHL LH 13
HHLHH 14
HHHLH 15
HHHHH 16

TRUTH TABLE HI-547

A

A

2

A

1

EN “ON” CHANNEL PAIR

0

X X X L None
LLLH 1
LLHH 2
LHLH 3
LHHH 4

TRUTH TABLE HI-547 (Continued)

A

A

2

A

1

EN “ON” CHANNEL PAIR

0

HLLH 5
HLHH 6
HHLH 7
HHHH 8

TRUTH TABLE HI-548

A

A

2

A

1

EN “ON” CHANNEL

0

X X X L None
LLLH 1
LLHH 2
LHLH 3
LHHH 4
HLLH 5
HLHH 6
HHLH 7
HHHH 8

TRUTH TABLE HI-549

A

1

A

0

EN “ON” CHANNEL PAIR

X X L None
LLH 1
LHH 2
HLH 3
HHH 4

Functional Diagrams

HI-546 HI-547

IN 1

IN 2

IN 16

1K

1K

1K

OVERVOLTAGE

CLAMP AND

SIGNAL

ISOLATION

† DIGITAL INPUT

PROTECTION

5V

REF

DECODER/

DRIVER

LEVEL
SHIFT

† † † †

V

REFA0A1A2

OUT

IN 1A

IN 8A
IN 1B

IN 8B

†

EN

A

3

1K

1K
1K

1K

OVERVOLTAGE

CLAMP AND

ISOLATION

† DIGITAL INPUT

PROTECTION

4

SIGNAL

5V

REF

DECODER/

DRIVER

LEVEL

SHIFT

† † †

V

REFA0A1A2

EN

OUT

A

OUT

B

†

Functional Diagrams (Continued)

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HI-548 HI-549

HI-546, HI-547, HI-548, HI-549

IN 1

IN 2

IN 8

1K

1K

1K

OVERVOLTAGE

CLAMP AND

SIGNAL

ISOLATION

5V

REF

† DIGITAL INPUT

PROTECTION

Schematic Diagrams

EN

OUT

A

OUT

B

†

DECODER/

DRIVER

LEVEL
SHIFT

† † †

A

0A1A2

EN

OUT

IN 1A

IN 4A
IN 1B

IN 4B

†

1K

1K
1K

1K

OVERVOLTAGE

CLAMP AND

SIGNAL

ISOLATION

† DIGITAL INPUT

PROTECTION

5V

REF

DECODER/

DRIVER

LEVEL

SHIFT

† †

A

0

A

1

ADDRESS DECODER

V+

P

PP PP P P

A3 OR A

ENABLE
DELETE A

DELETE A

OR A

A

0

OR A

A

1

1

A2 OR A

2

3

OR A3 INPUT FOR HI-547, HI-548, HI-549

3

OR A2 INPUT FOR HI-549

2

TO P-CHANNEL

N

0

N

N

N

N

NN

V-

DEVICE OF
THE SWITCH

TO N-CHANNEL
DEVICE OF
THE SWITCH

5

Schematic Diagrams (Continued)

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FROM

DECODE

OVERVOLTAGE PROTECTION

HI-546, HI-547, HI-548, HI-549

MULTIPLEX SWITCH

N

V+

IN

FROM

DECODE

R11

1K

P

D6 D7

Q6

Q5

D4 D5

N

V-

N

P

OUT

6

Schematic Diagrams (Continued)

www.BDTIC.com/Intersil

TTL REFERENCE

CIRCUIT

V+

R10

R9

V

REF

Q1

Q4

D3

GND

HI-546, HI-547, HI-548, HI-549

ADDRESS INPUT BUFFER AND LEVEL SHIFTER

LEVEL SHIFTER

V+

OVERVOLTAGE

PROTECTION

V+

D2

R1

D1

200

Ω

V-

ADD

IN

P

P

N

N

P

P

R2

R3

N

N

R4

GND

P

N

P P

N

P

R5 R7

R6
N

R8

N

P

N

V-

P

LEVEL
SHIFTED
ADDRESS
TO
DECODE

N

7

HI-546, HI-547, HI-548, HI-549

www.BDTIC.com/Intersil

Absolute Maximum Ratings Thermal Information

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44V

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+22V

V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V

Digital Input Voltage (V
Analog Signal (V

Continuous Current, IN or OUT . . . . . . . . . . . . . . . . . . . . . . . . 20mA

Peak Current, IN or OUT (Pulsed 1ms, 10% Duty Cycle Max). . 40mA

IN

, VA) . . . . . . . . . . . . . (V-) -4V to (V+) +4V

EN

, V

). . . . . . . . . . . . . . . (V-) -20V to (V+) +20V

OUT

or 20mA, Whichever Occurs First

Operating Conditions

Temperature Ranges

HI-546/548/549-2 . . . . . . . . . . . . . . . . . . . . . . . . . -55

HI-546/547/548/549-5 . . . . . . . . . . . . . . . . . . . . . . . 0

HI-546/547/548/549-9 . . . . . . . . . . . . . . . . . . . . . . -40

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied .

NOTE:

1. θ

is measured with the component mounted on an evaluation PC board in free air.

JA

o

C to 125oC

o

C to 75oC

o

C to 85oC

Thermal Resistance (Typical, Note 1) θ

16 Ld CERDIP Package. . . . . . . . . . . 85 32

28 Ld CERDIP Package. . . . . . . . . . . 55 18

28 Ld PDIP Package*. . . . . . . . . . . . . 60 N/A

16 Ld PDIP Package . . . . . . . . . . . . . 90 N/A

28 Ld PLCC Package. . . . . . . . . . . . . 70 N/A

20 Ld PLCC Package. . . . . . . . . . . . . 80 N/A

28 Ld SOIC Package . . . . . . . . . . . . . 75 N/A

16 Ld SOIC Package . . . . . . . . . . . . . 105 N/A

Maximum Junction Temperature

Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175

Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Maximum Storage Temperature Range. . . . . . . . . . -65

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300

(PLCC, SOIC - Lead Tips Only)

*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.

(oC/W) θJC (oC/W)

JA

o

C to 150oC

o
o

o

C
C

C

Electrical Specifications Supplies = +15V, -15V; V

Otherwise Specified. For Test Conditions, Consult Test Circuits Section

TEST

PARAMETER

SWITCHING CHARACTERISTICS

Access Time, t

Break-Before Make Delay, t
Enable Delay (ON), t

Enable Delay (OFF), t

Settling Time To 0.1% 25 - 1.2 - - 1.2 - µs

Off Isolation Note 6 25 50 68 - 50 68 - dB
Channel Input Capacitance, C
Channel Output Capacitance C

HI-546 25 - 52 - - 52 - pF
HI-547 25 - 30 - - 30 - pF
HI-548 25 - 25 - - 25 - pF
HI-549 25 - 12 - - 12 - pF

Input to Output Capacitance, C

DIGITAL INPUT CHARACTERISTICS

Input Low Threshold, TTL Drive, V
Input High Threshold, V
MOS Drive, V

A

OPEN

ON(EN)

OFF(EN)

S(OFF)

D(OFF)

DS(OFF)

AL

(Note 8) Full 4.0 - - 4.0 - - V

AH

(HI-546/547 Only) V

AL

CONDITIONS

To 0.01% 25 - 3.5 - - 3.5 - µs

= 10V 25 - - 0.8 - - 0.8 V

REF

Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V; Unless

REF

TEMP

o

C)

(

25 - 0.5 - - 0.5 - µs

Full - - 1.0 - - 1.0 µs

25 25 80 - 25 80 - ns
25 - 300 500 - 300 - ns

Full - - 1000 - - 1000 ns

25 - 300 500 - 300 - ns

Full - - 1000 - - 1000 ns

25-10- -10-pF

25 - 0.1 - - 0.1 - pF

Full - - 0.8 - - 0.8 V

-2 -5, -9
UNITSMIN TYP MAX MIN TYP MAX

8

HI-546, HI-547, HI-548, HI-549

www.BDTIC.com/Intersil

Electrical Specifications Supplies = +15V, -15V; V

Otherwise Specified. For Test Conditions, Consult Test Circuits Section (Continued)

PARAMETER

MOS Drive, V
Input Leakage Current (High or Low), I

ANALOG CHANNEL CHARACTERISTICS

Analog Signal Range, V
On Resistance, r

∆r

, (Any Two Channels) 25 - - 7.0 - - 7.0 %

ON

Off Input Leakage Current, I

Off Output Leakage Current, I

HI-546 Full - - 300 - - 300 nA
HI-547 Full - - 200 - - 200 nA
HI-548 Full - - 200 - - 200 nA
HI-549 Full - - 100 - - 100 nA

I

With Input Overvoltage Applied Note 4 25 - 4.0 - - 4.0 - nA

D(OFF)

On Channel Leakage Current, I

HI-546 Full - - 300 - - 300 nA
HI-547 Full - - 200 - - 200 nA
HI-548 Full - - 200 - - 200 nA
HI-549 Full - - 100 - - 100 nA

Differential Off Output Leakage Current

(HI-547, HI-549 Only)

I

DIFF

POWER SUPPLY CHARACTERISTICS

Power Dissipation, P
Current, I+ Note 7 Full - 0.5 2.0 - 0.5 2.0 mA
Current, I- Note 7 Full - 0.02 1.0 - 0.02 1.0 mA

NOTES:

2. V

OUT

3. 10nA is the practical lower limit for high speed measurement in the production test environments.

4. Analog Overvoltage = ±33V.

5. Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25
= 0.8V, RL = 1K, CL = 15pF, VS = 7V

6. V

EN

7. V

, VA = 0V or 4V.

EN

8. To drive from DTL/TTLCircuits, 1kΩ pull-up resistors to +5V supply are recommended.

(HI-546/547 Only) V

AH

IN

ON

D

= ±10V, I

= 100µA.

OUT

±

A

S(OFF)

D(OFF)

D(ON)

TEST

CONDITIONS

= 10V 25 6.0 - - 6.0 - - V

REF

Note 5 Full - - 1.0 - - 1.0 µA

Note 2 25 - 1.2 1.5 - 1.5 1.8 kΩ

Note 3 25 - 0.03 - - 0.03 - nA

Note 3 25 - 0.1 - - 0.1 - nA

Note 3 25 - 0.1 - - 0.1 - nA

, f = 100kHz.

RMS

Pin = Open; VAH (Logic Level High) = 4V; VAL (Logic Level Low) = 0.8V; Unless

REF

TEMP

o

(

C)

Full -15 - +15 -15 - +15 V

Full - 1.5 1.8 - 1.8 2.0 kΩ

Full - - 50 - - 50 nA

Full--2.0---µA

Full - - 50 - - 50 nA

Full - 7.5 - - 7.5 - mW

-2 -5, -9

o

C.

UNITSMIN TYP MAX MIN TYP MAX

9

HI-546, HI-547, HI-548, HI-549

www.BDTIC.com/Intersil

T est Circuits and W a veforms T

= 25oC, V

A

V

IN

SUPPLY

FIGURE 1A. ON RESISTANCE TEST CIRCUIT

1.4

1.3

1.2

1.1

1.0

0.9

ON RESISTANCE (kΩ)

0.8

0.7

0.6

-10-8-6-4-20246810

125oC

25oC

-55oC

ANALOG INPUT (V)

FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE

FIGURE 1. ON RESISTANCE

= ±15V, VAH = 4V, VAL = 0.8V, V

100µA

V

2

OUTIN

rON =

1.5

1.4

1.3

1.2

1.1

1.0

NORMALIZED ON RESIST ANCE

0.9

(REFERRED TO VALUE AT ±15V)

0.8
5 6 7 8 9 101112131415

FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY

= Open, Unless Otherwise Specified

REF

V

2

100µA

SUPPLY VOLTAGE (±V)

VOLTAGE

100nA

10nA

OFF OUTPUT

CURRENT
ON LEAKAGE
CURRENT

I

1nA

LEAKAGE CURRENT

100pA

10pA

D(ON)

25 50 75 100 125

TEMPERATURE (

I

D(OFF)

OFF INPUT

LEAKAGE CURRENT

I

S(OFF)

o

C)

±10V

FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE FIGURE 2B. I

10

TEST CIRCUIT (NOTE 9)

D(OFF)

EN

OUT

A

+0.8V

I

D(OFF)

±

10V

HI-546, HI-547, HI-548, HI-549

www.BDTIC.com/Intersil

T est Circuits and W avef orms T

I

A

S(OFF)

±10V

FIGURE 2C. I

±

10V

TEST CIRCUIT (NOTE 9) FIGURE 2D. I

S(OFF)

= 25oC, V

A

EN

= ±15V, VAH = 4V , VAL = 0.8V , V

SUPPLY

OUT

+0.8V

±

NOTE:

9. Two measurements per channel: ±10V and 10V. (Two measurements per device for I

±

FIGURE 2. LEAKAGE CURRENTS

18

ANALOG INPUT

15

12

9

6

3

ANALOG INPUT CURRENT (mA)

CURRENT (I

OUTPUT OFF LEAKAGE

CURRENT ID

IN

(OFF)

)

5

4

3

A

2

1

10V

I

IN

±V

IN

= Open, Unless Otherwise Specified (Continued)

REF

OUT

EN

4V

TEST CIRCUIT (NOTE 9)

D(ON)

: ±10V and 10V.)

D(OFF)

±

A

I

D(ON)

±10V

I

A

D(OFF)

0

15 18 21 24 27 30 33 36

ANALOG INPUT OVERVOLTAGE (±V)

FIGURE 3A. ANALOG INPUT CURRENT AND OUTPUT OFF

OUTPUT OFF LEAKAGE CURRENT (nA)

0

FIGURE 3B. TEST CIRCUIT
LEAKAGE CURRENT vs ANALOG INPUT
OVER-VOLTAGE

FIGURE 3. ANALOG INPUT OVERVOLTAGE CHARA CTERISTICS

±14

±12

±10

SWITCH CURRENT (mA)

±8

±6

±4

±2

0

2 4 6 8 10 12 14

0

VOLTAGE ACROSS SWITCH (±V)

-55oC
25oC

125oC

±V

IN

FIGURE 4A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 4B. TEST CIRCUIT

FIGURE 4. ON CHANNEL CURRENT

A

11

HI-546, HI-547, HI-548, HI-549

www.BDTIC.com/Intersil

T est Circuits and W avef orms T

8

6

V

4

2

SUPPLY CURRENT (mA)

0

1K

TOGGLE FREQUENCY (Hz)

SUPPLY

V

= ± 10V

SUPPLY

10K 100K 1M 10M

= ± 15V

= 25oC, V

A

= ±15V, VAH = 4V , VAL = 0.8V , V

SUPPLY

= Open, Unless Otherwise Specified (Continued)

REF

A

V+

A

3

HI-546

2

1

0

GND

†

THRU

IN 15

IN 16

V-

A

A

50Ω

V

A

+4V

Similar connection for HI-547/HI-548/HI-549.

†

A
A

EN

+15V/+10V

+I

IN 1

IN 2

OUT

-I

-15V/-10V

FIGURE 5A. SUPPLY CURRENT vs TOGGLE FREQUENCY FIGURE 5B. TEST CIRCUIT

FIGURE 5. DYNAMIC SUPPLY CURRENT

V+

IN 2 THRU

IN 15

HI-546

†

IN 16

OUT

V-

+15V

IN 1

-15V

900

800

700

600

500

ACCESS TIME (ns)

400

300

3

VA INPUT

V

= OPEN FOR LOGIC HIGH LEVEL < 6V

REF

V

= LOGIC HIGH FOR LOGIC HIGH LEVELS > 6V

REF

579 151311

4 6 8101214

LOGIC LEVEL (HIGH) (V)

2V/DIV.

S1 ON S16 ON

100ns/DIV.

V

REF

A

3

A

2

50Ω

V

A

OUTPUT

0.5V/DIV.

+4V

Similar connection for HI-547/HI-548/HI-549.

†

A
A

EN

1

0

GND

FIGURE 6A. ACCESS TIME vs LOGIC LEVEL (HIGH) FIGURE 6B. TEST CIRCUIT

SUPPLY

SUPPLY

±

10V

±10V/±5V

10V/±5V

10MΩ

±10V

10kΩ 50pF

±

14pF

VA INPUT
2V/DIV.

S1 ON

+10V

50%

t

A

VAH = 4.0V

10%

ADDRESS
DRIVE (V

OUTPUT

A

-10V

)

0V

FIGURE 6C. MEASUREMENT POINTS FIGURE 6D. WAVEFORMS

FIGURE 6. ACCESS TIME

12

200ns/DIV.

OUTPUT
5V/DIV.

S16 ON

HI-546, HI-547, HI-548, HI-549

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T est Circuits and W avef orms T

A

3

HI-546

†

A

2

50Ω

V

A

+4V

†

Similar connection for HI-547/HI-548/HI-549

A
A

EN

1

0

GND

FIGURE 7A. TEST CIRCUIT FIGURE 7B. MEASUREMENT POINTS

IN 1

IN 2 THRU

IN 15
IN 16

OUT

1kΩ

= 25oC, V

A

= ±15V, VAH = 4V , VAL = 0.8V , V

SUPPLY

+5V

V

OUT

50pF

= Open, Unless Otherwise Specified (Continued)

REF

VAH = 4V

ADDRESS

t

OPEN

DRIVE (V

0V

50% 50%

)

A

OUTPUT

A

3

HI-546

†

A

2

IN 2 THRU

A

1

A

0

EN

V

A

†

Similar connection for HI-547/HI-548/HI-549

50Ω

GND

FIGURE 8A. TEST CIRCUIT FIGURE 8B. MEASUREMENT POINTS

13

IN 1

IN16

OUT

FIGURE 7C. WAVEFORMS

FIGURE 7. BREAK-BEFORE-MAKE DELAY

+10V

V

OUT

1kΩ

50pF

50%

t

ON(EN)

VAH = 4V

90%

50%

t

OFF(EN)

ENABLE DRIVE
(VA)

0V

OUTPUT

10%

0V

HI-546, HI-547, HI-548, HI-549

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T est Circuits and W avef orms T

= 25oC, V

A

DISABLED

= ±15V, VAH = 4V , VAL = 0.8V , V

SUPPLY

ENABLE

DRIVE

2V/DIV.

OUTPUT

2V/DIV.

ENABLED (S1 ON)

100ns/DIV.

FIGURE 8C. WAVEFORMS

FIGURE 8. ENABLE DELAYS

= Open, Unless Otherwise Specified (Continued)

REF

14

Die Characteristics

www.BDTIC.com/Intersil

HI-546, HI-547, HI-548, HI-549

DIE DIMENSIONS:

83.9 mils x 159 mils

METALLIZATION:

Type: CuAl
Thickness: 16k

Å ±2kÅ

SUBSTRATE POTENTIAL (NOTE):

-V

SUPPLY

NOTE: The substrate appears resistive to the -V
conductor at -V

SUPPLY

potential.

Metallization Mask Layouts

HI-546 HI-547

EN

(18) (17) (16) (15) (13) (12)

A

0

A

A

2

1

A

(14)

V

REF

3

PASSIVATION:

Type: Nitride Over Silox
Nitride Thickness: 3.5kÅ ±1kÅ
Silox Thickness: 12kÅ ±2kÅ

WORST CASE CURRENT DENSITY:

5

2

1.4 x 10

A/cm

TRANSISTOR COUNT:

485

PROCESS:

CMOS-DI

terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a

SUPPLY

NC

GND

A

EN

(18) (17) (16) (15)

A

A

0

1

2

V

REF

(14)

(13) (12)

GND

IN 1
(19)

IN 2
(20)

IN 3
(21)

IN 4
(22)

IN 5
(23)

IN 6
(24)

IN 7
(25)

IN 8
(26)

V- (27) +V (1) NC (2)

OUT (28)

IN 9
(11)

IN 10

(10)

IN 11

(9)

IN 12

(8)

IN 13

(7)

IN 14

(6)

IN 15

(5)

IN 16

(4)

IN 1A

(19)

IN 2A

(20)

IN 3A

(21)

IN 4A

(22)

IN 5A

(23)

IN 6A

(24)

IN 7A

(25)

IN 8A

(26)

V- (27) +V (1) OUT B(2)

OUT A (28)

IN 1B

(11)

IN 2B

(10)

IN 3B

(9)

IN 4B

(8)

IN 5B

(7)

IN 6B

(6)

IN 7B

(5)

IN 8B

(4)

15

Die Characteristics

www.BDTIC.com/Intersil

HI-546, HI-547, HI-548, HI-549

DIE DIMENSIONS:

83 mils x 108 mils

METALLIZATION:

Type: CuAl
Thickness: 16k

Å ±2kÅ

SUBSTRATE POTENTIAL (NOTE):

-V

SUPPLY

NOTE: The substrate appears resistive to the -V
conductor at -V

SUPPLY

potential.

Metallization Mask Layouts

HI-548 HI-549

IN 6 IN 7 IN 8 OUT IN 4 IN 3
(11) (10) (9) (8) (7) (6)

PASSIVATION:

Type: Nitride Over Silox
Nitride Thickness: 3.5kÅ ±1kÅ
Silox Thickness: 12kÅ ±2kÅ

WORST CASE CURRENT DENSITY:

5

1.4 x 10

A/cm

TRANSISTOR COUNT:

253

PROCESS:

CMOS-DI

terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a

SUPPLY

IN 3B IN 4B OUT B OUT A IN 4AIN 3A

(11) (10) (9) (8) (7) (6)

IN 5
(12)

+V

(13)

GND

(14)

A

2

(15) (16) (1)

A

1

IN 2

(5)

IN 1

(4)

-V

(3)

A

EN

0

(2)

IN 2B

(12)

IN 1B

(13)

+V

(14)

GND

(15) (16) (1)

16

IN 2A

(5)

IN 1A

(4)

-V

(3)

A

A

1

EN

0

(2)

HI-546, HI-547, HI-548, HI-549

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17

HI-546, HI-547, HI-548, HI-549

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Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

LEAD FINISH

c1

-A-

-B-

bbb C A - B

S

BASE

PLANE

SEATING

PLANE

S1

b2

b

ccc C A - BMD

D

A

A

e

S

S

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat­ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.

5. This dimension allows for off-center lid, meniscus, and glass
overrun.

6. Dimension Q shall be measured from the seating plane to the
base plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

-D­BASE

E

D

S

S

Q

A

-C­L

METAL

b1

M

(b)

SECTION A-A

α

(c)

M

eA

eA/2

aaa CA - B

M

c

D

S

S

F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A)

28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.232 - 5.92 -

b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 ­b3 0.023 0.045 0.58 1.14 4

c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3

D - 1.490 - 37.85 5
E 0.500 0.610 12.70 15.49 5

e 0.100 BSC 2.54 BSC -

eA 0.600 BSC 15.24 BSC -

eA/2 0.300 BSC 7.62 BSC -

L 0.125 0.200 3.18 5.08 -

Q 0.015 0.060 0.38 1.52 6

S1 0.005 - 0.13 - 7

o

α

90

105

o

90

o

105
aaa - 0.015 - 0.38 ­bbb - 0.030 - 0.76 ­ccc - 0.010 - 0.25 -

M - 0.0015 - 0.038 2, 3
N28 288

NOTESMIN MAX MIN MAX

o

Rev. 0 4/94

-

18

HI-546, HI-547, HI-548, HI-549

www.BDTIC.com/Intersil

Dual-In-Line Plastic Packages (PDIP)

N

D1

E1

-B-

-C-

A1

A2

E

A

L

e

C

C

L

e

A

C

e

B

INDEX

AREA

BASE

PLANE

SEATING

PLANE

D1

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpendic­ular to datum .

7. e
e

8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

12 3 N/2

-A-

B1

B

e

A

and eC are measured at the lead tips with the leads unconstrained.

B

must be zero or greater.

C

D

e

0.010 (0.25) C AM BS

-C-

E28.6 (JEDEC MS-011-AB ISSUE B)

28 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.250 - 6.35 4
A1 0.015 - 0.39 - 4
A2 0.125 0.195 3.18 4.95 -

B 0.014 0.022 0.356 0.558 ­B1 0.030 0.070 0.77 1.77 8

C 0.008 0.015 0.204 0.381 -

D 1.380 1.565 35.1 39.7 5
D1 0.005 - 0.13 - 5

E 0.600 0.625 15.24 15.87 6
E1 0.485 0.580 12.32 14.73 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

L 0.115 0.200 2.93 5.08 4

N28 289

0.600 BSC 15.24 BSC 6

- 0.700 - 17.78 7

NOTESMIN MAX MIN MAX

Rev. 1 12/00

19

HI-546, HI-547, HI-548, HI-549

www.BDTIC.com/Intersil

Plastic Leaded Chip Carrier Packages (PLCC)

0.042 (1.07)

0.048 (1.22)
PIN (1) IDENTIFIER

0.020 (0.51) MAX
3 PLCS

0.045 (1.14)
MIN

NOTES:

1. Controlling dimension: INCH. Converted millimeter dimensions are

not necessarily exact.

2. Dimensions and tolerancing per ANSI Y14.5M-1982.

3. Dimensions D1 and E1 do not include mold protrusions. Allowable

mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.

4. To be measured at seating plane contact point.

5. Centerline to be determined where center leads exit plastic body.

6. “N” is the number of terminal positions.

C

L

D1

D

0.026 (0.66)

0.032 (0.81)

0.050 (1.27) TP

0.042 (1.07)

0.056 (1.42)

EE1

VIEW “A” TYP.

-C-

C

L

A1

A

0.013 (0.33)

0.021 (0.53)

0.025 (0.64)
MIN

0.004 (0.10) C

0.025 (0.64)

0.045 (1.14)

D2/E2

D2/E2

VIEW “A”

0.020 (0.51)
MIN

SEATING

-C-

PLANE

N28.45 (JEDEC MS-018AB ISSUE A)

28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

R

SYMBOL

A 0.165 0.180 4.20 4.57 -

A1 0.090 0.120 2.29 3.04 -

D 0.485 0.495 12.32 12.57 ­D1 0.450 0.456 11.43 11.58 3
D2 0.191 0.219 4.86 5.56 4, 5

E 0.485 0.495 12.32 12.57 ­E1 0.450 0.456 11.43 11.58 3
E2 0.191 0.219 4.86 5.56 4, 5

N28 286

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

Rev. 2 11/97

20

HI-546, HI-547, HI-548, HI-549

www.BDTIC.com/Intersil

Small Outline Plastic Packages (SOIC)

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45

o

α

e

B

0.25(0.010) C AM BS

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In­terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen­sions are not necessarily exact.

M

A1

0.10(0.004)

M28.3 (JEDEC MS-013-AE ISSUE C)

28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.6969 0.7125 17.70 18.10 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC ­H 0.394 0.419 10.00 10.65 -

C

h 0.01 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N28 287

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMIN MAX MIN MAX

-

21

HI-546, HI-547, HI-548, HI-549

www.BDTIC.com/Intersil

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

LEAD FINISH

c1

-A-

-B-

bbb C A - B

S

BASE

PLANE

SEATING

PLANE

S1

b2

b

ccc C A - BMD

D

A

A

e

S

S

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat­ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.

5. This dimension allows for off-center lid, meniscus, and glass
overrun.

6. Dimension Q shall be measured from the seating plane to the
base plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

-D­BASE

E

D

S

S

Q

A

-C­L

METAL

b1

M

(b)

SECTION A-A

α

(c)

M

eA

eA/2

aaa CA - B

M

c

D

S

S

F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)

16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.200 - 5.08 -

b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 ­b3 0.023 0.045 0.58 1.14 4

c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3

D - 0.840 - 21.34 5
E 0.220 0.310 5.59 7.87 5

e 0.100 BSC 2.54 BSC -

eA 0.300 BSC 7.62 BSC -

eA/2 0.150 BSC 3.81 BSC -

L 0.125 0.200 3.18 5.08 -

Q 0.015 0.060 0.38 1.52 6

S1 0.005 - 0.13 - 7

o

α

90

105

o

90

o

105
aaa - 0.015 - 0.38 ­bbb - 0.030 - 0.76 ­ccc - 0.010 - 0.25 -

M - 0.0015 - 0.038 2, 3
N16 168

NOTESMIN MAX MIN MAX

o

Rev. 0 4/94

-

22

HI-546, HI-547, HI-548, HI-549

www.BDTIC.com/Intersil

Dual-In-Line Plastic Packages (PDIP)

N

D1

E1

-B-

-C-

A1

A2

E

A

L

e

C

C

L

e

A

C

e

B

INDEX

AREA

BASE

PLANE

SEATING

PLANE

D1

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in JE­DEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be perpendic­ular to datum .

7. e
e

8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

12 3 N/2

-A-

B1

B

e

A

and eC are measured at the lead tips with the leads unconstrained.

B

must be zero or greater.

C

D

e

0.010 (0.25) C AM BS

-C-

E16.3 (JEDEC MS-001-BB ISSUE D)

16 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -

B 0.014 0.022 0.356 0.558 ­B1 0.045 0.070 1.15 1.77 8, 10

C 0.008 0.014 0.204 0.355 -

D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5

E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5

e 0.100 BSC 2.54 BSC -

e

A

e

B

L 0.115 0.150 2.93 3.81 4

N16 169

0.300 BSC 7.62 BSC 6

- 0.430 - 10.92 7

NOTESMIN MAX MIN MAX

Rev. 0 12/93

23

HI-546, HI-547, HI-548, HI-549

www.BDTIC.com/Intersil

Plastic Leaded Chip Carrier Packages (PLCC)

0.042 (1.07)

0.048 (1.22)
PIN (1) IDENTIFIER

0.020 (0.51) MAX
3 PLCS

C

L

D1

D

0.026 (0.66)

0.032 (0.81)

0.045 (1.14)
MIN

0.042 (1.07)

0.056 (1.42)

0.050 (1.27) TP

VIEW “A” TYP.

C

L

EE1

0.013 (0.33)

0.021 (0.53)

0.025 (0.64)
MIN

0.004 (0.10) C

0.025 (0.64)

0.045 (1.14)

D2/E2

D2/E2

A1

A

-C-

VIEW “A”

0.020 (0.51)
MIN

SEATING
PLANE

N20.35 (JEDEC MS-018AA ISSUE A)

20 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

R

SYMBOL

A 0.165 0.180 4.20 4.57 -

A1 0.090 0.120 2.29 3.04 -

D 0.385 0.395 9.78 10.03 ­D1 0.350 0.356 8.89 9.04 3
D2 0.141 0.169 3.59 4.29 4, 5

E 0.385 0.395 9.78 10.03 ­E1 0.350 0.356 8.89 9.04 3
E2 0.141 0.169 3.59 4.29 4, 5

N20 206

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

Rev. 2 11/97

NOTES:

1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.

2. Dimensions and tolerancing per ANSI Y14.5M-1982.

3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.

4. To be measured at seating plane contact point.

-C-

5. Centerline to be determined where center leads exit plastic body.

6. “N” is the number of terminal positions.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted b y implica tion or ot herw ise un der any patent or patent rights of Intersil or its subsidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

24