Intersil Corporation HI-5051, HI-5049, HI-5047, HI-5043, HI-5042 Datasheet
TM
HI-5042 thru HI-5051
Data Sheet April 2000
CMOS Analog Switches
This family of CMOS analog switches offers low resistance
switching performance for analog voltages up to the supply
rails and for signal currents up to 80mA. “ON” resistance is
low and stays reasonably constant over the full range of
operating signal voltage and current. r
exceptionally constant for input voltages between +5V and
-5V and currents up to 50mA. Switch impedance also
changes very little over temperature, particularly between
o
0
C and 75oC. rON is nominally 25Ω for HI-5049 and
HI-5051 and 50Ω for HI-5042 through HI-5047.
All devices provide break-before-make switching and are
TTL and CMOS compatible for maximum application
versatility. Performance is further enhanced by Dielectric
Isolation processing which insures latch-free operation with
very low input and output leakage currents (0.8nA at 25
This family of switches also features very low power
operation (1.5mW at 25
o
C).
There are 7 devices in this switch series which are
differentiated by type of switch action and value of r
Functional Description Table). The HI-504X and HI-505X
series switches can directly replace IH-5040 series devices,
and are functionally compatible with the DG180 and DG190
family.
remains
ON
ON
o
C).
(see
File Number 3127.4
Features
• Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . ±15V
• Low “ON” Resistance. . . . . . . . . . . . . . . . . . . . . . . . . 25Ω
• High Current Capability . . . . . . . . . . . . . . . . . . . . . . 80mA
• Break-Before-Make Switching
- Turn-On Time . . . . . . . . . . . . . . . . . . . . . . . . . . . .370ns
- Turn-Off Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 280ns
• No Latch-Up
• Input MOS Gates are Protected from Electrostatic
Discharge
• DTL, TTL, CMOS, PMOS Compatible
Applications
• High Frequency Switching
• Sample and Hold
• Digital Filters
• Operational Amplifier Gain Switching
Functional Diagram
S
Ordering Information
PART
NUMBER
HI1-5042-2 -55 to 125 16 Ld CERDIP F16.3
HI1-5043-2 -55 to 125 16 Ld CERDIP F16.3
HI1-5043-5 0 to 75 16 Ld CERDIP F16.3
HI3-5043-5 0 to 75 16 Ld PDIP E16.3
HI9P5043-5 0 to 75 16 Ld SOIC M16.15
HI1-5047-5 0 to 75 16 Ld CERDIP F16.3
HI1-5049-5 0 to 75 16 Ld CERDIP F16.3
HI1-5051-2 -55 to 125 16 Ld CERDIP F16.3
HI1-5051-5 0 to 75 16 Ld CERDIP F16.3
HI3-5051-5 0 to 75 16 Ld PDIP E16.3
HI9P5051-9 -40 to 85 16 Ld SOIC M16.15
TEMP. RANGE
(oC) PACKAGE PKG. NO.
A
N
P
Functional Description
PART NUMBER TYPE r
HI-5042 SPDT 50Ω
HI-5043 Dual SPDT 50Ω
HI-5047 4PST 50Ω
HI-5049 Dual DPST 25Ω
HI-5051 Dual SPDT 25Ω
D
ON
1
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
HI-5042 thru HI-5051
Pinouts (SWITCHES SHOWN FOR LOGIC “0” INPUT)
Single Control
SPDT
HI-5042 (50Ω)
1
D
1
2
3
D
2
4
S
2
5
6
7
8
16
S
1
15
A
14
V-
13
V
R
12
V
L
11
V+
D
D
S
1
S
4
D
4
10
9
D
3
NOTE: Unused pins may be internally connected. Ground all
unused pins.
HI-5047 (50Ω)
1
2
2
3
1
4
5
6
7
8
4PST
16
S
2
15
A
14
V-
13
V
R
12
V
L
11
V+
10
9
S
3
Switch Functions (SWITCHES SHOWN FOR LOGIC “1” INPUT)
16
S
1
S
2
15
A
SPDT
HI-5042 (50Ω)
L
12 11
4
13 14
R
V+V
1
D
1
3
D
2
S
S
A
A
S
S
V-V
16
1
4
3
15
1
10
2
9
2
5
4
DUAL SPDT
HI-5043 (50Ω)
L
12
13 14
R
Pinouts (SWITCHES SHOWN FOR LOGIC “0” INPUT)
Dual Control
DUAL SPDT
HI-5043 (50Ω), HI-5051 (25Ω)
1
D
1
2
3
D
3
4
S
3
5
S
4
6
D
4
7
8
D
2
16
S
1
15
A
1
14
V-
13
V
R
12
V
L
11
V+
10
A
2
9
S
2
NOTE: Unused pins may be internally connected. Ground all
unused pins.
V+V
11
1
D
1
3
D
3
8
D
2
6
D
4
V-V
DUAL DPST
HI-5049 (25Ω)
1
D
1
2
3
D
3
4
S
3
5
S
4
6
D
4
7
8
D
2
16
S
1
15
A
1
14
V-
13
V
R
12
V
L
11
V+
10
A
2
9
S
2
S
1
16
S
2
S
3
S
4
15
A
4PST
HI-5047 (50Ω)
L
12 11
4
9
5
13 14
R
DUAL DPST
HI-5049 (25Ω)
V+V
3
D
1
1
D
2
8
D
3
6
D
4
16
S
1
4
S
3
15
A
1
10
A
2
9
S
2
5
S
4
V-V
V+V
L
12
13 14
V-V
R
11
1
D
1
3
D
3
S
S
A
8
D
2
6
D
4
A
S
S
16
1
4
3
15
1
10
2
9
2
5
4
DUAL SPDT
HI-5051 (25Ω)
V+V
L
11
12
13 14
V-V
R
1
D
1
3
D
3
8
D
2
6
D
4
2
Schematic Diagrams
HI-5042 thru HI-5051
N13
25µA
V+
P15 P16
25µA
P13
16µA
QN2
QP2
N16
QP1
25µA
V
L
35µA
QP3 QP4
QP5 QP6
QP8
R2
V
R
R6
25µA
QP7
N14 N15
P14
R3
100µA
R4
R5
NOTE: Connect V+ to VL for minimizing power consumption when driving from CMOS circuits.
TTL/CMOS REFERENCE CIRCUIT (NOTE)
)
A
1(A2
N1
V+
IN
P2
N3
N2
V-
P1
R7
V+
QN1
25µA
TO V
’
R
V-
to VL’
OUT
A1(A2)
SWITCH CELL
V+
P3
V+
D1
R4
A
200Ω
D2
V-
P1
N1
'
V
R
'
V
L
P2
N2
N3
P5
P4
P6 P7
N4
N5
V-
NOTE: All N-Channel bodies to V-, all P-Channel bodies to V+ except as shown.
DIGITAL INPUT BUFFER AND LEVEL SHIFTER
3
P8 P9 P10 P11 P12
A1
A1
A2
A2
N12N11N10N9N8N7N6
HI-5042 thru HI-5051
Absolute Maximum Ratings Thermal Information
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36V
VR to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+, V-
Digital and Analog Input Voltage . . . . . . . . . . . . (V+) +4V to (V-) -4V
Analog Current (S to D) Continuous . . . . . . . . . . . . . . . . . . . . 30mA
Analog Current (S to D) Peak . . . . . . . . . . . . . . . . . . . . . . . . . 80mA
Operating Conditions
Temperature Range
HI-50XX-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
HI-50XX-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 75oC
HI-50XX-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
CERDIP Package. . . . . . . . . . . . . . . . . 75 22
SOIC Package . . . . . . . . . . . . . . . . . . . 110 N/A
PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175oC
Maximum Storage Temperature. . . . . . . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Electrical Specifications Supplies = +15V, -15V; V
Unless Otherwise Specified. For Test Conditions, Consult Performance Characteristics,
= 0V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V, VL=5V,
R
Unused Pins are Grounded
-2 -5, -9
UNITSMIN TYP MAX MIN TYP MAX
PARAMETER
TEST
CONDITIONS
TEMP
o
(
C)
DYNAMIC CHARACTERISTICS
Switch ON Time, t
Switch OFF Time, t
ON
OFF
(Note 5) 25 - 370 500 - 370 500 ns
(Note 5) 25 - 280 500 - 280 500 ns
Charge Injection, Q (Note 3) 25 - 5 20 - 5 - mV
OFF Isolation (Note 4) 25 75 80 - - 80 - dB
Crosstalk (Note 4) 25 80 88 - - 88 - dB
Input Switch Capacitance, C
S(OFF)
Output Switch Capacitance, C
Output Switch Capacitance, C
Digital Input Capacitance, C
A
Drain To Source Capacitance, C
D(OFF)
D(ON)
DS(OFF)
25 - 11 - - 11 - pF
25 - 11 - - 11 - pF
25 - 22 - - 22 - pF
25 - 5 - - 5 - pF
25 - 0.5 - - 0.5 - pF
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, V
Input High Threshold, V
AL
AH
Input Leakage Current (High or Low), I
A
Full - - 0.8 - - 0.8 V
Full 2.4 - - 2.4 - - V
Full - 0.01 1.0 - 0.01 1.0 µA
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range Full -15 - +15 -15 - +15 V
ON Resistance, r
ON
HI-5042 to HI-5047 (Note 2) 25 - 50 75 - 50 75 Ω
Full - - 150 - - 150 Ω
HI-5049, HI-5051 (Note 2) 25 - 25 45 - 25 45 Ω
Full - - 50 - - 50 Ω
Channel-to-Channel Match, ∆r
ON
HI-5042 to HI-5047 25 - 2 10 - 2 10 Ω
HI-5049, HI-5051 25 - 1 5 - 1 5 Ω
OFF Input or Output Leakage Current,
I
= I
S(OFF)
D(OFF)
25 - 0.8 2 - 0.8 2 nA
Full - 100 200 - 100 200 nA
4
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