Intersil Corporation HI3304 Datasheet

HI3304

August 1997

Features

• CMOS Low Power (Typ). . . . . . . . . . . . . . . . . . . . 35mW

• Parallel Conversion Technique

• Single Power Supply Voltage . . . . . . . . . . . . 3V to 7.5V

• Sampling Rate at 5V Supply . . . . . . . . . . . . . . . . . 25MHz

• 4-Bit Latched Three-State Output with Overflow and
Data Change Outputs

• Maximum Nonlinearity. . . . . . . . . . . . . . . . . . . .

• Inherent Resistance to Latch-Up

• Bipolar Input Range with Optional Second Supply

• Input Bandwidth (Typ) . . . . . . . . . . . . . . . . . . . . . 40MHz

• Linearity (INL, DNL):

- HI3304JIP . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.25 LSB

- HI3304JIB . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.25 LSB

• Sampling Rate:

- HI3304JIP . . . . . . . . . . . . . . . . . . . . . . . 25MHz (40ns)

- HI3304JIB . . . . . . . . . . . . . . . . . . . . . . . 25MHz (40ns)

Applications

• Video Digitizing

• High Speed Data Acquisition

• Digital Communication Systems

• Radar Signal Processing

1

/8 LSB

4-Bit, 25 MSPS, Flash A/D Converter

Description

The Intersil HI3304 is a CMOS parallel (FLASH) analog-to­digital converter designed for applications demanding both
low-power consumption and high speed digitization. Digitiz­ing at 25MHz, for example, requires only about 35mW.

The HI3304 operates over a wide, full-scale signal input volt­age range of 0.5V up to the supply voltage. Power consump­tion is as low as 10mW, depending upon the clock frequency
selected.

Sixteen paralleled auto-balanced voltage comparators mea­sure the input voltage with respect to a known reference to
produce the parallel-bit outputs in the HI3304. Fifteen com­parators are required to quantize all input voltage levels in
this 4-bit converter, and the additional comparator is required
for the overflow bit. A data change pin indicates when the
present output differs from the previous, thus allowing com­paction of data storage.

Ordering Information

TEMP.

PART NUMBER

HI3304JIP -40 to 85 16 Ld PDIP E16.3
HI3304JIB -40 to 85 16 Ld SOIC M16.3

RANGE (oC) PACKAGE PKG. NO.

Pinout

HI3304

(PDIP, SOIC)

TOP VIEW

16

V

DD

15

CLK

14

VAA-

13

V

REF

V

12

REF

V

11

IN

10

VAA+

9

CE1

BIT 2
BIT 3
BIT 4

CE2
V

SS

1
2
3
4
5
6
7
8

BIT 1 (LSB)

DATA CHANGE (DC)

OVERFLOW (OF)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

4-1424

­+

File Number 4137.1

Functional Block Diagram

φ1 φ1 φ1 φ1φ2

V

IN

11

1

/2R

12

V

+

REF

R

†CAB #16

D

LATCH

16

HI3304HI3304

VAA+V

COUNT

16

Q

OUTPUT

φ2

DD

1610

REGISTER

DQ
CLK

DQ
CLK

DQ
CLK

THREE-STATE

DRIVERS

DAT A

5

CHANGE

6

OVERFLOW

BIT 4

4

V

REF

13

CLOCK

15

R

†CAB #8

R

R

-

1

/2R

†CAB COMPARATOR #1

50kΩ

D

LATCH

8

D

LATCH

0

COUNT

Q

COUNT

Q

φ1 (AUTO BALANCE)
φ2 (SAMPLE UNKNOWN)

8

1

ENCODER

LOGIC

ARRA Y

VAA-V

814

SS

DQ
CLK

DQ
CLK

DQ
CLK

3

BIT 3

2

BIT 2

1

BIT 1 (LSB)

9

CE1

CE2

7

†Cascaded Auto Balance (CAB)

NOTE: CE1 and CE2 inputs and data outputs have standard CMOS protection networks to VDD and VSS. Analog inputs and clock have
standard CMOS protection networks to VAA+ and VAA-.

4-1425

HI3304HI3304

Absolute Maximum Ratings Thermal Information

DC Supply Voltage Range (VDD or VAA+)

(Voltage Referenced to VSS or VAA- Terminal,

Whichever is More Negative) . . . . . . . . . . . . . . . . . . -0.5V to +8V

Input Voltage Range

CE1, CE2 Inputs. . . . . . . . . . . . . . . . . . . VSS -0.5V to VDD +0.5V

Clock, V

REF

+, V

-, VIN Inputs . . . . . . VAA -0.5V to VAA +0.5V

REF

DC Input Current, Any Input. . . . . . . . . . . . . . . . . . . . . . . . . ±20mA

Operating Conditions

Supply Voltage Range (VDD or VAA+) . . . . . . . . . . . . . . . . . .3V to 7.5V

VAA+ Voltage Range . . . . . . . . . . . . . . . . . . VDD -1V to VDD +2.5V

VAA- Voltage Range. . . . . . . . . . . . . . . . . . . .VSS -2.5V to VSS +1V

Operating Temperature Range. . . . . . . . . . . . . . . . . . -40oC to 85oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 1) θJA(oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range (T

) . . . .-65oC to 150oC

STG

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

Electrical Specifications T

= 25oC, V

A

+ = 2V, VDD = VAA+ = 5V, VAA- = V

REF

- = VSS = GND, f

REF

CLK

= 25MHz

Unless Otherwise Specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SYSTEM PERFORMANCE

Resolution 4 - - Bits
Input Errors Integral Linearity Error - ±0.125 ±0.25 LSB

Differential Linearity Error - ±0.125 ±0.25 LSB
Offset Error (Unadjusted) - - ±1.0 LSB

Gain Error (Unadjusted) - - ±1.0 LSB
DYNAMIC CHARACTERISTICS Input Signal Level 0.5dB Below Full Scale
Conversion Timing Aperture Delay - 3 - ns
Signal to Noise Ratio (SNR) f

RMS Signal

----------------------------------

=

RMS Noise

Signal to Noise Ratio (SINAD) f

RMS Signal

--------------------------------------------------------------- -

=

RMSNoise + Distortion

= 25MHz, fIN = 100kHz - 23.7 - dB

S

= 25MHz, fIN = 5MHz - 23.6 - dB

f

S

= 25MHz, fIN = 100kHz - 23.4 - dB

S

= 25MHz, fIN = 5MHz - 22.8 - dB

f

S

Total Harmonic Distortion, THD fS = 25MHz, fIN = 100kHz - -34.5 - dBc

= 25MHz, fIN = 5MHz - -31.0 - dBc

f

S

Effective Number of Bits, ENOB f

= 25MHz, fIN = 100kHz - 3.67 - Bits

S

= 25MHz, fIN = 5MHz - 3.57 - Bits

f

S

ANALOG INPUTS

Input Range Full Scale Input Range (Notes 1, 4) 0.5 - V

AA

V

Input Loading Input Capacitance - 10 - pF

Input Current V

= 2V (Note 2) - 150 200 µA

IN

-3dB Input Bandwidth - 40 - MHz

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HI3304HI3304

Electrical Specifications T

= 25oC, V

A

+ = 2V, VDD = VAA+ = 5V, VAA- = V

REF

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

REFERENCE INPUTS

Input Range V

+ Range (Note 4) VAA- +0.5 - VAA+V

REF

- Range (Note 4) VAA--V

V

REF

Input Loading Resistor Ladder Impedance V

DIGITAL INPUTS

Digital Input Maximum V

, Low CLOCK (Notes 3, 4) - - 0.3 x V

IN

CE1, CE2 (Note 4) - - 0.3 x V

Minimum V

, High CLOCK (Notes 3, 4) 0.7 x V

IN

CE1, CE2 (Note 4) 0.7 x V
Input Leakage, Except CLK V = 0V, 5V - - ±1 µA
Input Leakage, CLK (Note 3) - ±100 ±150 µA

DIGITAL OUTPUTS

Digital Outputs Output Low (Sink) Current V

Output High (Source) Current V
Three-State Leakage Current V

TIMING CHARACTERISTICS

- = VSS = GND, f

REF

= 5V, CLK = Low 640 - 960 Ω

IN

AA
DD

= 0.4V 6 - - mA

O

= 4.6V -3 - - mA

O

= 0V, 5V - ±0.2 ±5 µA

O

= 25MHz

CLK

+ -0.5 V

AA

AA
DD

--V

--V

V
V

Conversion Timing Maximum Conversion Speed CLK = Square Wave 25 35 - MSPS

Auto-Balance Time (
Sample Time (

φ2) 20 - 5000 ns

φ1) 20 -

-

ns

Output Timing Data Valid Delay (Note 4) - 30 40 ns

Data Hold Time (Note 4) 15 25 - ns
Output Enable Time - 15 - ns
Output Disable Time - 10 - ns

POWER SUPPLY CHARACTERISTICS

Device Current, I

Device Current, I

AA

DD

V

AA

+ = 5V,

Continuous Clock - 5.5 - mA
Continuous
Continuous

φ2 - 0.4 - mA
φ1-2-mA

Continuous Clock - 1.5 - mA
Continuous φ2-510mA

VSS = CE1 = VAA- = CLK = GND
V

+ = 7V Continuous φ1-520mA

AA

NOTES:

1. Full scale input range, V

REF

+ - V

-, may be in the range of 0.5V to VAA+ -VAA- volts. Linearity errors increase at lower full scale ranges,

REF

however.

2. Input current is due to energy transferred to the input at the start of the sample period. The average value is dependent on input and V
voltage.

3. The CLK input is a CMOS inverter with a 50kΩ feedback resistor. It operates from the VAA+ and VAA- supplies. It may be AC-coupled
with a 1V

minimum source.

P-P

4. Parameter not tested, but guaranteed by design or characterization.

DD

4-1427