Intersil Corporation HI3026 Datasheet

HI3026

August 1997

Features

• Differential Linearity Error . . . . . . . . . . . . . . . ±0.5 LSB

• Integral Linearity Error . . . . . . . . . . . . . . . . . . ±0.5 LSB

• Integral Linearity Compensation Circuit

• Low Input Capacitance . . . . . . . . . . . . . . . . . . . . . . 21pF

• Wide Analog Input Bandwidth . . . . . . . . . . . . . 150MHz

• Low Power Consumption . . . . . . . . . . . . . . . . . .760mW

1

• Internal

/2 Frequency Divider Circuit (w/Reset Function)

• CLK/2 Clock Output

• Compatible with ECL, PECL and TTL Digital Input Levels

• 1:2 Demultiplexed Output Pin

• Surface Mounting Package

• Direct Replacement for Sony CXA3026Q

Applications

• RGB Graphics Processing (LCD, PDP)

• Digital Oscilloscopes

• Digital Communications (QPSK, QAM)

• Magnetic Recording (PRML)

8-Bit, 120 MSPS, Flash A/D Converter

Description

The HI3026 is an 8-bit, high-speed, flash analog-to-digital
converter optimized for high speed, low power, and ease of
use. With a 120 MSPS encode rate capability and full-power
analog bandwidth of 150MHz, this component is ideal for appli­cations requiring the highest possible dynamic performance.

To minimize system cost and power dissipation, only a +5V
power supply is required. The HI3026’s clock input interfaces
directly to TTL, ECL, or PECL logic and will operate with single­ended inputs. The user may select 16-bit demultiplexed output
or 8-bit single channel digital outputs. The demultiplexed mode
interleaves the data through two 8-bit channels at
rate. Operation in demultiplexed mode reduces the speed and
cost of external digital interfaces, while allowing the A/D con­verter to be clocked to the full 120 MSPS conversion r ate.

Fabricated with an advanced Bipolar process, the HI3026 is
provided in a space-saving 48-lead MQFP surface mount
plastic package and is specified over the -20
perature range. For a faster clock rate, please refer to the
HI3026A (140 MSPS), AnswerFAX Document number 4246.

Ordering Information

PART

NUMBER

HI3026JCQ -20 to 75 48 Ld MQFP Q48.12x12-S
HI3026EVAL 25 Evaluation Board

TEMP. RANGE

(oC) PACKAGE PKG. NO.

1

/2 the clock

o

C to 75oC tem-

Pinout

DV

EE3

V

RB

AGND

V

RM1

AV

CC

V

V

RM2

AV

CC

V

RM3

AGND

V

RT

DGND3

HI3026 (MQFP)

TOP VIEW

CC2

RESET/E

RESETN/T

INV

RESETN/E

1
2

3
4
5

IN

6
7

8
9
10

11
12

13 14 15 16

CLK/E

CLKN/E

CLK/T

CLKOUT

SELECT

NCNCNC

DV

CC2

DV

P1D7

DGND2

P2D0

DGND2

P1D6

P2D1

P1D5

373839404142434445464748

36
35
34
33
32
31
30
29
28
27
26
25

2423222120191817

P2D2

P1D4

P2D3

P1D3
P1D2
P1D1
P1D0

DGND2
DV

CC2

DV

CC1

DGND1
P2D7

P2D6
P2D5
P2D4

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

4-1362

File Number 4109.3

Block Diagram

11

V

RT

R1

R/2
R

R

R

HI3026

AV

CC

5 8 30 19 31 42 12

1

2

6 BITS

INV

44

DV

CC1

DV

CC2

DGND3

(MSB)

40

P1D7

39

P1D6

38

P1D5

V

V

V

RM3

RM2

V

RM1

V

RB

63

9

7

6

IN

4

2

R/2

R

R

R

R

R

R

R

R

R

R

R

R/2

64

65

126

127

128

129

191

192

193

254

255

6 BITS

ENCODER

6 BITS

6 BITS

8 BITS

8 BITS

6-BIT LATCH AND ENCODER

LATCHA

LATCHB

TTLOUT

TTLOUT

37

P1D4

36

P1D3

35

P1D2

34

P1D1

33

P1D0
(LSB)

(MSB)

28

P2D7

27

P2D6

P2D5

26

P2D4

25

P2D3

24

P2D2

23

P2D1

22

P1D0

21

(LSB)

CLK/T

CLK/E

CLKN/E

RESETN/T

RESETN/E

RESET/E

15

13

14

46

48

47

3 10 45 29 20 32 41 1

AGND

DELAY

DQ

Q

SELECT

DGND2DGND1SELECT

DV

EE3

16
17
18

43

NC

CLKOUT

4-1363

HI3026

Absolute Maximum Ratings T

Supply Voltage (AVCC, DV

(DGND3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V

(DV

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7.0V to 0.5V

EE3

(DGND3 - DV

). . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7.0V

EE3

Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . .VRT - 2.7V to AV

Reference Input Voltage (VRT). . . . . . . . . . . . . . . . . . .2.7V to AV

(VRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN - 2.7V to AV

CC1

, DV

=25oC Thermal Information

A

) . . . . . . . . . . -0.5V to 7.0V

CC2

Thermal Resistance (Typical, Note 1) θJA (oC/W)

MQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC

CC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

CC
CC

(Lead Tips Only)

(|VRT - VRB|). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5V

Digital Input Voltage

ECL (***/E (Note 2)) . . . . . . . . . . . . . . . . . . . . . . . .DV

EE3

to 0.5V

PECL (***/E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DGND3

TTL (***/T, INV). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DV

Other (SELECT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to DV

CC1
CC1

VID (|***/E - ***N/E| (Note 3)) . . . . . . . . . . . . . . . . . . . . . . . . .2.7V

Recommended Operating Conditions

WITH A SINGLE POWER SUPPLY MIN TYP MAX

Supply Voltage

DV

, DV

CC1

, AVCC . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V

CC2

DGND1, DGND2, AGND . . . . . . . . . . . . . -0.05 0 +0.05V

DGND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75 +5.0 +5.25V

DV

. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V

EE3

Analog Input Voltage (VIN) . . . . . . . . . . . . . . V

RB

-V

Reference Input Voltage

VRT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 - +4.1V

VRB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 - +2.6V

|VRT - VRB| . . . . . . . . . . . . . . . . . . . . . . . . 1.5 - 2.1V

Digital Input Voltage

PECL (***/E) VIH. . . . . . . . . . . . . . . DGND3 - 1.05 DGND3 - 1.4V

PECL (***/E) VIL. . . . . . . . . . . . . . . DGND3 - 3.2 DGND3 - 1.4V

TTL (***/T, INV) VIH. . . . . . . . . . . . . . . . . . 2.0V - -

TTL (***/T, INV) VIL. . . . . . . . . . . . . . . . . . - - 0.8V

Other (SELECT) VIH. . . . . . . . . . . . . . . . . - DV

CC1

Other (SELECT) VIL. . . . . . . . . . . . . . . . . - DGND1 -

VID (Note 3) (|***/E- ***N/E|). . . . . . . . . . . 0.4 0.8 -

Max Conversion Rate (fC, Straight Mode) . . . 100 - -

MSPS

Max Conversion Rate (fC, DMUX Mode) . . . . 120 - -

MSPS

Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . .-20oC to 75oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

2. ***/E and ***T indicate CLK/E and CLK/T, etc., for the pin name.

3. VID: Input Voltage Differential.

WITH DUAL POWER SUPPLIES MIN TYP MAX

Supply Voltage

DV

, DV

CC1

, AVCC . . . . . . . . . . . . . . +4.75 +5.0 +5.25V

CC2

DGND1, DGND2, AGND. . . . . . . . . . . . . -0.05 0 +0.05V

DGND3 . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05 0 +0.05V

DV

. . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5 -5.0 -4.75V

EE3

Analog Input Voltage (VIN) . . . . . . . . . . . . . V

RT

RB

Reference Input Voltage

VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.9 - +4.1V

VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 - +2.6V

|VRT - VRB| . . . . . . . . . . . . . . . . . . . . . . . 1.5 - 2.1V

Digital Input Voltage

ECL (***/E) VIH. . . . . . . . . . . . . . . . DGND3 - 1.05 DGND3 - 0.5V

ECL (***/E) VIL . . . . . . . . . . . . . . . . DGND3 - 3.2 DGND3 - 1.4V

TTL (***/T, INV) VIH. . . . . . . . . . . . . . . . . 2.0V - -

TTL (***/T, INV) VIL . . . . . . . . . . . . . . . . . - - 0.8V

-

Other (SELECT) VIH . . . . . . . . . . . . . . . . - DV

Other (SELECT) VIL . . . . . . . . . . . . . . . . - DGND1 -

VID (Note 3) (|***/E- ***N/E|) . . . . . . . . . . 0.4 0.8 -

Max Conversion Rate (fC, Straight Mode). . . 100 - -

MSPS

Max Conversion Rate (fC, DMUX Mode). . . . 120 - -

MSPS

Ambient Temperature (TA). . . . . . . . . . . . . . . . . . . . . .-20oC to 75oC

-V

RT

CC1

-

Electrical Specifications DV

, AVCC, DGND3 = +5V, DGND1, 2, AGND, DV

CC1,2

= 0V, VRT = 4V, VRB = 2V,

EE3

TA = 25oC

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Resolution - 8 - Bits

DC CHARACTERISTICS

Integral Linearity Error, E

IL

Differential Linearity Error, E

DL

VIN = 2V

, fC = 5 MSPS - - ±0.5 LSB

P-P

--±0.5 LSB

ANALOG INPUT

Analog Input Capacitance, C
Analog Input Resistance, R
Analog Input Current, I

IN

IN

IN

VIN = +3.0V +0.07V

RMS

-21-pF
4 - 50 kΩ
0 - 500 µA

4-1364

HI3026

Electrical Specifications DV

, AVCC, DGND3 = +5V, DGND1, 2, AGND, DV

CC1,2

= 0V, VRT = 4V, VRB = 2V,

EE3

TA = 25oC (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

REFERENCE INPUT

Reference Resistance (Note 4), R
Reference Current (Note 5), I

REF

REF

75 115 155 Ω

9.7 17.4 28 mA
Offset Voltage VRT Side, EOT 2 - 15 mV
Offset Voltage VRB Side, EOB 2 - 10 mV

DIGITAL INPUT (ECL, PECL)

Digital Input Voltage: High, V
Digital Input Voltage: Low, V
Threshold Voltage, V

TH

Digital Input Current: High, I
Digital Input Current: Low, I

IH

IL

IH

IL

VIH = DGND3 - 0.8V -50 - +50 µA
VIL = DGND3 - 1.6V -75 - 0 µA

DGND3 - 1.05 - DGND3 - 0.5 V

DGND3 - 3.2 - DGND3 -1.4 V

- DGND3 - 1.2 - V

Digital Input Capacitance - - 5 pF

DIGITAL INPUT (TTL)

Digital Input Voltage: High, V
Digital Input Voltage: Low, V
Threshold Voltage, V

TH

Digital Input Current: High, I
Digital Input Current: Low, I

IH

IL

IH

IL

VIH = 3.5V -50 - 0 µA
VIL = 0.2V -500 - 0 µA

2.0 - - V

- - 0.8 V

- 1.5 - V

Digital Input Capacitance - - 5 pF

DIGITAL OUTPUT (TTL)

Digital Output Voltage: High, V
Digital Output Voltage: Low, V

OH

OL

IOH = -2mA 2.4 - - V
IOL = 1mA - - 0.5 V

SWITCHING CHARACTERISTICS

Maximum Conversion Rate, f
Aperture Jitter, t
Sampling Delay, t
Clock High Pulse Width, t
Clock Low Pulse Width, t
Reset Pulse Width, t

AJ

DS

PW1

PW0

(Note 6) RESETN t x 2 - - ns

PWR

RESET Signal Setup Time, t
RESET Signal Hold Time, t
CLKOUT Output Delay, t

DCLK

Data Output Delay (Note 6), t

Output Rise Time, t
Output Fall Time, t

r

f

RH

RS

t

C

DO1
DO2

DMUX Mode 120 - - MSPS

-10-ps

3 4.5 6 ns
CLK 3.2 - - ns
CLK 3.2 - - ns

RESETN-CLK 3.5 - - ns
RESETN-CLK 0 - - ns
(CL = 5pF) 3.5 7 9 ns
DEMUX Mode (CL = 5pF) t t + 1 t + 2 ns

(CL = 5pF) 4.5 8 10 ns

0.8 to 2.0V (CL = 5pF) - 2 - ns

0.8 to 2.0V (CL = 5pF) - 2 - ns

DYNAMIC CHARACTERISTICS

Input Bandwidth VIN = 2V
S/N Ratio fC = 120 MSPS, fIN = 1kHz Full Scale,

, -3dB 150 - - MHz

P-P

-46-dB

DMUX Mode
fC = 120 MSPS, fIN = 29.999MHz Full Scale,

-40-dB

DMUX Mode

4-1365

HI3026

Electrical Specifications DV

, AVCC, DGND3 = +5V, DGND1, 2, AGND, DV

CC1,2

TA = 25oC (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Error Rate (Note 7) fC = 120 MSPS, fIN = 1kHz Full Scale,

DMUX Mode, Error > 16 LSB
fC = 120 MSPS, fIN = 29.999MHz

Full Scale, DMUX Mode, Error > 16 LSB
fC = 100 MSPS, fIN = 24.999MHz

Full Scale, Straight Mode, Error > 16 LSB

POWER SUPPLY

Supply Current, I
Supply Current, I
Power Consumption (Note 8), P

CC
EE

D

NOTES:

4.

R

: Resistance value between VRT and VRB.

REF

VRTVRB–

I

REF

-----------------------------=

R

1

-----=

.

f

C

REF

.

5.

6.

T

7.The unit of measure TPS: Times Per Sample.

2

–()

V

P

8. .

DICCIEE

+()VCC•

RTVRB

-------------------------------------+=

V

REF

= 0V, VRT = 4V, VRB = 2V,

EE3

--

--

--

10

10

10

-12

-9

-9

TPS

TPS

TPS

125 145 185 mA

0.4 0.6 0.8 mA

660 760 960 mW

Timing Diagrams

V

IN

CLK

P1D0 TO D7

P2D0 TO D7

CLK OUT

N - 1

t

DS

t

t

PW1tPW0

t

DCLK

2V

0.8V

N + 2

N

N + 1

N - 2

N - 3

t

D02

t + 1ns

2V

0.8V

t

D01

N + 3

2V

0.8V

2V

0.8V

N

N - 1

N + 2

N - 1

RESET PULSE

t

PWR

FIGURE 1. DEMUX MODE TIMING CHART (SELECT = VCC)

4-1366

Timing Diagrams

HI3026

V

CLK

P1D0 TO D7

P2D0 TO D7

CLK OUT

(CLK IS INVERTED AND OUTPUT)

RESET PULSE

N - 1

IN

t

t

DS

PW1

N - 4

N - 5

t

D02

8ns

t

DCLK

t

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

t

PW0

N

N - 3

N - 4

N + 1

N - 2

N - 3

FIGURE 2. STRAIGHT MODE TIMING CHART (SELECT = GND)

N + 2

N - 1

N - 2

N + 3

N

N - 1

DGND3

(MAX)

V

IH

V

IL

VTH (DGND3 - 1.2V)

V

ID

V

IH

VIL (MIN)

FIGURE 3. ECL AND PECL SWITCHING LEVEL

Pin Descriptions

TYPICAL

PIN NO SYMBOL I/O

3, 10 AGND GND Analog Ground. Separated from the

5, 8 AV

20, 29
32, 41

19, 30
31, 42

CC

DGND1
DGND2

DV

CC1

DV

CC2

12 DGND3 +5V (Typ) (With a

VOLTAGE LEVEL EQUIVALENT CIRCUIT DESCRIPTION

digital ground.

+5V (Typ) Analog Power Supply. Separated from

the digital power supply.

GND Digital Ground.

+5V (Typ) Digital Power Supply.

Digital Power Supply. Ground for ECL

Single Power Supply)

input. -5V for PECL and TTL input.

GND (With Dual
Power Supplies)

4-1367