Intersil Corporation HI2302 Datasheet
November 1997
HI2302
8-Bit, 50 MSPS, Video
A/D Converter with Clamp Function
Features
• Resolution . . . . . . . . . . . . . . . . . . 8-Bit ±0.5 LSB (DNL)
• Maximum Sampling Frequency . . . . . . . . . . . 50 MSPS
• Low Power Consumption . . . . . . . . . . . . . . . . . .125mW
(Reference Current Excluded)
• Built-In Input Clamp Function (DC Restore)
• Clamp ON/OFF Function
• Internal Voltage Reference
• Input CMOS/TTL Compatible
• Three-State TTL Compatible Output
• Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . +5V Single
or +5V/3.3V Dual
• Direct Replacement for Sony CXD2302Q
Applications
• Video Digitizing
• Wireless Receivers
• LCD Projectors/Panels
• Cable Modems
• RGB Graphics Processing
• Camcorders
• Instrumentation
Description
The HI2302 is an 8-bit CMOS A/D Converter for video with
synchronizing clamp function. The adoption of two-step
parallel method achieves low power consumption and a
maximum conversion rate of 50 MSPS. For pin compatible
lower sample rate converters refer to HI1179 (35 MSPS) or
HI1176 (20 MSPS) data sheets.
Ordering Information
PART
NUMBER
HI2302JCQ -40 to 85 32 Ld MQFP Q32.7x7-S
TEMP.
RANGE (oC) PACKAGE PKG. NO.
Pinout
HI2302 (MQFP)
TOP VIEW
OE
TEST
CLE
CLK
4-1
DV
NC
SS
CCP
NC
REF
V
161514131211109
CLP
RBS
V
24
23
22
21
20
19
18
17
DD
AV
SS
DV
NC
D0
D1
D2
D3
D4
D5
D6
D7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
DD
TEST
DV
V
AV
AV
V
AV
AV
V
V
RB
SS
SS
IN
DD
DD
RT
RTS
File Number 4105.1
Functional Block Diagram
DV
28
30
OE
31
DV
SS
D0 (LSB)
D7 (MSB)
TEST (OPEN)
DV
D1
D2
D3
D4
D5
D6
DD
CLK
1
2
3
4
5
6
7
8
10
11
12
LOWER
DAT A
LATCH
UPPER
DAT A
LATCH
CLOCK GENERATOR
SS
LOWER
ENCODER
(4-BIT)
LOWER
ENCODER
(4-BIT)
UPPER
ENCODER
(4-BIT)
HI2302
SAMPLING COMPARATOR
SAMPLING COMPARATOR
SAMPLING COMPARATOR
LOWER
(4-BIT)
LOWER
(4-BIT)
UPPER
(4-BIT)
REFERENCE
SUPPLY
25
V
RBS
24
V
RB
23
AV
SS
22
AV
SS
21
V
IN
20
AV
DD
19
AV
DD
18
V
RT
17
V
RTS
16
AV
DD
TEST (OPEN)
-
+
15
9
32NC
29 27 26
CCPCLE
V
REF
D-FF
CLP
NC
14
NC
13
4-2
HI2302
Absolute Maximum Ratings T
Supply Voltage (VDD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Reference Voltage (VRT, VRB) . . . . . . . . . . . VDD+0.5 to VSS-0.5V
Input Voltage (Analog) (VIN). . . . . . . . . . . . . VDD+0.5 to VSS-0.5V
Input Voltage (Digital) (VI). . . . . . . . . . . . . . . VDD+0.5 to VSS-0.5V
Output Voltage (Digital) (VO) . . . . . . . . . . . . VDD+0.5 to VSS-0.5V
Operating Conditions
=25oC Thermal Information
A
Thermal Resistance (Typical, Note 1) θJA (oC/W)
MQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-55oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(MQFP - Lead Tips Only)
Supply Voltage (AVDD, AVSS). . . . . . . . . . . . . . . . . .4.75 to 5.25V
(DVDD, DVSS) . . . . . . . . . . . . . . . . . . . 3.0 to 5.5V
(DVSS-AVSS) . . . . . . . . . . . . . . . . . 0 to 100mV
Reference Input Voltage
(VRB) . . . . . . . . . . . . . . . . . . . . . . .0 and Above V
(VRT) . . . . . . . . . . . . . . . . . . . . . 2.7 and Below V
Analog Input (VIN) . . . . . . . . . . . . . . . . . . . . . . . 1.7V
Clock Pulse Width (t
Ambient Temperature (T
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
, t
PW1
). . . . . . . . . . . . . . . . . . . . 10ns (Min)
PW0
). . . . . . . . . . . . . . . . . . . -40oC to 85oC
OPR
P-P
Above
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications f
= 50 MSPS, AVDD = 5V, DVDD = 3 to 5.5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC
C
PARAMETER SYMBOL TEST CONDITIONS NOTES MIN TYP MAX UNITS
ANALOG CHARACTERISTICS
Maximum Conversion Rate f
Minimum Conversion Rate f
Input Bandwidth Full Scale BW Envelope
Differential Nonlinearity Error E
Integral Nonlinearity Error E
Offset Voltage E
Max AVDD = 4.75 to 5.25V, TA = 20 to 75oC, V
C
Min - - 0.5 MSPS
C
= 0.5 to 2.5V,
fIN = 1kHz Triangular Wave
IN
-1dB - 60 - MHz
RIN = 33Ω
End Point - ±0.3 0.5 LSB
D
L
Potential Difference to V
OT
E
Potential Difference to V
OB
-3dB - 100 - MHz
RT
RB
Note 2 -70 -50 -30 mV
Differential Gain Error DG NTSC 40 IRE Mod Ramp
= 14.3 MSPS
f
Differential Phase Error DP - 1.5 - Degrees
Sampling Delay t
Clamp Offset Voltage E
SD
OC
C
VIN = DC, CIN = 10µF
t
= 2.75µs,
PCW
fC = 14.3 MSPS,
f
= 15.75kHz
CLP
V
= 0.5V 0 20 40 mV
REF
= 2.5V 0 20 40 mV
V
REF
50 65 - MSPS
- +0.7 1.5 LSB
20 40 60 mV
-3- %
-0-ns
Signal-To-Noise Ratio SNR fIN = 100kHz - 45 - dB
f
= 500kHz - 44 - dB
IN
= 1MHz - 44 - dB
f
IN
f
= 3MHz - 43 - dB
IN
f
= 10MHz - 38 - dB
IN
= 25MHz - 32 - dB
f
IN
Spurious Free Dynamic SFDR f
= 100kHz - 51 - dB
IN
f
= 500kHz - 46 - dB
IN
= 1MHz - 49 - dB
f
IN
= 3MHz - 46 - dB
f
IN
= 10MHz - 45 - dB
f
IN
f
= 25MHz - 45 - dB
IN
4-3
HI2302
Electrical Specifications f
= 50 MSPS, AVDD = 5V, DVDD = 3 to 5.5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Continued)
C
PARAMETER SYMBOL TEST CONDITIONS NOTES MIN TYP MAX UNITS
DC CHARACTERISTICS fC = 50 MSPS, AVDD = 5V, DVDD = 5V or 3.3V, VRB = 0.5V, VRT = 2.5V, TA = 25oC
Supply Current I
AD
Analog I
Digital I
Reference Current I
Reference Resistance
(V
- VRB)
RT
R
Self-Bias Voltage V
V
RT -VRB
Input Capacitance C
C
Output Capacitance C
Digital Input Voltage V
Digital Input Current I
+ IDDNTSC Ramp,
AD
DD
REF
REF
C
DIN
C
V
I
Wave Input,
CLE = 0V
Shorts V
RB
Shorts V
VIN, VIN = 1.5V + 0.07V
AI1
V
AI2
RTS
RBS
, VRT, VRB, V
RTS
TEST, CLK, CLP, CLE, OE - - 11 pF
CCP - - 11 pF
AO
D0 to D7, TEST - - 11 pF
DO
AVDD = 4.75 to 5.25V,
IH
DVDD = 3 to 5.5V, TA = -20oC to 75oC
IL
VI = 0V to AVDD,
IH
TA = 20oC to 75oC
IL
and A
and A
DVDD = 5V - 25 36 mA
DVDD = 3.3V - 23 33 mA
-23mA
4.1 5.4 7.7 mA
260 370 480 Ω
VDD
VSS
RBS
RMS
, V
REF
0.52 0.56 0.60 V
1.80 1.92 2.04 V
-15- pF
- - 11 pF
2.2 - - V
- - 0.8 V
CLK -240 - 240 µA
TEST, CLP,
CLE -240 - 40 µA
OE -40 - 240 µA
Digital Output Current I
I
I
I
I
OZH
I
OZL
OH
OL
OH
OL
OE = 0V, DVDD = 5V
TA = 20oC to 75oC
OE = 0V
DVDD = 3.3V
TA = -20oC to 75oC
OE = 3V
DVDD = 3 to 5.5V
TA = -20oC to 75oC
VOH = DVDD - 0.8V - - -2 mA
VOL = 0.4V 4 - - mA
VOH = DVDD- 0.8V - - -1.2 mA
VOL = 0.4V 2.4 - - mA
VOH = DV
DD
-40 - 40 µA
VOL = 0V -40 - 40 µA
TIMING fC = 50 MSPS, AVDD = 5V, DVDD = 5V or 3.3V, VRB = 0.5V, VRT = 2.5V, TA = 25oC
Output Data Delay t
Three-State Output Enable
Time
Three-State Output Enable
Time
t
PHZ
t
PZH,tPZL
Clamp Pulse Width t
PZH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PZH
t
PZL
CPWfC
, t
PLZRL
CL = 15pF
OE = 0V
DVDD = 5V 5.5 9.5 12.0 ns
8.5 ns
DVDD = 3.3V 4.3 11.8 16.3 ns
7.6 ns
RL = 1kΩ
CL = 15pF
OE = 3V➝0V
DVDD = 5V 2.5 4.5 8.0 ns
6.0 ns
DVDD = 3.3V 3.0 7.0 9.0 ns
5.0 ns
= 1kΩ, CL = 15pF
OE = 3V➝0V
DVDD = 5V 3.5 5.5 7.5 ns
DVDD = 3.3V 2.5 5.5 8.0 ns
= 14.3MHz, CIN = 10µF for NTSC Wave Note 4 1.75 2.75 3.75 µs
NOTES:
2. The offset voltage E
is a potential difference between VRB and a point of position where the voltage drops equivalent to1/2 LSB of
OB
the voltage when the output data changes from “00000000” to “00000001”. EOT is a potential difference between VRT and a potential
point where the voltage rises equivalent to1/2 LSB of the voltage when the output data changes from “11111111” to “11111110”.
3. The voltage of up to (AVDD + 0.5V) can be input when DVDD = 3.3V. But the output pin voltage is less than the DVDD voltage. When the
digital output is in the high impedance mode, the IC may be damaged by applying the voltage which is more than the (DVDD + 0.5V)
voltage to the digital output.
4. The clamp pulse width is for NTSC as an example. Adjust the rate to the clamp pulse cycle (1/15.75kHz for NTSC) for other processing
systems to equal the values for NTSC.
4-4
Timing Diagrams
CLOCK 1.3V
t
PW1tPW0
HI2302
ANALOG INPUT
DATA OUTPUT
DATA OUTPUT
CLOCK
0.7 DV
0.3 DV
1.3V
DD
DD
N
N + 1
N - 2N - 3
FIGURE 1A. TIMING CHART
4ns
t
r
t
PLH,
t
PHL
4ns
t
f
90%
10%
N + 2
N + 3
NN - 1
= ANALOG SIGNAL SAMPLING POINT
N + 4
N + 1
3V
0V
OE INPUT
OUTPUT 1
OUTPUT 2
FIGURE 1B. TIMING CHART
tr = 4.5ns tf = 4.5ns
90%
1.3V
t
PLZ
t
PHZ
10%
90%
t
t
PZL
PZH
FIGURE 1C. TIMING CHART
10%
1.3V
1.3V
3V
0V
V
OH
VOL (≠DVSS)
VOH (≠DVDD)
V
OL
4-5
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